MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
DESCRIPTION
The MH8V7245BWZTJ is 8388608-word x 72-bit dynamic
ram module. This consist of nine industry standard 8M x 8
dynamic RAMs in TSOP and one industry standard
EEPROM in TSSOP.
The mounting of TSOPs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
MH8V7245BWZTJ-5
Type name
/RAS
access
time
(max.ns)
/CAS
Address
/OE
Cycle
Power
access
time
(max.ns)
access
time
(max.ns)
access
time
(max.ns)
time
(min.ns)
dissipation
(typ.W)
50
13
25
13
15
84
104
Utilizes industry standard 8M x 8 RAMs in TSOP and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
16.2mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V7245BWZTJ -5 . . . . . . . . . . . . . . . . . . 4.22W(Max)
MH8V7245BWZTJ -6 . . . . . . . . . . . . . . . . . . 3.89W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 9) decoupling capacitors
4096 refresh cycle every 64ms
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
APPLICATION
Main memory unit for computers , Microcomputer memory
3.51
2.93
PIN CONFIGURATION
1pin
10pin
11pin
40pin
41pin
84pin
85pin
94pin
95pin
124pin
125pin
168pin
FRONT SIDE
BACK SIDE
60
15
30
MH8V7245BWZTJ-6
1
Row Address
Column Address
A0 ~ A11
A0 ~ A10
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
PIN CONFIGURATION
NC: No Connect
DU: Don't Use
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
9
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
51
85
86
87
88
89
90
91
92
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
93
127
128
129
130
131
132
133
134
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
135
NC
Vss
DQ32
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
Vss
NC
/CAS5
Vcc
DU
DU
Vss
A1
A3
A5
A7
A9
Vcc
DU
DU
/CAS1
NC
NC
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
Vss
NC
Vcc
/WE0
/CAS0
/RAS0
/OE0
Vss
A0
A2
A4
A6
A8
NC
Vcc
Vcc
DU
DQ22
Vss
/OE2
/RAS2
/CAS2
/CAS3
/WE2
Vcc
NC
NC
CB2
CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
DU
NC
Vss
DQ21
DQ23
DQ26
Vss
DQ24
DQ25
DQ27
Vcc
DQ28
Vss
NC
NC
NC
SDA
SCL
Vcc
DQ30
DQ29
DQ31
DQ54
Vss
DU
/CAS7
DU
Vcc
NC
NC
CB6
CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
DU
NC
Vss
DQ53
DQ55
DQ58
Vss
DQ56
DQ57
DQ59
Vcc
DQ60
Vss
NC
NC
SA0
SA1
SA2
Vcc
DQ62
DQ61
DQ63
A10
A11
2
/CAS4
NC
/CAS6
NC
DQ33
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
3
BLOCK DIAGRAM
DQ32
DQ33
DQ34
DQ35
/RAS0
/WE0
/OE0
DQ36
DQ37
DQ38
DQ39
/RAS2
/CAS4
/WE2
/OE2
A0~A11
D0~D8
. . .
Vcc
Vss
C
0
~C
8
D0~D8
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
SCL
A0
A1
A2
SA2
SA1
SA0
SDA
EEPROM
/CAS5
/CAS6
/CAS7
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQ44
DQ45
DQ46
DQ40
DQ41
DQ42
DQ43
DQ47
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
D2
/RAS
/W
/OE
M5M465805B
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
D1
/CAS1
/RAS
/W
/OE
M5M465805B
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
/CAS2
D3
/RAS
/W
/OE
M5M465805B
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
/CAS3
D4
/RAS
/W
/OE
M5M465805B
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
/CAS0
/RAS
/W
/OE
M5M465805B
D0
D7
/RAS
/W
/OE
M5M465805B
D6
/RAS
/W
/OE
M5M465805B
D8
/RAS
/W
/OE
M5M465805B
/RAS
/W
/OE
M5M465805B
D5
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
4
Serial Presence Detect Table
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
EDO
02
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A10
0B
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x72
48
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
9
RAS# access time of this assembly
-5
50ns
32
10
CAS# access time of this assembly
13ns
0D
11
DIMM Configuration type (Non-parity,Parity,ECC)
ECC
02
12
Refresh Rate/Type
Normal : 15.625us
00
13
DRAM width,Primary DRAM
x8
08
14
Error Checking DRAM data width
x8
08
15 - 20
option
00
21
DRAM Module Attributes
non-buffered,non-registered
00
22 - 26
00
27
Precharge to Active Minimum
-5
30ns
1E
28
Row Active to Row Active Min.
N/A
00
-6
3C
60ns
-5
-6
15ns
0F
Superset Information (may be used in future)
Superset Information (may be used in future)
option
-6
40ns
28
29
RAS to CAS Delay Min
14ns
0E
30
Active to Precharge Min
-5
50ns
32
-6
60ns
3C
31
Density of each bank on module
64MByte
10
32 - 35
00
Superset Information (may be used in future)
option
36 - 61
Superset Information (may be used in future)
option
00
62
SPD Revision
rev 1.0
01
63
Checksum for bytes 0-62
Check sum for -5
AB
Check sum for -6
64 - 71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73 - 90
Manufactures Part Number
MH8V7245BWZTJ-5
4D4838563732343542575A544A2D35202020
91 - 92
Revision Code
PCB revision
rrrr
93 - 94
Manufacturing date
year/week code
yyww
95 - 98
Assembly Serial Number
serial number
ssssssss
99 -125
Manufacture Specific Data
option
00
126
Intetl specification frequency
N/A
00
127
Intel specification CAS# Latency support
N/A
00
128+
Unused storage locations
open
00
MH8V7245BWZTJ-6
CB
4D4838563732343541575A544A2D36202020
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
FUNCTION
The MH8V7245BWZTJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode,
/CAS before /RAS refresh, and delayed-write. The
input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
/RAS
/CAS
Inputs
Input/Output
Refresh
Remark
/W
Row
address address
Column
Output
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
/CAS before /RAS refresh
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
NAC
APD
APD
APD
APD
DNC
DNC
OPN
VLD
IVD
VLD
VLD
OPN
YES
YES
YES
YES
YES
YES
Hyper page
mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
/OE
ACT
DNC
DNC
ACT
ACT
DNC
APD
APD
APD
APD
DNC
DNC
Input
VLD
VLD
VLD
OPN
DNC
OPN
5
Standby
NAC
DNC
DNC
DNC
OPN
NO
DNC
DNC
DNC
Hidden refresh
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
IO
Pd
Topr
Tstg
Parameter
Conditions
Ratings
-0.5~ 4.6
50
9
0~70
-40~125
With respect to Vss
Ta=25°C
Supply voltage
Output current
Power dissipation
Operating temperature
Storage temperature
RECOMMENDED OPERATING CONDITIONS
Unit
Limits
Min
Nom
Max
V
V
V
V
3.6
0
Vcc+0.3
0.8
3.3
0
3.0
0
2.0
-0.3
Parameter
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
Vcc
Symbol
Vss
VIH
VIL
(Ta=0~70°C, unless otherwise noted) (Note 1)
ELECTRICAL CHARACTERISTICS
CAPACITANCE
Symbol
VOH
VOL
IOZ
I I
ICC1 (AV)
ICC2
ICC4(AV)
ICC6(AV)
High-level output voltage
Parameter
Limits
Min
Max
Unit
Typ
Test conditions
Low-level output voltage
Off-state output current
Input current (except /CAS)
Average supply
current
from Vcc operating
(Note 3,4,5)
(Note 3,4,5)
(Note 3,5)
Supply current from Vcc , stand-by
Average supply current
from Vcc
Hyper-Page-Mode
Average supply current from
Vcc
/CAS before /RAS refresh
mode
IOH=-2.0mA
IOL=2.0mA
Q floating 0V
≤
VOUT
≤
Vcc
0V
≤
VIN
≤
Vcc+0.3, Other input pins=0V
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS=WE
≥
Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
/CAS before /RAS refresh cycling
tRC=min.
output open
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VIH
I I (CAS)
Input current (/CAS)
0V
≤
VIN
≤
Vcc+0.3, Other input pins=0V
2.4
0
-10
-90
-20
Vcc
0.4
10
90
20
V
V
uA
mA
mA
mA
mA
Limits
Min
Max
Unit
Typ
pF
pF
pF
CI
CI (/CAS)
C(DQ)
Symbol
Parameter
Test conditions
Input capacitance, /CAS input
Input/Output capacitance,DATA
VI=Vss
f=1MHZ
Vi=25mVrms
Input capacitance, except /CAS input
80
20
15
Unit
V
mA
W
°C
°C
- 5
- 6
- 6
1170
1080
810
1080
9
4.5
Note 1 : All voltage values are with respect to Vss
uA
uA
6
- 6
- 5
900
- 5
1170
C(SCL)
C(SDA)
Input/Output capacitance,SPD DATA
Input capacitance, SPD clock
9
9
C(SA0~3) Input capacitance, SPD address
7
pF
pF
pF
MITSUBISHI LSIs
MH8V7245BWZTJ -5, -6
Preliminary Spec.
MITSUBISHI
ELECTRIC
9/Nov./1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0287-0.0
( / 24 )
Specifications subject to
change without notice.
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
SWITCHING CHARACTERISTICS
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD
≥
tRCD(max), tASC
≥
tASC(max) and tCP
≥
tCP(max).
9: Assumes that tRCD
≤
tRCD(max) and tRAD
≤
tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD
≥
tRAD(max) and tASC
≤
tASC(max).
11: Assumes that tCP
≤
tCP(max) and tASC
≥
tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT
≤
I ± 10uA I )
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both /RAS and /CAS go to high.
Limits
Parameter
Symbol
Unit
- 6
Min
Max
tCAC
tRAC
tAA
tCPA
tOEA
tOHR
tCLZ
Access time from /CAS
Access time from /RAS
Column address access time
Access time from /CAS precharge
Output hold time from /RAS
Output low impedance time /CAS low
Access time from /OE
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 7)
ns
ns
ns
ns
ns
ns
ns
ns
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits
Min
Max
Parameter
Symbol
Unit</