MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
DESCRIPTION
The MH32S64PHB is 3354432 word X 64 bit
Synchronous DRAM module. This consists of sixteen
industry standard 16Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Clock frequency 100MHz
single 3.3V±0.3V power supply
Fully synchronous operation referenced to clock rising
edge
Burst length- 1/2/4/8/Full Page(programmable)
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
APPLICATION
PC main memory
Auto precharge / All bank precharge controlled by A10
Burst type- sequential / interleave(programmable)
Column access - random
LVTTL Interface
Auto refresh and Self refresh
4096 refresh cycle /64ms
1pin
10pin
11pin
40pin
41pin
84pin
Front side
85pin
94pin
95pin
124pin
125pin
168pin
Back side
1
Utilizes industry standard 16M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
Frequency
CLK Access Time
-8
100MHz
6.0ns(CL=3)
(Component SDRAM)
6.0ns(CL=3)
100MHz
-7
-10
8.0ns(CL=3)
100MHz
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
2
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NAME
PIN NO.
PIN NAME
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
/S2
87
DQ33
129
/S3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VDD
48
NC
90
VDD
132
NC
7
DQ4
49
VDD
91
DQ36
133
VDD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
NC
94
DQ39
136
NC
11
DQ8
53
NC
95
DQ40
137
NC
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VDD
101
DQ45
143
VDD
18
VDD
60
DQ20
102
VDD
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
NC
63
NC
105
NC
147
NC
22
NC
64
VSS
106
NC
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
VDD
68
VSS
110
VDD
152
VSS
27
/WE0
69
DQ24
111
/CAS
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
/S0
72
DQ27
114
/S1
156
DQ59
31
NC
73
VDD
115
/RAS
157
VDD
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VDD
82
SDA
124
VDD
166
SA1
41
VDD
83
SCL
125
CK1
167
SA2
42
CK0
84
VDD
126
NC
168
VDD
NC = No Connection
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
3
Block Diagram
CK0
Vcc
Vss
D0 - D15
D0 - D15
/S0
/S2
DQMB0
DQMB4
DQMB1
DQMB5
DQMB2
DQMB6
DQMB3
DQMB7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CKE0
D0 - D7
/RAS
D0 - D15
/CAS
D0 - D15
/WE
D0 - D15
BA0,BA1,A<11:0>
D0 - D15
CK1
CK,DQ=10
Ω
4SDRAMs+3.3pF cap.
4SDRAMs+3.3pF cap.
CK2
CK3
4SDRAMs+3.3pF cap.
4SDRAMs+3.3pF cap.
CKE1
D8 - D15
3.3V
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D1
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D8
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D9
I/O 4
I/O 5
I/O 6
I/O 7
/S1
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D4
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D5
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D12
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D13
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D2
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D3
I/O 4
I/O 5
I/O 6
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D10
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D6
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D7
I/O 4
I/O 5
I/O 6
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D14
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
DQM /CS
D15
I/O 4
I/O 5
I/O 6
I/O 7
I/O 7
/S3
10K
SA0 SA1 SA2
SERIAL PD
SCL
SDA
A0
A1
A2
WP
47K
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Defines # bytes written into serial memory at module mfgr
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM
04
3
# Row Addresses on this assembly
A0-A11
0C
4
# Column Addresses on this assembly
A0-A9
0A
5
# Module Banks on this assembly
2BANK
02
6
Data Width of this assembly...
x64
40
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
LVTTL
01
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
A0
Cycle time for CL=3
10
SDRAM Access from Clock
6ns
60
tAC for CL=3
8ns
80
11
DIMM Configuration type (Non-parity,Parity,ECC)
non-parity
00
12
Refresh Rate/Type
self refresh(15.625uS)
80
13
SDRAM width,Primary DRAM
x8
08
14
Error Checking SDRAM data width
N/A
00
15
Minimum Clock Delay,Back to Back Random Column Addresses
1
01
16
Burst Lengths Supported
1/2/4/8/Full page
8F
17
# Banks on Each SDRAM device
4bank
04
18
CAS# Latency
2/3
06
19
CS# Latency
0
01
20
Write Latency
0
01
21
SDRAM Module Attributes
non-buffered,non-registered
00
22
SDRAM Device Attributes:General
Precharge All,Auto precharge
0E
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
13ns
D0
24
SDRAM Access form Clock(2nd highest CAS latency)
7ns
70
tAC for CL=2
8ns
80
25
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
N/A
00
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
20ns
14
28
Row Active to Row Active Min.
20ns
14
-7,-8
-10
10ns
-8
-8
-10
-7,-8
-7
10ns
A0
6ns
60
-7
29
RAS to CAS Delay Min
20ns
14
-7,-8
30
Active to Precharge Min
50ns
32
60ns
3C
-7,-8
-10
4
-7,-8,-10
15ns
F0
-10
30ns
1E
-10
-7,-8,-10
30ns
1E
-10
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
Serial Presence Detect Table II
31
Density of each bank on module
128MByte
20
36-61
Superset Information (may be used in future)
option
00
62
SPD Revision
rev 1
01
63
Checksum for bytes 0-62
Check sum for -8
57
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
1CFFFFFFFFFFFFFF
72
Manufacturing location
Miyoshi,Japan
01
Tajima,Japan
02
NC,USA
03
Germany
04
73-90
Manufactures Part Number
MH32S64PHB-8
91-92
Revision Code
PCB revision
rrrr
93-94
Manufacturing date
year/week code
yyww
95-98
Assembly Serial Number
serial number
ssssssss
99-125
Manufacture Specific Data
option
00
126
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
06
128+
Unused storage locations
open
00
MH32S64PHB-10
32
Command and Address signal input setup time
-7,-8
-10
2ns
N/A
20
00
20
00
33
Command and Address signal input hold time
-7,-8
-10
1ns
N/A
10
00
34
Data signal input setup time
-7,-8
-10
2ns
N/A
35
Data signal input hold time
-7,-8
-10
1ns
N/A
10
00
-7,-8
-10
rev 1.2A
12
Check sum for -7
17
MH32S64PHB-7
4D4833325336345048422D37202020202020
-7,-8
-10
66MHz
66
-7
-10
FF
5
Check sum for -10
54
CL=2/3,AP,CK0-3
CL=2/3
4D4833325336345048422D38202020202020
4D4833325336345048422D31302020202020
-8
FD
CL=3,AP,CK0-3
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0-3)
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE
Input
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
DQ0-63
Input/Output Data In and Data out are referenced to the rising edge of
CK
DQMB0-7
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
Vdd,Vss
Power Supply Power Supply for the memory mounted module.
SCL
SDA
SA0-3
Input
Output
Input
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
6
CK
(CK0 ~ CK3)
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
BASIC FUNCTIONS
/S
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
CK
define basic commands
The MH32S64PHB provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
Activate(ACT) [/RAS =L, /CAS = /WE =H]
Read(READ) [/RAS =H,/CAS =L, /WE =H]
Write(WRITE) [/RAS =H, /CAS = /WE =L]
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
ACT command activates a row in an idle bank indicated by BA.
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
7
MH32S64PHB -7,-8,-10
214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 55 )
MITSUBISHI
ELECTRIC
11/Jan. /1999
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0301-0.0
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/S
/RAS /CAS
/WE BA0,1
A10
A0-9
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Bank
PREA
H
X
L
L
H
L
X
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with Auto-
Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry