TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
2-A Low-Dropout Voltage Regulator
D
Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed
Output and Adjustable Versions
D
Open Drain Power-On Reset With 100-ms
Delay (TPS752xxQ)
D
Open Drain Power-Good (PG) Status
Output (TPS754xxQ)
D
Dropout Voltage Typically 210 mV at 2 A
(TPS75233Q)
D
Ultra Low 75-
µ
A Typical Quiescent Current
D
Fast Transient Response
D
2% Tolerance Over Specified Conditions
for Fixed-Output Versions
D
20-Pin TSSOP (PWP) PowerPAD
™
Package
D
Thermal Shutdown Protection
description
The TPS752xxQ and TPS754xxQ are low dropout regulators with integrated power-on reset and power good
(PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210
mV (TPS75233Q, TPS75433Q). Quiescent current is 75
µ
A at full load and drops down to 1
µ
A when the device
is disabled. TPS752xxQ and TPS754xxQ are designed to have fast transient response for larger load current
changes.
TJ – Junction Temperature –
°
C
–40
10
110
60
– Dropout V
oltage – mV
V
DO
TPS75x33Q
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
300
160
250
200
150
100
50
0
IO = 0.5 A
IO = 1.5 A
IO = 2 A
t – Time – ms
TPS75x33Q
LOAD TRANSIENT RESPONSE
I – Output Current –
A
O
V
O
– Change in
∆
Output
V
oltage – mV
–150
3
2
1
4
5
7
6
8
9
10
0
0
0
50
–50
IL=2 A
CL=100
µ
F (Tantalum)
VO=3.3 V
–100
2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2000, Texas Instruments Incorporated
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWP PACKAGE
(TOP VIEW)
GND/HEATSINK
NC
IN
IN
EN
RESETor PG
†
FB/SENSE
OUTPUT
OUTPUT
GND/HEATSINK
GND/HEATSINK
NC
NC
GND
NC
NC
NC
NC
NC
GND/HEATSINK
NC – No internal connection
† PG is on the TPS754xx and RESET is on the TPS752xx
PowerPAD is a trademark of Texas Instruments.
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV
at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 75
µ
A over the full range of output current, 1 mA to 2 A). These two key specifications
yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features
a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent
current to 1
µ
A at T
J
= 25
°
C.
The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and
microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ
monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms
delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load
condition) of its regulated voltage.
The TPS754xxQ has a power good terminal (PG) as an active high, open drain output, which can be used to
implement a power-on reset or a low-battery indicator.
The TPS752xxQ or the TPS754xxQ are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in
an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as
a maximum of 2% over line, load, and temperature ranges. The TPS752xxQ and the TPS754xxQ families are
available in 20 pin TSSOP (PWP) packages.
AVAILABLE OPTIONS
TJ
OUTPUT VOLTAGE
TSSOP (PWP)
TJ
(TYP)
RESET
PG
3.3 V
TPS75233QPWP
TPS75433QPWP
2.5 V
TPS75225QPWP
TPS75425QPWP
– 40
°
C to 125
°
C
1.8 V
TPS75218QPWP
TPS75418QPWP
1.5 V
TPS75215QPWP
TPS75415QPWP
Adjustable 1.5 V to 5 V
TPS75201QPWP
TPS75401QPWP
The TPS75x01 is programmable using an external resistor divider (see application
information). The PWP package is available taped and reeled. Add an R suffix to the device
type (e.g., TPS75201QPWPR) to indicate tape and reel.
† See application information section for capacitor selection details.
PG or
RESET
OUT
OUT
4
3
5
IN
IN
EN
GND
17
6
8
9
VI
0.22
µ
F
PG or RESET Output
VO
47
µ
F
+
CO†
SENSE
7
Figure 1. Typical Application Configuration (For Fixed Output Options)
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
functional block diagram—adjustable version
100 ms Delay
(for RESET Option)
_
+
Vref = 1.1834 V
OUT
FB
EN
GND
PG or RESET
_
+
IN
R1
R2
External to the device
functional block diagram—fixed-voltage version
_
+
Vref = 1.1834 V
OUT
EN
GND
R1
R2
PG or RESET
_
+
IN
SENSE
100 ms Delay
(for RESET Option)
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Terminal Functions (TPS752xxQ)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
EN
5
I
Enable Input
FB/SENSE
7
I
Feedback input voltage for adjustable device (sense input for fixed-voltage option)
GND
17
Regulator ground
GND/HEATSINK
1, 10, 11, 20
Ground/heatsink
IN
3, 4
I
Input voltage
NC
2, 12, 13, 14,
15, 16, 18, 19
No connection
OUTPUT
8, 9
O
Regulated output voltage
RESET
6
O
Reset output
Terminal Functions (TPS754xxQ)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
EN
5
I
Enable Input
FB/SENSE
7
I
Feedback input voltage for adjustable device (sense input for fixed-voltage option)
GND
17
Regulator ground
GND/HEATSINK
1, 10, 11, 20
Ground/heatsink
IN
3, 4
I
Input voltage
NC
2, 12, 13, 14,
15, 16, 18, 19
No connection
OUTPUT
8, 9
O
Regulated output voltage
PG
6
O
Power good output
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TPS752xxQ RESET timing diagram
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
Vres
(see Note A)
Vres
t
t
t
VO
Threshold
Voltage
RESET
Output
100 ms
Delay
100 ms
Delay
Output
Undefined
Output
Undefined
VIT +(see Note B)
VIT –(see Note B)
VIT –(see Note B)
VIT +(see Note B)
Less than 5% of the
output voltage
NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TPS754xxQ PG timing diagram
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
VI
VPG
(see Note A)
VPG
t
t
t
VO
Threshold
Voltage
PG
Output
Output
Undefined
Output
Undefined
VIT +(see Note B)
VIT –(see Note B)
VIT –(see Note B)
VIT +(see Note B)
NOTES: A. VPG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC standards for
semiconductor symbology.
B. VIT –Trip voltage is typically 17% lower than the output voltage (83%VO) VIT– to VIT+ is the hysteresis voltage.
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating junction temperature range
(unless otherwise noted)
Input voltage range
‡
, V
I
– 0.3 V to 5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN
–0.3 V to 16.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum RESET voltage (TPS752xxQ)
16.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum PG voltage (TPS754xxQ)
16.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current
Internally limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, V
O
(OUTPUT, FB)
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See dissipation rating tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
– 40
°
C to 125
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
– 65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, HBM
2 kV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES
PACKAGE
AIR FLOW
(CFM)
TA < 25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
TA = 70
°
C
POWER RATING
TA = 85
°
C
POWER RATING
PWP§
0
2.9 W
23.5 mW/
°
C
1.9 W
1.5 W
PWP§
300
4.3 W
34.6 mW/
°
C
2.8 W
2.2 W
PWP¶
0
3 W
23.8 mW/
°
C
1.9 W
1.5 W
PWP¶
300
7.2 W
57.9 mW/
°
C
4.6 W
3.8 W
§ This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in
×
5-in PCB, 1 oz. copper, 2-in
×
2-in coverage
(4 in2).
¶ This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in
×
2-in PCB, 1 oz. copper with layers 1,
2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002.
recommended operating conditions
MIN
MAX
UNIT
Input voltage, VI
#
2.7
5
V
Output voltage range, VO
1.5
5
V
Output current, IO
0
2.0
A
Operating virtual junction temperature, TJ
– 40
125
°
C
# To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range (T
J
= –40
°
C to
125
°
C), V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = 0 V, C
O
= 47
µ
F (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Adjustable
1.5 V
≤
VO
≤
5 V,
TJ = 25
°
C
VO
j
Voltage
1.5 V
≤
VO
≤
5 V
0.98VO
1.02VO
1 5 V Output
TJ = 25
°
C,
2.7 V < VIN < 5 V
1.5
1.5 V Output
2.7 V < VIN < 5 V
1.470
1.530
Output voltage
1 8 V Output
TJ = 25
°
C,
2.8 V < VIN < 5 V
1.8
V
g
(see Notes 1 and 3)
1.8 V Output
2.8 V < VIN < 5 V
1.764
1.836
V
2 5 V Output
TJ = 25
°
C,
3.5 V < VIN < 5 V
2.5
2.5 V Output
3.5 V < VIN < 5 V
2.450
2.550
3 3 V Output
TJ = 25
°
C,
4.3 V < VIN < 5 V
3.3
3.3 V Output
4.3 V < VIN < 5 V
3.234
3.366
Quiescent current (GND current) (see Note 1)
TJ = 25
°
C,
See Note 3
75
µ
A
Quiescent current (GND current) (see Note 1)
See Note 3
125
µ
A
Output voltage line regulation (
∆
VO/VO
)
VO + 1 V < VI
≤
5 V,
TJ = 25
°
C,
0.01
%/V
g
g
(
O
O
)
(see Notes 1 and 2)
VO + 1 V < VI < 5 V
0.1
%/V
Load regulation (see Note 3)
1
mV
Output noise voltage
BW = 300 Hz to 50 kHz, VO = 1.5 V
CO = 100
µ
F,
TJ = 25
°
C
60
µ
Vrms
Output current Limit
VO = 0 V
3.3
4.5
A
Thermal shutdown junction temperature
150
°
C
Standby current
EN = VI,
TJ = 25
°
C,
1
µ
A
Standby current
EN = VI
10
µ
A
FB input current
TPS75x01Q
FB = 1.5 V
–1
1
µ
A
High level enable input voltage
2
V
Low level enable input voltage
0.7
V
Power supply ripple rejection (see Note 2)
f = 100 Hz,
CO = 100
µ
F,
TJ = 25
°
C,
See Note 1, IO = 2 A
60
dB
Minimum input voltage for valid
RESET
IO(RESET) = 300
µ
A,
V(RESET)
≤
0.8 V
1
1.3
V
Trip threshold voltage
VO decreasing
92
98
%VO
Reset
(TPS752xxQ)
Hysteresis voltage
Measured at VO
0.5
%VO
(TPS752xxQ)
Output low voltage
VI = 2.7 V,
IO(RESET) = 1 mA
0.15
0.4
V
Leakage current
V(RESET) = 5 V
1
µ
A
RESET time-out delay
100
ms
NOTES:
1. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 5V.
2. If VO
≤
1.8 V then Vimin = 2.7 V, Vimax = 5 V:
Line Reg. (mV)
+
% V
V
O
V
imax
*
2.7 V
100
1000
If VO
≥
2.5 V then Vimin = VO + 1 V, Vimax = 5 V:
Line Reg. (mV)
+
% V
V
O
V
imax
*
V
O
)
1 V
100
1000
3. IO = 1 mA to 2 A
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
9
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range (T
J
= –40
°
C to
125
°
C), V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = 0 V, C
O
= 47
µ
F (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum input voltage for valid PG
IO(PG) = 300
µ
A
V(PG)
≤
0.8 V
1.1
1.3
V
PG
Trip threshold voltage
VO decreasing
80
86
%VO
PG
(TPS754xxQ)
Hysteresis voltage
Measured at VO
0.5
%VO
(TPS754xxQ)
Output low voltage
IO(PG) = 1 mA
0.15
0.4
V
Leakage current
V(PG) = 5.5 V
1
µ
A
Input current (EN)
EN = VI
–1
1
µ
A
Input current (EN)
EN = 0 V
–1
0
1
µ
A
High level EN input voltage
2
V
Low level EN input voltage
0.7
V
Dropout voltage (3.3 V Output) (see Note 4)
IO = 2 A,
TJ = 25
°
C
VI = 3.2 V,
210
mV
g (
) (
)
IO = 2 A,
VI = 3.2 V
400
NOTE 4: IN voltage equals VO(Typ) – 100 mV; TPS75x15Q, TPS75x18Q and TPS75x25Q dropout voltage limited by input voltage range
limitations (i.e., TPS75x33Q input voltage needs to drop to 3.2 V for purpose of this test).
Table of Graphs
FIGURE
VO
Output voltage
vs Output current
2, 3
VO
Output voltage
vs Junction temperature
4, 5,
Ground current
vs Junction temperature
6
Power supply ripple rejection
vs Frequency
7
Output spectral noise density
vs Frequency
8
Zo
Output impedance
vs Frequency
9
VDO
Dropout voltage
vs Input voltage
10
VDO
Dropout voltage
vs Junction temperature
11
Line transient response
12, 14
Load transient response
13, 15
VO
Output voltage
vs Time
16
Equivalent series resistance (ESR)
vs Output current
18, 19
TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET
TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD
FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
SLVS242 – MARCH 2000
10
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
IO – Output Current – mA
TPS75x33Q
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.303
3.297
3.301
3.299
3.295
500
1500
3.305
0
– Output V
oltage – V
V
O
1000
VO
2000
VI = 4.3 V
TJ = 25
°
C
Figure 3
IO – Output Current – mA
TPS75x15Q
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.502
1.499
1.501
1.5
1.498
1.503
0
– Output V
oltage – V
V
O
1.497
500
1500
1000
2000
VO
VI = 2.7 V
TJ = 25
°
C
TJ – Junction Temperature –
°
C
TPS75x33Q
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
– Output V
oltage – V
V
O
Figure 4
3.31
–50
0
3.33
150
3.35
3.29
50
100
3.25
3.27
1 mA
3.23
3.37
2 A
TJ – Junction Temperature –
°
C
TPS75x15Q
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
– Output V
oltage – V
V
O
Figure 5
1.48
–40
10
1.50
110
60
160
1.52