DOLBY DIGITAL DECODER

Chapter 1

Features

This Audio Decoder for Dolby Digital (AC-3)

M65863FP is a single device. The device decodes AC-3

bitstreams into PCM audio. Dolby Digital (AC-3) is a multi-channel audio coding algorithm developed by

Dolby Laboratories, Inc.

• Decoding

1) 5.1 ch AC-3 bitstream

2) Dolby Pro Logic

encoded 2ch Dolby Digital (AC-3) bitstream

3) Dolby Pro Logic encoded 2ch PCM data

• All input combinations from 1 to 5.1 channels

• Output : mono 5.1 surround

• Sampling rates : 32kHz, 44.1 kHz, 48 kHz and 96 kHz (96 kHz is for linear PCM only)

• Supports a maximum bit rate of 640 kbps at a full service (up to 448 kbps when 32 kHz sampling rates)

• 2 DIR (Digital Audio Interface Receiver)/ADC input interfaces

• Serial input bitstream interface for DEMUX

• PCM output interface

Standard 3-wire DAC output interface (data,clock,LR clock), 16/18/20/24 bit DAC word size

• Supports IEC958 digital audio output for Dolby Digital (AC-3) data stream

• I

interface and clocked serial (4 line) interface for host microcontroller

• Generates audio test noise

• 2nd DSP I/F (twice higher PCM transfer rate)

• Controllable dynamic range compression

• Programmable center and surround channel delays

• Dialogue level control

• No external memory required (M65863FP doos not have memory space for surround delay)

M65863FP

MCU

I C/Clocked serial

DAC

DIR

ADC

IEC958

Analog

IEC958

DSP

Figure 1.1 M65863FP Configuration Diagram (DIR I/F)

Dolby, Dolby Digital (AC-3), and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corp.

Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA 94111, USA, (415) 558-

0200, from whom licensing and application information must be obtained.

Phillips Semiconductors, "I

C bus specification",January,1992

Product Note

M65863FP

April 1998

Dolby Digital Decoder

MITSUBISHI ELECTRIC CORPORATION

Chapter 2

Device Overview

The figure 2.1 show the M65863FP I/O interface.

MCU Interface

Processor

Clock

DAC/DSP

Interface

Digital Audio

Interface

Audio Master Clock

Interface

Main/Sub Chip

Interface

TOP VIEW

(package 68P6S-A)

DOLR

DOCW

DOSS

GND

ACLK2

ADATA2

ALRCK2

VDD5V

DEMPH

VDD5V

GND

MCLKI

MCLKO

HMCLKO

VDD5V

DIRX

DOTX

GND

VDD3V

ACLK1

ADATA1

ALRCK1

GND

_AMUT

ACLKS

ADATA

ADVLDS

_ADREQ

SYNCRST

RSYCREQ

CCLK

CDATA

ASOUT

VDD5V

DIRSTAT

_RST

HSCL/SCK

HSDA/SI

NC/_SS

MCUSEL

NC/SO

GND

VDD5V

DECSTAT

CHIPMOD

BCLK

LRCK

2LRCK

PLL3

PLL2

VDD3V

PLLGND

MCLKSI[1]

MCLKSI[0]

VDD5V

PLL1

PCLK

PVCO

VDD3V

PLLVCC

GND

2BCLK

DEMUX

Interface

DIR/ADC

Interface

Audio Master

Clock Selection

GND

PIN1

PIN68

PIN34

PIN35

Figure 2.1 M65863FP I/O Interface

Product Note

M65863FP

April 1998

Dolby Digital Decoder

MITSUBISHI ELECTRIC CORPORATION

Chapter 3

Input/Output Pins

Table 3.1 shows input/output pins. "low active" pins are added "_" to tail of pin name (ex. _AERR).

Table 3.1 Input/Output Pins

No.

Pin Name

Pins I/O

Out Voltage

Description

1 VDD5V

Voltage supply 5V (I/O)

2 ASOUT

I/O 2mA

Indication of audio data output timing (main chip output / sub chip

input)

3 CDATA

I/O 2mA

Dynamic range compression data input from sub chip / output to main

chip

4 CCLK

I/O 2mA

Dynamic range compression data transfer clock input from sub chip /

output to main chip

5 RSYCREQ

2mA

Indication of sync word lock condition

6 SYNCRST

Sync world detection start signal

7 ADVLDS

Indication of valid data

8 ADATAS

Data input from DEMUX

9 ACLKS

Clock input from DEMUX

10 VDD3V

Voltage supply 3.3V

11 GND

GND

12 VDD5V

13 _ADREQ

2mA

Data Request for DEMUX

14 _AMUTE

Mute sound0 (0 : Mute ON, 1 : Mute OFF)

15 DOTX

2mA

Digital audio interface IEC958 output

16 DIRX

Digital audio interface IEC958 input

17 ALRCK1

L/R clock from DIR/ADC

18 ACLK1

Data from DIR

19 ADATA1

Bit clock from DIR/ADC

20 GND

21 VDD5V

22 DEMPH

De-emphasis control

23 ALRCK2

L/R clock from DIR/ADC

24 ACLK2

Bit clock from DIR

25 ADATA2

Data from DIR

26 MCLKI

Audio master clock input

27 GND

28 VDD5V

29 MCLKO

Audio master clock output

30 HMCLKO

Audio master clock output (1/2MCLKI)

31 DOLR

2mA

PCM output for L ch and R ch

32 DOCW

2mA

PCM output for C channel SW ch

33 DOSS

2mA

PCM output for SL ch and SR ch

Product Note

M65863FP

April 1998

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No.

Pin Name

Pins I/O

Out Voltage

Description

34 GND

35 VDD5V

36 BCLK

4mA

Bit clock for PCM output

37 LRCK

4mA

LR clock for PCM output

38 2LRCK

2mA

LR clock for 2nd DSP

39 2BCLK

2mA

Bit clock for 2nd DSP

40 VDD3V

41 PLLGND

GND for PLL

42 PVCO

P3.3

Processor clock output for crystal

43 PCLK

P3.3

Processor clock input

44 PLL1

I/O

45 PLL2

I/O

46 PLL3

I/O

47 PLLVCC

P3.3

VDD for PLL

48 GND

49 GND

50 GND

51 GND

52 MCLSI[0]

Selection of audio master clock

([0:1] = 00 : 512fs, 01 : 384fs, 10 : 256fs, 11 : Reserved)

53 MCLSI[1]

54 VDD3V

55 VDD5V

56 _RST

Reset

57 CHIPMOD

Chip mode

58 DECSTAT

2mA

Decode status (Normal : 1, Error : 0)

59 GND

60 DIRSTAT

2mA

(AC-3 : 1, PCM : 0)

61 MCUSEL

MCU I/F Selection (Clocked serial : 0, I2C : 1)

62 VDD5V

63 _NC/SS

64 ADR/SO

4mA

65 HSDA/SI

I/O 4mA

66 HSCL/SCK

I/O 4mA

67 GND

68 GND

Note)

: Degital 5V I/O

P3.3

: PLL oscillation I/O

ACLK1

Bit clock input for DIR/ADC input (Line 1).

ADATA1

Data input for DIR/ADC interface (Line 1). Latched at the rising edge of ACLK1.

ALRCK1

LR clock input for DIR/ADC interface (Line 1).

ACLK2

Bit clock input for DIR/ADC input (Line 2).

ADATA2

Data input for DIR/ADC interface (Line 2). Latched at the rising edge of ACLK2.

ALRCK2

LR clock input for DIR/ADC interface (Line 2)

ACLKS

Clock for DEMUX interface.

Product Note

M65863FP

April 1998

Dolby Digital Decoder

MITSUBISHI ELECTRIC CORPORATION

ADATAS

Data input for DEMUX interface. Latched at the rising edge of ACLKS.

_AVLDS

Data enable instruction for DEMUX interface. Data is input when this signal is enabled

(0).

_ADREQ

Used in the data transmission control of DEMUX interface.

SYNCRST

Synchronization lock cancel signal. M65863FP starts detecting sync word when this

signal is disabled.

RSYCREQ

SYNCRST request signal which is enabled when M65863FP comes out of

synchronization.

_AMUTE

Audio mute output signal. Output is muted when this signal is enabled (0). This signal is

valid for both DIR/ADC interface and DEMUX interface.

DOLR

PCM output terminal. When control register dspif is 0, L and R channel data are output.

When dspif is 1, L, R, C and SW channel data are output.

DOCW

PCM output terminal. When control register dspif is 0, C and SW channel data are

output. When dspif is 1, SL and SR channel data are output.

DOSS

PCM output terminal. When control register dspif is 0, SL and SR channel data are

output.

BCLK

Bit clock output.

LRCK

LR clock output.

2BCLK

Double-rate bit clock. Used in DSP interface.

2LRCK

Double-rate LR clock. Used in DSP interface.

CHIPMOD

Specifies the chip mode. Decodes the main service when 0, and decodes the associate

service when 1. Select decoding of main service when it is not necessary to decode dual

streams.

CCLK

Transmission clock used in data transmission between main and sub chips during dual-

stream decoding. Sub chip becomes the clock master. This is valid only when control

CDATA

Data transmission line from sub chip to main chip during dual-stream decoding. This is

valid only when control register asmix is 1.

ASOUT

Synchronization signal for dual-stream output. CCLK, CDATA and ASOUT terminals

may be open when dual-stream decoding is not required (when control register asmix is

0).

MCUSEL

Selects which of synchronized serial and I

C is to be used as MCU interface.

Synchronized serial is selected when this is 0, and I

C is selected when 1.

HSCL/SCK

Becomes data transmission clock input in either case of I

C or synchronized serial.

HSDA/SI

Becomes data input/output terminal in the case of I

C, and data input terminal in the case

of synchronized serial.

ADR/SO

Becomes chip address selection terminal in the case of I

C, and data output terminal in

the case of synchronized serial.

_NC/SS

Becomes enable signal in the case of synchronized serial. In the case of I

C, this may be

left open because it is not used.

MCLKI

Audio master clock input.

MCLSI [0:1]

Indicates whether the audio master clock which is input from MCLKI is 512 fs, 384 fs or

256 fs. Only 384 fs or 256 fs can be selected when the sampling frequency is 96kHz.

MCLKO

Audio master clock output which gives MCLKI as through-output.

Product Note

M65863FP

April 1998

Dolby Digital Decoder

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HMCLKO

Audio master clock output which gives MCLKI at 1/2-divided frequency.

DIRX

Digital audio interface IEC958 input.

DOTX

Digital audio interface IEC958 output.

DEMPH

Enabled when control register demph is 10, turning de-emphasis ON when this is 0, and

de-emphasis OFF when 1.

DECSTAT

Indicates the current decoding status: 1 during normal decoding and 0 at a time of error.

DIRSTAT

Indicates the current DIR input stream: 1 in the case of Dolby Digital AC-3 input, 0 in the

case of PCM input.

Product Note

M65863FP

April 1998

Dolby Digital Decoder

MITSUBISHI ELECTRIC CORPORATION

Chapter 4

Registers

Table 4.1 shows the registers overview.

Table 4.1 Registers Overview

Byte

Description

Dolby Digital (AC-3) Bitstream Information

• Synchronization Information

• Bitstream Information

IEC958 Burst Information

• IEC958 Burst Information

Status

• CRC Result

• Synchronization Condition

• Pointer to the input buffer

Control

• I/O Signals Control

• Decoding Status Control

• Channel delay control

• Dynamic Range Control

• Pro Logic Control

• Calibration Noise Control

• Mute Control

• IEC958 Category code input

Test

• Monitor of overflow and underflow

• Register Address

Dual stream (main effect and Associate service) can be decoded with 2 M65863FP. In the case, the

associate service) are different.

In the following sections, only the register address for a main chip will be shown. For a sub chip you

should add h'40 to the corresponding register address for a main chip. For a example, the address of the

control register "synclock" is h'14 for a main chip and h'54 for a sub chip. In this may, the address range

will be following.

Main chip

: h'00~h'3f

Sub chip

: h'40~h'7f

Product Note

M65863FP

April 1998

Dolby Digital Decoder

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4.1

Dolby Digital (AC-3) Bitstream Information Registers

Table 4.2 shows Dolby Digital (AC-3) bitstream information registers.

Table 4.2 Dolby Digital (AC-3) Bitstream Information Registers

bit

Address

R/W

h'00

frmsizecod

fscod

h'01

bsmod

bsid

h'02

origbs

copyrightb

lfeon

dsurmod

acmod

h'03

compre

dynrnge

dialnorm

h'04

compr

h'05

langcod

h'06

dynrng

h'07

audprodie

roomtyp

mixlevel

h'08

compr2e

dynrng2e

dialnorm2

h'09

compr2

h'0A

langcod2

h'0B

dynrng2

h'0C

audprodi2e

roomtyp2

mixlevel2

address h'00

Sample Rate Code (fscod)

2 bits

This field indicates sampling rate according to the following table.

fscod

Sampling Rate

0 0

48 kHz

0 1

44.1 kHz

1 0

32 kHz

1 1

Reserved

Frame Size Code(frmsizecod)

6 bits

This field indicates nominal bit rate. This code is used along with the sample rate code to determine the

number of bytes per frame.

address h'01

Bitstream Identification (bsid)

5 bits

This field contains the version number of the coder syntax.

M65863FP only supports 0 to 8.

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M65863FP

April 1998

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Bitstream Mode(bsmod)

3 bits

This field indicates the type of service that the bitstream conveys as defined by the following table.

bsmod

acmod

Type of Service

0 0 0

any

Main audio service : complete main (CM)

0 0 1

any

Main audio service : music and effects (ME)

0 1 0

any

Associated service : visually impaired (VI)

0 1 1

any

Associated service : hearing impaired (HI)

1 0 0

any

Associated service : dialogue (D)

1 0 1

any

Associated service : commentary (C)

1 1 0

any

Associated service : emergency (E)

1 1 1

0 0 1

Associated service : voice-over (VO)

1 1 1

0 1 0 ~ 1 1 1 Main audio service : karaoke

address h'02

Audio Coding Mode (acmod)

3 bits

This field indicates channel array for audio service.

acmod

Audio Coding Mode

Channel Array Ordering

0 0 0

1+1

[Ch1,Ch2]

0 0 1

1/0

[C]

0 1 0

2/0

[L,R]

0 1 1

3/0

[L,C,R]

1 0 0

2/1

[L,R,S]

1 0 1

3/1

[L,C,R,S]

1 1 0

2/2

[L,R,SL,SR]

1 1 1

3/2

[L,C,R,SL,SR]

Dolby Surround Mode (dsurmod)

2 bits

When acmod is 010, these bits indicate whether or not the program has been encoded in Dolby Surround.

dsurmod

Indication

0 0

Not indicated

0 1

NOT Dolby Surround encoded

1 0

Dolby Surround encoded

1 1

Reserved

Low Frequency Effects ch On (lfeon)

1 bit

If this bit has a value of 1, the sub-woofer channel is on. If this bit has a value of 0, the sub-woofer

channel is off.

1 bit

If this bit has a value of 1, the bitstream is protected by copyright. If this bit has a value of 0, the bitstream

is not protected by copyright.

Original Bitstream (origbs)

1 bit

If this bit has a value of 1, this bitstream is an original bitstream. If this bit has a value of 0, this bitstream

is a copy of another bitstream.

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April 1998

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address h'03

Dialogue Normalization (dialnorm)

5 bits

This field contains how far the average dialogue level is below digital 100%.

Dynamic Range Gain Word Exists (dynrnge)

1 bit

If this bit is a 1, this bitstream has dynamic range gain word which can use dynamic range compression.

Heavy dynamic range Compression Code Exists (compre)

1 bit

If this bit is a 1, this bitstream has compression gain word which can use heavy dynamic range

compression.

address h'04

Compression Gain Word (compr)

8 bits

If compre is a 1, this field indicates scale for the reproduced audio level in order to reproduce a very

narrow dynamic range.

address h'05

Language Code (langcod)

8 bits

This field indicates the audio service language. If the language code doesn't exist in bitstream, this value

indicates h'00.

address h'06

Dynamic Range Gain Word (dynrng)

8 bits

If dynrnge is a 1, this field indicates the scale of the reproduced audio level in order to reproduce an

ordinary dynamic range.

address h'07

Mixing Level (mixlevel)

5 bits

This field contains the acoustic sound pressure level of the dialogue level of the final audio mixing

session.

Room Type (roomtyp)

2 bits

This field indicates the type of mixing room used for the final audio mixing session.

roomtyp

Type of Mixing Room

0 0

Not indicated

0 1

Large room. X curve monitor

1 0

Small room. flat monitor

1 1

Reserved

Audio Production Information Exists (audprodie)

1 bit

If this bit is a 1,this bitstream has mixing level data and room type data.

address h'08

Dialogue Normalization, Ch2 (dianorm2)

5 bits

This field contains dialogue normalization for ch2 when acmod indicates dual mono mode (acmod=000).

Dynamic Range Gain Word Exists, Ch2 (dynrng2e)

1 bit

If this bit is a 1, this bitstream has a dynamic range gain word for ch2 when acmod indicates dual mono

mode (acmod=000).

Compression Gain Word Exists, Ch2 (compr2e)

1 bit

If this bit is a 1,this bitstream has a compression gain word for ch2 when acmod indicates dual mono

Product Note

M65863FP

April 1998

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mode (acmod=000).

address h'09

Compression Gain Word, Ch2 (compr2)

8 bits

This field indicates compression gain word for ch2 when acmod indicates dual mono mode (acmod=000).

address h'0A

Language Code, Ch2 (langcod2)

8 bits

This field indicates language code for ch2 when acmod indicates dual mono mode (acmod=000).

address h'0B

Dynamic Range Gain Word , Ch2 (dynrng2)

8 bits

This field indicates dynamic range gain word for ch2 when acmod indicates dual mono mode

(acmod=000).

address h'0C

Mixing Level, Ch2 (mixlevel2)

5 bits

This field contains mixing level for ch2 when acmod indicates dual mono mode (acmod=000).

Room Type, Ch2 (roomtyp2)

2 bits

This field contains room type for ch2 when acmod indicates dual mono mode (acmod=000).

Audio Production Information Exists, Ch2 (audprodi2e)

1 bit

This bit indicates audio production information for ch2 when acmod indicates dual mono mode

(acmod=000).

Product Note

M65863FP

April 1998

Dolby Digital Decoder

MITSUBISHI ELECTRIC CORPORATION

4.2

IEC958 Burst Information Registers

IEC958 burst information registers are provided. Table 4.3 shows IEC958 burst information registers.

Table4.3 IEC958 Burst Information Registers

bit

Address

R/W

h'0D

burste

ierrflg

idtdep

address h'0D

Data Type Dependent Code (idtdep)

5 bits

3rd and 4th bit are reserved,and these values set '0'. If Data Type Code indicates Dolby Digital (AC-3)

Data,other 3 bits field indicates same as bsmod code.

idtdep

Type of Service

0 0 0 0 0

Main audio service : complete main (CM)

0 0 0 0 1

Main audio service : music and effects (ME)

0 0 0 1 0

Associated service : visually impaired (VI)

0 0 0 1 1

Associated service : hearing impaired (HI)

0 0 1 0 0

Associated service : dialogue (D)

0 0 1 0 1

Associated service : commentary (C)

0 0 1 1 0

Associated service : emergency (E)

0 0 1 1 1

Associated service : voice-over (VO) , or main audio service : karaoke

Error Flag (ierrflg)

1 bit

This field indicates error condition for burst data , according to the following table.

ierrflg

Status

No error

Error

Burst Data Exists (burste)

1 bit

If this bit is a1, burst data which is assigned "istrnums" in control register exists.

Product Note

M65863FP

April 1998

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4.3

Status Registers

The default values are described in the bit fields shown in table 4.4.

Table 4.4 Status Registers

bit

Address

R/W

h'0E

synccon

syncdet

decode

bserr

h'0F

crc1err

crc2err

0 0

h'10

readpointer

R/W

h'11

h'12

writepointer

h'13

address h'0E

Error Information (bserr)

1 bit

This bit indicates error status.

bserr

Description

The value of bsid is less than 8 and encode error doesn't exist

The value of bsid is more than 9, or encode error exists

Decoding Condition Information (decode)

1 bit

decode

Description

Regular decode

Mute

Synchronous Detection Information (syncdet)

1 bit

This bit indicates whether sync word was detected per frame or not.

syncdet

Description

Sync word was detected

Sync word was not detected

Synchronous Lock Information (synccon)

1 bit

This bit indicates whether sync word is locked or not.

synccon

Description

Sync word is locked

Sync word is not locked

Product Note

M65863FP

April 1998

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address h'0F

CRC2 Checked Data (crc2err)

2 bits

This field indicates the status of CRC error for CRC2.

crc2err

Description

0 0

No error

0 1

One error

1 0

More than 2 sequential errors

1 1

Reserved

CRC1 Checked Data (crc1err)

2 bits

This field indicates the status of CRC error for CRC1.

crc1err

Description

0 0

No error

0 1

One error

1 0

More than 2 sequential errors

1 1

Reserved

address h'10

address h'11

Read Pointer to the Input Data Buffer (readpointer)

16 bits

Read pointer to the input data buffer. Read/Write operation are allowed when M65863FP is not decoding.

Only read operation is allowed when M65863FP is decoding.

address h'12

address h'13

Write Pointer to the Input Data Buffer (writepointer)

16 bits

Write pointer to the input data buffer. Only read operation is allowed.