1
CAT25C128/256
128K/256K-Bit SPI Serial CMOS E
2
PROM
FEATURES
s
5 MHz SPI Compatible
s
1.8 to 6.0 Volt Operation
s
Hardware and Software Protection
s
Zero Standby Current
s
Low Power CMOS Technology
s
SPI Modes (0,0 &1,1)
s
Commercial, Industrial and Automotive
Temperature Ranges
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Self-Timed Write Cycle
s
8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
s
64-Byte Page Write Buffer
s
Block Write Protection
– Protect 1/4, 1/2 or all of E
2
PROM Array
PIN CONFIGURATION
DIP Package (P)
PIN FUNCTIONS
Pin Name
Function
SO
Serial Data Output
SCK
Serial Clock
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
CS
Chip Select
SI
Serial Data Input
HOLD
Suspends Serial Input
NC
No Connect
BLOCK DIAGRAM
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DESCRIPTION
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E
2
PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substan-
tially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (
CS
). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The
HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write pro-
tection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
TSSOP Package (U20)
SENSE AMPS
SHIFT REGISTERS
SPI
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
I/O
CONTROL
E
2
PROM
ARRAY
COLUMN
DECODERS
XDEC
HIGH VOLTAGE/
TIMING CONTROL
SO
25C128 F02
STATUS
REGISTER
BLOCK
PROTECT
LOGIC
CONTR
OL LOGIC
DATA IN
STORAGE
SI
CS
WP
HOLD
SCK
SOIC Package (S, K)
VSS
SO
WP
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
CS
SO
WP
CS
VCC
HOLD
SCK
SI
1
2
3
4
8
7
6
5
VSS
Doc. No. 25088-00 1/01
CS
WP
HOLD
VCC
NC
NC
NC
NC
SO
NC
NC
V
SS
SCK
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOIC Package (S16)
NC
NC
CS
WP
HOLD
HOLD
VCC
NC
NC
NC
NC
NC
NC
SO
NC
NC
SO
V
SS
SCK
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TSSOP Package (U14)
CS
NC
1
2
3
4
14
13
12
11
NC
NC
NC
5
6
7
10
9
8
NC
SCK
V
SS
SI
NC
WP
VCC
HOLD
SO
15
16
NC
NC
Note: CAT25C256 not available in 8-Lead S or U packages.
2
CAT25C128/256
Doc. No. 25088-00 1/01
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC1
Power Supply Current
10
mA
V
CC
= 5V @ 5MHz
(Operating Write)
SO=open; CS=Vss
I
CC2
Power Supply Current
2
mA
V
CC
= 5.5V
(Operating Read)
F
CLK
= 5MHz
I
SB
Power Supply Current
0
µ
A
CS
= V
CC
(Standby)
V
IN
= V
SS
or V
CC
I
LI
Input Leakage Current
2
µ
A
I
LO
Output Leakage Current
3
µ
A
V
OUT
= 0V to V
CC
,
CS = 0V
V
IL
(3)
Input Low Voltage
-1
V
CC
x 0.3
V
V
IH
(3)
Input High Voltage
V
CC
x 0.7
V
CC
+ 0.5
V
V
OL1
Output Low Voltage
0.4
V
V
OH1
Output High Voltage
V
CC
- 0.8
V
V
OL2
Output Low Voltage
0.2
V
1.8V
≤
V
CC
<2.7V
V
OH2
Output High Voltage
V
CC
-0.2
V
I
OL
= 150
µ
A
I
OH
= -100
µ
A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55
°
C to +125
°
C
Storage Temperature ....................... –65
°
C to +150
°
C
Voltage on any Pin with
Respect to V
SS
(1)
.................. –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
°
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
°
C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
N
END
(3)
Endurance
100,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
4.5V
≤
V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
3
CAT25C128/256
Doc. No. 25088-00 1/01
Figure 1. Sychronous Data Timing
Limits
Vcc=
V
CC
=
V
CC
=
1.8V-6.0V
2.5V-6.0V
4.5V-5.5V
Test
SYMBOL
PARAMETER
Min.
Max.
Min.
Max.
Min.
Max.
UNITS
Conditions
t
SU
Data Setup Time
100
70
35
ns
t
H
Data Hold Time
100
70
35
ns
t
WH
SCK High Time
250
150
80
ns
t
WL
SCK Low Time
250
150
80
ns
f
SCK
Clock Frequency
DC
1
DC
3
DC
5
MHz
t
LZ
HOLD
to Output Low Z
50
50
50
ns
t
RI
(1)
Input Rise Time
2
2
2
µ
s
t
FI
(1)
Input Fall Time
2
2
2
µ
s
t
HD
HOLD
Setup Time
250
250
40
ns
t
CD
HOLD
Hold Time
250
250
40
ns
t
WC
Write Cycle Time
10
10
5
ms
t
V
Output Valid from Clock Low
250
250
80
ns
t
HO
Output Hold Time
0
0
0
ns
t
DIS
Output Disable Time
250
250
100
ns
t
HZ
HOLD
to Output High Z
150
150
50
ns
t
CS
CS
High Time
1000
250
100
ns
t
CSS
CS
Setup Time
1000
250
100
ns
t
CSH
CS
Hold Time
1000
250
100
ns
t
WPS
WP Setup Time
50
50
50
ns
t
WPH
WP Hold Time
50
50
50
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS (CAT25C128)
VALID IN
V
IH
V
IL
t
CSS
V
IH
V
IL
V
IH
VIL
V
OH
V
OL
HI-Z
t
SU
t
H
t
WH
t
WL
t
V
t
CS
t
CSH
t
HO
t
DIS
HI-Z
CS
SCK
SI
SO
t
RI
tFI
Note: Dashed Line= mode (1, 1) — — — —
C
L
= 50pF
4
CAT25C128/256
Doc. No. 25088-00 1/01
Limits
Vcc= V
CC
= V
CC
= V
CC
=
1.8V-6.0V 2.5V-6.0V 2.7V-6.0V 4.5V-5.5V
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. UNITS
t
SU
Data Setup Time 500 100
70
35
ns
t
H
Data Hold Time 500 100
70
35
ns
t
WH
SCK High Time 2500 250
200
80
ns
t
WL
SCK Low Time 2500 250
200
80
ns
f
SCK
Clock Frequency DC 0.2 DC 2.0 DC 2.5
DC 5 MHz
t
LZ
HOLD
to Output Low Z
100 50
50 50 ns
t
RI
(1)
Input Rise Time
2
2
2 2
µ
s
t
FI
(1)
Input Fall Time
2 2
2 2
µ
s
t
HD
HOLD
Setup Time 250 100
100
40
ns
t
CD
HOLD
Hold Time 250 100
100
40
ns
t
WC
Write Cycle Time
10 10
10 5 ms
t
V
Output Valid from Clock Low 250 200
200 80 ns
t
HO
Output Hold Time 0
0
0
0
ns
t
DIS
Output Disable Time
250 200
200 100 ns
t
HZ
HOLD
to Output High Z 150 100
100 50 ns
t
CS
CS
High Time 100 100
100
100 ns
t
CSS
CS
Setup Time 100 100
100
100 ns
t
CSH
CS
Hold Time 100 100
100
100 ns
t
WPS
WP
Setup Time 50 50
50
50
ns
t
WPH
WP
Hold Time 50 50
50 50
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS (CAT25C256)
Test
Conditions
C
L
= 50pF
5
CAT25C128/256
Doc. No. 25088-00 1/01
FUNCTIONAL DESCRIPTION
The CAT25C128/256 supports the SPI bus data trans-
mission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction regis-
ter. (The instruction set and the operation codes are
detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C128/256. Input data is latched on the rising edge of
the serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C128/256. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
CS
CS
CS
CS
CS
: Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C128/
256 and
CS
high disables the CAT25C128/256.
CS
high
takes the SO output pin to high impedance and forces
the device into a Standby Mode (unless an internal write
operation is underway) The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low
transition on
CS
is required prior to any sequence being
initiated. A low to high transition on
CS
after a valid write
sequence is what initiates an internal write cycle.
WP
WP
WP
WP
WP
: Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP
going low while
CS
is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP
going low will
have no effect on any write operation to the status
register. The
WP
pin function is blocked when the WPEN
bit is set to 0.
HOLD
HOLD
HOLD
HOLD
HOLD
: Hold
HOLD
is the HOLD pin. The
HOLD
pin is used to pause
transmission to the CAT25C128/256 while in the middle
of a serial sequence without having to re-transmit entire
sequence at a later time. To pause,
HOLD
must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,
HOLD
is brought high, while SCK is low.
(HOLD
should be held high any time this function is not
being used.)
HOLD
may be tied high directly to V
cc
or tied
to V
cc
through a resistor. Figure 9 illustrates hold timing
sequence.
Instruction
Opcode
Operation
WREN
0000 0110
Enable Write Operations
WRDI
0000 0100
Disable Write Operations
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory
WRITE
0000 0010
Write Data to Memory
INSTRUCTION SET
6
CAT25C128/256
Doc. No. 25088-00 1/01
Status Register Bits
Array Address
Protection
BP1
BPO
Protected
25C128
25C256
0
0
None
None
No Protection
0
1
3000-3FFF
6000-7FFF
Quarter Array Protection
1
0
2000-3FFF
4000-7FFF
Half Array Protection
1
1
0000-3FFF
0000-7FFF
Full Array Protection
BLOCK PROTECTION BITS
Protected
Unprotected
Status
WPEN
WP
WP
WP
WP
WP
WEL
Blocks
Blocks
Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
WRITE PROTECT ENABLE OPERATION
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
STATUS REGISTER
STATUS REGISTER
The Status Register indicates the status of the device.
The
RDY
(Ready) bit indicates whether the CAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the WREN
instruction and can be reset by the WRDI instruction.
The BPO and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP
pin. The
WP
pin and
WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when
WP
is
low and WPEN bit is set to high. The user cannot write
to the status register (including the block protect bits and
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either
WP
pin is high or the
WPEN bit is zero.
7
CAT25C128/256
Doc. No. 25088-00 1/01
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (7FFFh for 25C256 and 3FFFh for 25C128) is
reached, the address counter rolls over to 0000h allow-
ing the read cycle to be continued indefinitely. The read
operation is terminated by pulling the
CS
high. To read
the status register, RDSR instruction should be sent.
The contents of the status register are shifted out on the
SO line. The status register may be read at any time
even during a write cycle.Read sequence is illustrated in
figure 4. Reading status register is illustrated in figure 5.
Figure 2. WREN Instruction Timing
Figure 3. WRDI Instruction Timing
DEVICE OPERATION
Write Enable and Disable
The CAT25C128/256 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when V
cc
is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling
CS
low. The 8-bit read
instruction is transmitted to the CAT25C128/256, fol-
lowed by the 16-bit address (the Most Significant Bit is