Quad 2-Input Multiplexer
CY54/74FCT157T
SCCS014 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
©
2000, Texas Instruments Incorporated
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 4.3 ns max. (Com’l),
FCT-A speed at 5.0 ns max. (Com’l)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Extended commercial range of
−
40˚C to +85˚C
• Sink current
64 mA (Com’l),
32 mA (Mil)
Source current
32 mA (Com’l),
12 mA (Mil)
Functional Description
The FCT157T is a quad two-input multiplexer that selects four
bits of data from two sources under the control of a common
data Select input (S). The Enable input (E) is Active LOW.
When (E) is HIGH, all of the outputs (Y) are forced LOW
regardless of all other input conditions.
Moving data from two groups of registers to four common
output buses is a common use of the FCT157T. The state of
the Select input determines the particular register from which
the data comes. It can also be used as a function generator.
The device is useful for implementing highly irregular logic by
generating any four of the sixteen different functions of two
variables with one variable common.
The FCT157T is a logic implementation of a four-pole,
two-position switch where the position of the switch is
determined by the logic levels supplied to the Select input.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram, FCT157T
Pin Configurations
1
2
3
4
5
6
7
8
V
CC
GND
Top View
FCT157T
4
8
9
10
11
12
7 6 5
1516 17 18
3
2
1
20
13
14
19
I 1b
I 0b
Y
a
I 1d
I 0c
I 0d
NC
NC
NC
V
CC
E
GND
Y
d
Top View
SOIC/QSOP
I 1a
LCC
NC
16
15
14
13
12
11
10
9
Y
a
S
I
1a
I
0a
I
1d
I
0d
E
I
0a
S
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
Y
a
Y
b
Y
c
Y
d
Y
b
I
1b
I
0b
I
1c
I
0c
Y
d
Y
c
S
I
0a
Y
b
I
1c
Y
c
E
FCT157T–1
Y
a
S
I
1a
I
0a
I
1d
I
0d
Y
b
I
1b
I
0b
I
1c
I
0c
Y
c
Y
d
E
FCT157T
FCT157T
Logic Symbol
CY54/74FCT157T
2
Maximum Ratings
[2,3]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................−
65
°
C to +150
°
C
Ambient Temperature with
Power Applied
..................................................−
65
°
C to +135
°
C
Supply Voltage to Ground Potential
..................−
0.5V to +7.0V
DC Input Voltage
.................................................−
0.5V to +7.0V
DC Output Voltage
..............................................−
0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation .......................................................... 0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Pin Description
Name
Description
S
Common Select Input
E
Enable Inputs (Active LOW)
I
0
Data Inputs from Source 0
I
1
Data Inputs from Source 1
Y
Non-Inverted Output
Function Table
[1]
Inputs
Outputs
E
S
I
0
I
1
Y
H
X
X
X
L
L
H
X
L
L
L
H
X
H
H
L
L
L
X
L
L
L
H
X
H
Operating Range
Range
Range
Ambient
Temperature
V
CC
Commercial
All
−
40
°
C to +85
°
C
5V
±
5%
Military
[4]
All
−
55
°
C to +125
°
C
5V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
[5]
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
=
−
32 mA
Com’l
2.0
V
V
CC
=Min., I
OH
=
−
15 mA
Com’l
2.4
3.3
V
V
CC
=Min., I
OH
=
−
12 mA
Mil
2.4
3.3
V
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
Com’l
0.3
0.55
V
V
CC
=Min., I
OL
=32 mA
Mil
0.3
0.55
V
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
V
H
Hysteresis
[6]
All inputs
0.2
V
V
IK
Input Clamp Diode Voltage
V
CC
=Min., I
IN
=
−
18 mA
−
0.7
−
1.2
V
I
I
Input HIGH Current
V
CC
=Max., V
IN
=V
CC
5
µ
A
I
IH
Input HIGH Current
V
CC
=Max., V
IN
=2.7V
±
1
µ
A
I
IL
Input LOW Current
V
CC
=Max., V
IN
=0.5V
±
1
µ
A
I
OZH
Off State HIGH-Level Output
Current
V
CC
= Max., V
OUT
= 2.7V
10
µ
A
I
OZL
Off State LOW-Level
Output Current
V
CC
= Max., V
OUT
= 0.5V
−
10
µ
A
I
OS
Output Short Circuit Current
[7]
V
CC
=Max., V
OUT
=0.0V
−
60
−
120
−
225
mA
I
OFF
Power-Off Disable
V
CC
=0V, V
OUT
=4.5V
±
1
µ
A
Note:
1.
H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care
2.
Unless otherwise noted, these limits are over the operating free-air temperature range.
3.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4.
T
A
is the “instant on” case temperature.
5.
Typical values are at V
CC
=5.0V, T
A
=+25˚C ambient.
6.
This parameter is specified but not tested.
7.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
CY54/74FCT157T
3
Capacitance
[6]
Parameter
Description
Typ.
[5]
Max.
Unit
C
IN
Input Capacitance
5
10
pF
C
OUT
Output Capacitance
9
12
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.
[5]
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
=Max., V
IN
≤
0.2V, V
IN
≥
V
CC
−
0.2V
0.1
0.2
mA
∆
I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
V
CC
=Max., V
IN
=3.4V,
[8]
f
1
=0, Outputs Open
0.5
2.0
mA
I
CCD
Dynamic Power Supply Current
[9]
V
CC
=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND, V
IN
≤
0.2V or V
IN
≥
V
CC
−
0.2V
0.06
0.12
mA/MHz
I
C
Total Power Supply Current
[10]
V
CC
=Max., 50% Duty Cycle,
Outputs Open,
One Input Toggling at f
1
=10 MHz,
OE=GND, V
IN
≤
0.2V or V
IN
≥
V
CC
−
0.2V
0.7
1.4
mA
V
CC
=Max., 50% Duty Cycle,
Outputs Open,
One Input Toggling at f
1
=10 MHz,
OE=GND, V
IN
=3.4V or V
IN
=GND
1.0
2.4
mA
V
CC
=Max., 50% Duty Cycle,
Outputs Open,
Four Bits Toggling at f
1
=2.5 MHz,
OE=GND, V
IN
≤
0.2V or V
IN
≥
V
CC
−
0.2V
0.7
1.4
[11]
mA
V
CC
=Max., 50% Duty Cycle,
Outputs Open,
Four Bits Toggling at f
1
=2.5 MHz,
OE=GND, V
IN
=3.4V or V
IN
=GND
1.7
5.4
[11]
mA
Notes:
8.
Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
9.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆
I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆
I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the I
CC
formula. These limits are specified but not tested.
CY54/74FCT157T
4
Document #: 38
−
00288-C
Switching Characteristics
Over the Operating Range
Parameter
Description
FCT157T
FCT157AT
FCT157CT
Unit
Fig.
No.
[13}
Commercial
Military
Commercial
Commercial
Min.
[12]
Max.
Min.
[12]
Max.
Min.
[12]
Max.
Min.
[12]
Max.
t
PLH
t
PHL
Propagation Delay
I to Y
1.5
6.0
1.5
5.8
1.5
5.0
1.5
4.3
ns
1, 3
t
PLH
t
PHL
Propagation Delay
E to Y
1.5
10.5
1.5
7.4
1.5
6.0
1.5
4.8
ns
1, 5
t
PLH
t
PHL
Propagation Delay
S to Y
1.5
10.5
1.5
8.1
1.5
7.0
1.5
5.2
ns
1, 3
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
4.3
CY74FCT157CTQCT
Q1
16-Lead (150-Mil) QSOP
Commercial
CY74FCT157CTSOC/SOCT
S1
16-Lead (300-Mil) Molded SOIC
5.0
CY74FCT157ATQCT
Q1
16-Lead (150-Mil) QSOP
Commercial
CY74FCT157ATSOC/SOCT
S1
16-Lead (300-Mil) Molded SOIC
5.8
CY54FCT157ATLMB
L61
20-Pin Square Leadless Chip Carrier
Military
Note:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information Section
Package Diagrams
20-Pin Square Leadless Chip Carrier L61
MIL
−
STD
−
1835 C
−
2A
CY54/74FCT157T
5
Package Diagrams
(continued)
16-Lead Quarter Size Outline Q1
16-Lead Molded SOIC S1
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Copyright
©
2000, Texas Instruments Incorporated