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Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
1
M2V56S20ATP is a 4-bank x 16777216-word x 4-bit,
M2V56S30ATP is a 4-bank x 8388608-word x 8-bit,
M2V56S40ATP is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40ATP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
Some of contents are subject to change without notice.
DESCRIPTION
FEATURES
Standard
PC100 (CL2)
PC133 (CL3)
PC133 (CL2)
166 MHz
133 MHz
100 MHz
100MHz
100MHz
133 MHz
M2V56S20/30/40ATP-7
M2V56S20/30/40ATP-6
M2V56S20/30/40ATP-5
Max. Frequency
@CL3
Max. Frequency
@CL2
background image
Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
2
CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQ0-15
: Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12
: Address Input
BA0,1
: Bank Address Input
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
x16
x8
x4
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Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
3
Speed Grade 5: 166MHz@CL3, 133MHz@CL2
6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2
Type Designation Code
This rule is applied to only Synchronous DRAM family.
Mitsubishi Main Designation
Package Type TP: TSOP(II)
Process Generation A:2nd. gen.
Function Reserved for Future Use
Organization 2n 2: x4, 3: x8, 4: x16
SDRAM Data Rate Type S:Single Data Rate
Density 56: 256M bits
Interface V:LVTTL
Memory Style (DRAM)
M 2 V 56 S 4 0 A TP - 5
BLOCK DIAGRAM
/CS /RAS /CAS /WE DQMU/L
Memory
Array
Bank #0
DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)
I/O Buffer
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
A0-12
BA0,1
Clock Buffer
CLK
CKE
Control Signal Buffer
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Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
4
VddQ and VssQ are supplied to the Output Buffers only.
Power Supply for the memory array and peripheral circuitry.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.
Data In and Data out are referenced to the rising edge of CLK.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12. The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.
Input / Output
Power Supply
Power Supply
Input
Input
Input
Input
VddQ, VssQ
Vdd, Vss
DQM
DQMU/L
DQ0-15
BA0,1
A0-12
/RAS, /CAS, /WE
Chip Select: When /CS is high, any command means No Operation
Input
/CS
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto
/ self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Input
CKE
CLK
PIN FUNCTION
background image
Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
5
BASIC FUNCTIONS
The M2V56S20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
Refresh Option @refresh command
A10
Precharge Option @precharge or read/write command
CLK
define basic commands
background image
Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
6
COMMAND TRUTH TABLE
NOTE:
1. A7-9,11-12=L, A0-A6 =Mode
Address
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
COMMAND
MNEMONIC
CKE
n-1
CKE
n
/CS
/RAS /CAS
/WE BA0,1
A10
/AP
A0-9,
11-12
Deselect
DESEL
H
X
H
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
L
X
Precharge All Banks
PREA
H
X
L
L
H
L
H
X
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
Auto-Precharge
WRITEA
H
X
L
H
L
L
V
H
V
Column Address Entry
& Read
READ
H
X
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
READA
H
X
L
H
L
H
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
Self-Refresh Exit
REFSX
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
V
X
note
1
background image
Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
7
FUNCTION TRUTH TABLE
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE / PREA
NOP*4
L
L
L
H
X
REFA
Auto-Refresh*5
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set*5
ROW ACTIVE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA, CA, A10
READ / READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Precharge / Precharge All
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
background image
Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
8
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
WRITE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
READ / READA
Terminate Burst, Latch CA,
Begin Read, Determine Auto-
Precharge*3
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
Terminate Burst, Precharge
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
READ with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP (Continue Burst to END)
L
H
H
H
X
NOP
NOP (Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
READ / READA ILLEGAL
L
H
L
L
BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L
L
H
H
BA, RA
ACT
Bank Active / ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
background image
Jul '01
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.01)
Single Data Rate
M2V56S20/ 30/ 40 ATP -5, -6, -7
256M Synchronous DRAM
9
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
PRE -
CHARGING
H
X
X
X
X
DESEL
NOP (Idle after tRP)
L
H
H
H
X
NOP
NOP (Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
NOP*4 (Idle after tRP)
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
H
X
X
X
X
DESEL
NOP (Row Active after tRCD)
L
H
H
H
X
NOP
NOP (Row Active after tRCD)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
PRE / PREA
ILLEGAL*2
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE RE-
COVERING
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ / WRITE ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2