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MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

DESCRIPTION

The MH8S64DBKG is 8388608 - word by 64-bit

Synchronous DRAM module. This consists of eight

industry standard 4Mx16 Synchronous DRAM s in

TSOP and one industory standard EEPROM in

TSSOP.

The mounting of TSOP on a card edge Dual

Inline package provides any application where

high densities and large quantities of memory are

required.

This is a socket type - memory modules, suitable

for easy interchange or addition of modules.

FEATURES

Clock frequency 100MHz(max.)

single 3.3V±0.3V power supply

Fully synchronous operation referenced to clock rising

edge

Burst length- 1/2/4/8/Full Page(programmable)

4 bank operation controlled by BA0,1(Bank Address)

/CAS latency- 2/3(programmable)

APPLICATION

main memory or graphic memory in computer systems

Auto precharge / All bank precharge controlled by A10

Burst type- sequential / interleave(programmable)

Column access - random

LVTTL Interface

Auto refresh and Self refresh

4096 refresh cycle /64ms

Utilizes industry s t andard 4M x 16 Sy nchronous DRAMs

TSOP and industry s t andard EEPROM in TSSOP

144-pin (72-pin dual in-line package)

(Front)

(Back)

143

144

PCB Outline

Frequency

CLK Access Time

-8,-8L

100MHz

6.0ns(CL=2)

(Component SDRAM)

6.0ns(CL=3)

100MHz

-7,-7L

PC100 compliant

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

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ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

NC = No Connection

PIN CONFIGURATION

PIN

Number

Front side

Pin Name

Back side

Pin Name

PIN

Number

PIN

Number

Front side

Pin Name

Back side

Pin Name

PIN

Number

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Vss

DQ0

DQ1

DQ2

DQ3

Vcc

DQ4

DQ5

DQ6

DQ7

Vss

DQ32

DQ33

DQ34

DQ35

Vcc

DQ36

DQ37

DQ38

DQ39

CLK1

Vss

Vcc

DQ16

DQ48

DQ17

DQ49

DQ18

DQ50

DQ19

DQ51

Vss

DQ20

DQ52

DQMB0

DQMB4

DQ21

DQ53

DQMB1

DQMB5

DQ22

DQ54

Vcc

DQ23

DQ55

Vcc

BA0

Vss

DQ8

DQ40

BA1

DQ9

DQ41

A10

A11

DQ10

DQ42

Vcc

DQ11

DQ43

DQMB2

DQMB6

Vcc

DQMB3

DQMB7

DQ12

DQ44

Vss

DQ13

DQ45

DQ24

DQ56

DQ14

DQ46

DQ25

DQ57

DQ15

DQ47

DQ26

DQ58

Vss

DQ27

DQ59

Vcc

DQ28

DQ60

CLK0

CKE0

DQ29

DQ61

Vcc

DQ30

DQ62

/RAS

/CAS

DQ31

DQ63

/WE

CKE1

Vss

/S0

SDA

SCL

/S1

Vcc

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

Block Diagram

CLK0

SERIAL PD

SCL

SDA

Vcc

Vss

D0 - D7

/S0

DQMB0

DQMB4

DQMB1

DQMB5

DQMB2

DQMB6

DQMB3

DQMB7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

CKE0

D0 - D3

/RAS

D0 - D7

/CAS

D0 - D7

/WE

D0 - D7

BA0,BA1,A<11:0>

D0 - D7

CLK1

Ω

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

I/O 0

I/O 1

I/O 2

I/O 3

DQML /CS

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

DQMU

I/O 12

I/O 13

I/O 14

I/O 15

/S1

4loads

CKE1

D4 - D7

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

Serial Presence Detect Table I

Byte

Function described

SPD enrty data

SPD DATA(hex)

Defines # bytes written into serial memory at module mfgr

128

Total # bytes of SPD memory device

256 Bytes

Fundamental memory type

SDRAM

# Row Addresses on this assembly

A0-A11

# Column Addresses on this assembly

A0-A7

# Module Banks on this assembly

2BANK

Data Width of this assembly...

x64

... Data Width continuation

Voltage interface standard of this assembly

LVTTL

SDRAM Cycletime at Max. Supported CAS Latency (CL).

Cycle time for CL=3

SDRAM Access from Clock

6ns

tAC for CL=3

DIMM Configuration type (Non-parity,Parity,ECC)

Non-PARITY

Refresh Rate/Type

self refresh(15.625uS)

SDRAM width,Primary DRAM

x16

Error Checking SDRAM data width

N/A

Minimum Clock Delay,Back to Back Random Column Addresses

Burst Lengths Supported

1/2/4/8/Full page

# Banks on Each SDRAM device

4bank

CAS# Latency

2/3

CS# Latency

Write Latency

SDRAM Module Attributes

non-buffered,non-registered

SDRAM Device Attributes:General

Precharge All,Auto precharge

SDRAM Cycle time(2nd highest CAS latency)

13ns

Cycle time for CL=2

SDRAM Access form Clock(2nd highest CAS latency)

7ns

tAC for CL=2

SDRAM Cycle time(3rd highest CAS latency)

N/A

SDRAM Access form Clock(3rd highest CAS latency)

Precharge to Active Minimum

20ns

Row Active to Row Active Min.

20ns

10ns

-8,8L

-7,7L

10ns

6ns

-7,7L

RAS to CAS Delay Min

20ns

Active to Precharge Min

50ns

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

Serial Presence Detect Table II

Density of each bank on module

32MByte

36-61

Superset Information (may be used in future)

option

SPD Revision

Checksum for bytes 0-62

Check sum for -8,-8L

64-71

Manufactures Jedec ID code per JEP-108E

MITSUBISHI

1CFFFFFFFFFFFFFF

Manufacturing location

Miyoshi,Japan

Tajima,Japan

NC,USA

Germany

73-90

Manufactures Part Number

MH8S64DBKG-8

4D483853363444424B472D38202020202020

MH8S64DBKG-8L

91-92

Revision Code

PCB revision

rrrr

93-94

Manufacturing date

year/week code

yyww

95-98

Assembly Serial Number

serial number

ssssssss

99-125

Manufacture Specific Data

option

126

Intetl specification frequency

100MHz

127

Intel specification CAS# Latency support

128+

Unused storage locations

open

4D483853363444424B472D384C2020202020

Command and Address signal input setup time

2ns

Command and Address signal input hold time

1ns

Data signal input setup time

2ns

Data signal input hold time

1ns

rev 1.2A

Check sum for -7,7L

MH8S64DBKG-7

4D483853363444424B472D374C2020202020

-7,7L

-8,8L

MH8S64DBKG-7L

4D483853363444424B472D37202020202020

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

( / 55 )

MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

PIN FUNCTION

Input

Master Clock:All other inputs are referenced to the ris ing

edge of CK

CKE0, CKE1

Input

Clock Enable:CKE controls internal clock.When CKE is

low,internal clock for the following cycle is ceased. CKE is

also used to select auto / self refresh. After self refresh

mode is started, CKE E becomes asynchronous input.Self

refresh is maintained as long as CKE is low.

/S0, /S1

Input

Chip Select: When /S is high,any command means

No Operation.

/RAS,/CAS,/WE

Input

Combination of /RAS,/CAS,/WE defines basic commands.

A0-11

Input

A0-11 specify the Row/Column Address in conjunction with

BA0,1.The Row Address is specified by A0-11.The Column

Address is specified by A0-7.A10 is also used to indicate

precharge option.When A10 is high at a read / write

command, an auto precharge is performed. When A10 is

high at a precharge command, both banks are precharged.

BA0,1

Input

Bank Address:BA0,1 is not simply BA.BA specifies the

bank to which a command is applied.BA0,1 must be set

with ACT,PRE,READ,WRITE commands

DQ0-63

Input/Output Data In and Data out are referenced to the rising edge

of CK

DQMB0-7

Input

Din Mask/Output Disable:When DQMB is high in burst

write.Din for the current cycle is masked.When DQMB is

high in burst read,Dout is disabled at the next but one cycle.

Vdd,Vss

Power Supply Power Supply for the memory mounted module.

SCL

SDA

Input

Output

Serial clock for serial PD

Serial data for serial PD

CLK

(CLK0 ~ CLK1)

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI LSIs

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MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

BASIC FUNCTIONS

Chip Select : L=select, H=deselect

/RAS

Command

/CAS

Command

/WE

Command

CKE

Ref resh Option @ref resh

command

A10

Precharge Option @precharge or read/write

command

def ine basic commands

The MH8S64DBKG provides basic functions,bank(row)activate,burst read / write,

bank(row)precharge,and auto / self refresh.

Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.

In addition to 3 s ignals,/S,CKE and A10 are used as chip select,refresh option,and

precharge option,respectively.

To know the detailed definition of commands please see the command truth table.

Activate(ACT) [/RAS =L, /CAS = /WE =H]

Read(READ) [/RAS =H,/CAS =L, /WE =H]

Write(WRITE) [/RAS =H, /CAS = /WE =L]

Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]

Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]

ACT command activates a row in an idle bank indicated by BA.

READ command starts burst read from the active bank indicated by BA.First output

data appears after /CAS latency. When A10 =H at this command,the bank is

deactivated after the burst read(auto-precharge,

READA).

WRITE command starts burst write to the active bank indicated by BA. Total data

length to be written is set by burst length. When A10 =H at this command, the bank is

deactivated after the burst write(auto-precharge,

WRITEA).

PRE command deactivates the active bank indicated by BA. This command also

terminates burst read / write operation. When A10 =H at this command, both banks

are deactivated(precharge all,

PREA).

PEFA command starts auto-refresh cycle. Refresh address including bank address

are generated internally. After this command, the banks are precharged automatically.

MH8S64DBKG -7,-7L,-8,-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

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MITSUBISHI

ELECTRIC

17.Sep.1999

Preliminary Spec.

Some contents are subject to change without notice.

MIT-DS-0340-0.0

COMMAND TRUTH TABLE

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

COMMAND

MNEMONIC

CKE

n-1

CKE

/RAS /CAS

/WE BA0,1

A10

A0-9

Deselect

DESEL

No Operation

NOP

Row Adress Entry &

Bank Activate

ACT

Single Bank Precharge

PRE

Precharge All Bank

PREA

Column Address Entry

& Write

WRIT E

Column Address Entry

& Write with Auto-

Precharge

WRITEA

Column Address Entry

& Read

READ

Column Address Entry

& Read with Auto

Precharge

READA

Auto-Refresh

REFA

Self-Refresh Entry

REFS

Self-Refresh Exit

REFSX

Burst Terminate

TERM

Mode Register Set

MRS

V*1

A11