MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
PACKAGE
M5M256DP : 28 pin 600 mil DIP
M5M5256DFP : 28 pin 450 mil SOP
M5M5256DVP,RV : 28pin 8 X 13.4 mm TSOP
•Single +5V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current··········0.05µA(typ.)
APPLICATION
Small capacity memory units
DESCRIPTION
The M5M5256DP,FP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
FEATURE
PIN CONFIGURATION (TOP VIEW)
1
20µA
(Vcc=5.5V)
(Vcc=5.5V)
5µA
(max)
Stand-by
(max)
Active
(max)
Power supply current
Type
M5M5256DP, FP,VP,RV-45LL
Access
time
45ns
55mA
M5M5256DP, FP,VP,RV-55LL
M5M5256DP, FP,VP,RV-70LL
55ns
70ns
M5M5256DP, FP,VP,RV-45XL
45ns
M5M5256DP, FP,VP,RV-55XL
M5M5256DP, FP,VP,RV-70XL
55ns
70ns
2
(Vcc=3.0V,
Typical)
0.05µA
(Vcc=5.5V)
M5M5256DP,FP
1
A14
2
A12
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
3
A7
11
DQ1
12
DQ2
13
DQ3
14
GND
28 Vcc
26 A13
25 A8
24 A9
23 A11
21 A10
DQ8
18
DQ7
17
DQ6
16
DQ5
15
DQ4
27 /W
22 /OE
20 /S
19
M5M5256DVP
1 A14
2 A12
4 A6
5 A5
6 A4
7 A3
3 A7
8
A2
9
A1
10
A0
11
DQ1
12
DQ2
13
DQ3
14
GND
Vcc
28
A13
26
A8
25
A9
24
A11
23
/W
27
/OE
22
A10 21
DQ7 18
DQ6 17
DQ5 16
DQ415
/S 20
DQ8 19
M5M5256DRV
A14
A12
A6
A5
A4
A3
A7
A2
A1
A0
DQ1
DQ2
DQ3
GND
A10
DQ7
DQ6
DQ5
DQ4
Vcc
A13
A8
A9
A11
/W
/OE
/S
DQ8
Outline 28P2C-A (DVP)
Outline 28P2C-B (DRV)
Outline 28P4 (DP)
28P2W-C (DFP)
28
27
25
24
23
22
26
21
20
19
18
17
16
15
1
3
4
5
6
2
7
8
11
12
13
14
9
10
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
FUNCTION
FUNCTION TABLE
The operation mode of the M5M5256DP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
Mode
DQ
Icc
/S
/W
/OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
D
IN
D
OUT
X
X
L
L
L
L
X
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
VCC
(5V)
GND
(0V)
27
20
22
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
2
12
11
13
15
16
17
18
19
ADDRESS INPUT
BUFFER
ROW DECODER
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
SENSE ANPLIFIER
OUTPUT BUFFER
DATA INPUT
BUFFER
COLUMN
DECODER
ADDRESS INPUT
BUFFER
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
INPUT
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
BLOCK DIAGRAM
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
3
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
Test conditions
pF
pF
Unit
Max
6
8
Typ
Min
Limits
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Input capacitance
Output capacitance
C
I
C
O
DC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
V
V
V
Limits
Test conditions
Unit
V
uA
* -3.0V in case of AC ( Pulse width
≤
30ns )
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: C
I
, C
O
are periodically sampled and are not 100% tested.
mA
* -3.0V in case of AC ( Pulse width
≤
30ns )
uA
uA
mA
V
Active supply current
(AC, MOS level )
Icc
1
Icc
2
Stand-by current
Icc
4
V
IH
High-level input voltage
V
IL
Low-level input voltage
I
O
Output current in off-state
Icc
3
Stand-by current
V
OH1
High-level output voltage 1
I
OH
=-1mA
V
OH2
High-level output voltage 2
I
OH
=-0.1mA
V
OL
Low-level output voltage
I
OL
=2mA
I
I
Input current
V
I
=0
~
Vcc
Vcc
+0.3
0.8
2.2
-0.3
2.4
3
0.4
50
35
20
5
Vcc
-0.5
±1
40
25
-LL
-XL
Max
Typ
Min
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Unit
V
V
V
mW
°C
Conditions
With respect to GND
Ta=25°C
700
0~70
-65~150
Ratings
Symbol
Vcc
V
I
V
O
P
d
T
opr
T
stg
-0.3
*
~7.0
-0.3
*
~Vcc+0.3
0~Vcc
(Max 7.0)
/S=V
IH
,other inputs=0
~
Vcc
/S
≥
Vcc-0.2V,
other inputs=0~Vcc
/S=V
IH
or or /OE=V
IH
,
V
I/O
=0
~
Vcc
45ns
70ns
45
30
55ns
mA
55
35
45
25
/S=V
IL
,
other inputs=V
IH
or V
IL
Output-open Min. cycle
45ns
70ns
50
30
55ns
Active supply current
(AC, TTL level )
/S
≤
0.2V,
Other inputs<0.2V or >Vcc-0.2V
Output-open Min. cycle
°C
±1
0.1
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
4
(2) READ CYCLE
(3) WRITE CYCLE
Symbol
Parameter
t
CR
Read cycle time
Address access time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
t
a
(A)
-70LL, XL
AC ELECTRICAL CHARACTERISTICS
(Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
Max
Min
Input pulse level···················V
IH
=2.4V,V
IL
=0.6V
Input rise and fall time··········5ns
Reference level····················V
OH
=V
OL
=1.5V
Output loads·························Fig.1,CL=30pF (-45LL,-45XL )
CL=50pF (-55LL,-55XL )
CL=100pF (-70LL,-70XL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
55
5
5
10
Min
55
55
30
20
20
Max
45
5
5
10
Min
45
45
25
15
15
Max
-45LL, XL
-55LL, XL
70
5
5
10
70
70
35
25
25
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
Max
Min
-70LL, XL
-45LL, XL
-55LL, XL
20
20
Max
55
40
0
50
50
25
0
0
5
5
Min
15
15
Max
45
35
0
40
40
20
0
0
5
5
Min
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
25
25
70
50
0
65
65
30
0
0
5
5
Vcc
DQ
C
L
Fig.1 Output load
1.8k
Ω
990
Ω
(Including
scope and JIG)
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
t
en
(W)
5
Read cycle
Write cycle (/W control mode)
(4) TIMING DIAGRAMS
DATA VALID
(Note 3)
(Note 3)
t
a
(A)
t
a
(S)
t
v
(A)
t
dis
(S)
t
a
(OE)
t
en
(OE)
t
dis
(OE)
(Note 3)
(Note 3)
t
CR
t
h
(D)
t
su
(D)
DQ
1~8
/S
t
su
(S)
/OE
t
su
(A-WH)
t
en
(OE)
t
dis
(OE)
(Note 3)
(Note 3)
/W
t
w
(W)
t
rec
(W)
t
su
(A)
t
dis
(W)
t
CW
t
en
(S)
/W = "H" level
A
0~14
DQ
1~8
/S
/OE
A
0~14
DATA IN
STABLE
(Note 3)
(Note 3)
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
6
Write cycle ( /S control mode)
t
su
(S)
t
rec
(W)
t
h
(D)
t
CW
(Note 5)
(Note 3)
(Note 3)
t
su
(A)
(Note 4)
t
su
(D)
DATA IN
STABLE
DQ
1~8
/S
/W
A
0~14
Note 3 : Hatching indicates the state is "don't care".
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
4 : Writing is executed in overlap of /S and /W low.
7 : ten, tdis are periodically sampled and are not 100% tested.
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
'97.4.7
7
(3) POWER DOWN CHARACTERISTICS
/S control mode
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
(Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted)
Power down set up time
Power down recovery time
(2) TIMING REQUIREMENTS
(Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted )
t
su (PD)
t
rec (PD)
Symbol
Parameter
ns
Max
Typ
Limits
Min
Test conditions
Unit
0
t
CR
ns
2.2V
t
su (PD)
4.5V
2.2V
t
rec (PD)
/S
≥
Vcc
-
0.2V
Vcc
/S
Symbol
Parameter
V
V
Max
Typ
Limits
Min
Test conditions
Unit
uA
V
2
10
-XL
(Note 8)
0.05
2
Vcc
(PD)
Icc
(PD)
Power down supply voltage
Power down supply current
Note7: ICC (PD) = 1uA in case of Ta = 25°C
Note8: ICC (PD) = 0.2uA in case of Ta = 25°C
2.2
V
I (/S)
Chip select input /S
Vcc = 3V,
/
S
≥
Vcc
-0.2V,
Other inputs=0~Vcc
-LL
(Note 7)
4.5V
2.2V
≤
V
CC(PD)
2V
≤
V
CC(PD)
≤
2.2V
V
CC(PD)