MITSUBISHI ELECTRIC
M5M5408BFP/TP/RT/KV/KR
revision-K0.1e, ' 98.07.30
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
DESCRIPTION
• Single +5V power supply
• Small stand-by current: 0.4µA(3V,typ.)
• No clocks, No refresh
• Data retention supply voltage=2.0V to 5.5V
• All inputs and outputs are TTL compatible.
• Easy memory expansion by S
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Process technology: 0.25µm CMOS
• Package:
M5M5408BFP: 32 pin 525 mil SOP
M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
M5M5408BKV/KR: 32 pin 8mm x 13.4mm STSOP
FEATURES
1
The M5M5408B is a family of 4-Mbit static RAMs organized as
524,288-words by 8-bit, fabricated by Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5408B is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic
TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of
TSOPs and two types of STSOPs are available , M5M5408BTP
(normal-lead-bend TSOP) , M5M5408BRT (reverse-lead-bend
TSOP) , M5M5408BKV (normal-lead-bend STSOP) and
M5M5408BKR (reverse-lead-bend STSOP). These two types
TSOPs and two types STSOPs are suitable for a surface mounting
on double-sided printed circuit boards.
From the point of operating temperature, the family is divided
into three versions; "Standard", "
W
-version", and "
I
-version". Those
are summarized in the part name table below.
PART NAME TABLE
* "typical" parameter is sampled, not 100% tested.
M5M5408B## -55L
M5M5408B## -70L
M5M5408B## -10L
M5M5408B## -55H
Standard
0 ~ +70°C
Version,
Part name
(## stands for "FP","TP",
"RT","KV"or"KR")
Power
Supply
Access
time
max.
25°C
Stand-by current Icc
(PD)
, Vcc=3.0V
55ns
5.0V
---
0.4µA
10µA
typical *
70ns
100ns
W-
version
-20 ~ +85°C
I-
version
-40 ~ +85°C
Active
current
50mA
(10MHz)
25mA
(1MHz)
Ratings (max.)
Operating
temperature
(5.0V, typ.)
Icc1
M5M5408B## -70H
M5M5408B## -10H
5.0V
55ns
70ns
100ns
M5M5408B## -55LW
M5M5408B## -70LW
M5M5408B## -10LW
M5M5408B## -55HW
55ns
5.0V
---
0.4µA
20µA
70ns
100ns
M5M5408B## -70HW
M5M5408B## -10HW
5.0V
55ns
70ns
100ns
M5M5408B## -55LI
M5M5408B## -70LI
M5M5408B## -10LI
M5M5408B## -55HI
55ns
5.0V
---
0.4µA
20µA
70ns
100ns
M5M5408B## -70HI
M5M5408B## -10HI
5.0V
55ns
70ns
100ns
50µA
100µA
100µA
70°C
85°C
---
---
---
---
---
---
MITSUBISHI ELECTRIC
M5M5408BFP/TP/RT/KV/KR
revision-K0.1e, ' 98.07.30
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
PIN CONFIGURATION (TOP VIEW)
Outline 32P3Y-J (RT)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
9
OE
S
A
13
A
8
A
15
DQ
6
DQ
5
DQ
4
DQ
8
DQ
7
A
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
W
V
CC
(5V)
A
10
Outline 32P2M-A (FP)
32P3Y-H (TP)
Outline 32P3K-C
Outline 32P3K-B
A
4
A
5
A
6
A
7
A
14
A
16
A
17
Vcc
A
15
A
18
W
A
13
A
8
A
9
A
11
A
12
GND
A
2
A
0
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
DQ8
S
A
10
OE
A
1
A
3
DQ4
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
11
A
9
A
8
A
13
A
18
A
15
Vcc
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
W
OE
A
10
S
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A
0
A
1
A
2
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M5M5408BKR
M5M5408BKV
(0V)
GND
DQ
3
DQ
2
DQ
1
A
12
A
14
A
16
A
18
A
6
A
2
A
3
A
5
A
1
A
0
A
7
A
4
A
17
A
9
OE
S
A
13
A
8
A
15
DQ
6
DQ
5
DQ
4
DQ
8
DQ
7
A
11
W
V
CC
(5V)
A
10
A
17
GND
(0V)
DQ
3
DQ
2
DQ
1
A
12
A
14
A
16
A
18
A
6
A
2
A
3
A
5
A
1
A
0
A
7
A
4
2
MITSUBISHI ELECTRIC
M5M5408BFP/TP/RT/KV/KR
revision-K0.1e, ' 98.07.30
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
FUNCTION TABLE
BLOCK DIAGRAM
3
DQ
1
DQ
2
DQ
3
DQ
4
V
CC
(3V)
GND
(0V)
W
OE
DQ
5
DQ
6
DQ
7
DQ
8
S
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
A
18
A
11
A
9
A
8
20
A
0
19
A
1
18
A
2
17
A
3
A
13
1
2
3
4
16
15
14
13
12
11
10
9
6
Mode
DQ
Icc
S
W
OE
Write
Read
H
L
L
L
L
X
L
H
H
H
X
X
Non selection
High-impedance
High-impedance
Active
Standby
Read
A
15
7
A
10
31
A0 ~ A18
DQ1 ~ DQ8
S
W
OE
Vcc
GND
Address input
Data input / output
Chip select input
Write control input
Output inable input
Power supply
Ground supply
Pin
Function
Data input (D)
Active
Active
MEMORY ARRAY
524288 WORDS
x 8 BITS
CLOCK
GENERATOR
FUNCTION
The M5M5408BFP,TP,RT,KV,KR is organized as 524,288-
words by 8-bit. These devices operate on a single +5.0V
power supply, and are directly TTL compatible to both input
and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
A write operation is executed during the S low and W low
overlap time. The address(A0~A18) must be set up before
the write cycle
A read operation is executed by setting W at a high level
and OE at a low level while S are in an active state(S=L).
When setting S at a high level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips. Setting the OE at a high
level,the output stage is in a high-impedance state, and the
data bus contention problem in the write cycle is eliminated.
The power supply current is reduced as low as 0.4µA(25°C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure
or power-down operation in the non-selected mode.
Data output (Q)
12
11
10
9
25
26
27
28
8
7
6
5
4
3
2
30
1
31
23
24
13
14
15
17
32
22
18
19
20
21
29
16
21
22
23
25
26
27
28
29
32
8
30
5
24
M5M5408BKV/KR
M5M5408B
FP/TP/RT
M5M5408BKV/KR
M5M5408B
FP/TP/RT
MITSUBISHI ELECTRIC
M5M5408BFP/TP/RT/KV/KR
revision-K0.1e, ' 98.07.30
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4
ABSOLUTE MAXIMUM RATINGS
pF
8
10
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=
GND,V
O
=25mVrms, f=1MHz
C
I
C
O
Symbol
Parameter
Limits
Conditions
Units
µA
mA
µA
mA
V
Icc
1
Icc
2
Icc
4
V
IH
V
IL
I
O
Icc
3
V
OH1
I
OH
= -1mA
V
OH2
I
OH
= -0.1mA
V
OL
I
OL
=2mA
I
I
V
I
=0
~
Vcc
S=V
IH
or OE=V
IH,
V
I/O
=0
~
Vcc
Vcc+0.3V
0.8
2.2
-0.3 *
2.4
3
0.4
±1
80
50
Vcc-0.5V
±1
30
-HW, -HI
Max
Typ
Min
DC ELECTRICAL CHARACTERISTICS
0.4
minimum cycle
f= 1MHz
-
-
-
-
-
-
-
-
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
temperature
Storage temperature
V
mW
°C
°C
Conditions
Ta=25°C
700
-20 ~ +85
-65 ~150
Ratings
Vcc
V
I
V
O
P
d
T
a
T
stg
-0.3
*
~ +7
-0.3
*
~ Vcc + 0.3
0 ~ Vcc
Symbol
Parameter
Units
-40 ~ +85
0 ~ +70
Standard
W-
version
I-
version
With respect to GND
f= 1MHz
25
90
60
40
30
-L
-H
-
-LW, -LI
20
-
-
40
100
200
-
(-L, -H)
(-LW, -HW)
(-LI, -HI)
With respect to GND
With respect to GND
( Vcc=5V±10%, unless otherwise noted)
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
( AC,MOS level )
( AC,TTL level )
Active supply current
Stand by supply current
( AC,MOS level )
( AC,TTL level )
Stand by supply current
S
≤
0.2V
Other inputs
≤
0.2V or
≥
Vcc-0.2V
Output-open
S=VIL
Other inputs=V
IH
or V
IL
Output-open
S=V ,Other inputs= 0 ~ Vcc
S
≥
Vcc-0.2V
Other inputs=0~Vcc
* -3.0V in case of AC (Pulse width
≤
50ns)
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=5.0V and Ta=25°C
CAPACITANCE
(Vcc=5.0V±10%, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Max
Typ
Min
Units
Input capacitance
Output capacitance
* -3.0V in case of AC (Pulse width
≤
30ns)
minimum cycle
0.4
MITSUBISHI ELECTRIC
M5M5408BFP/TP/RT/KV/KR
revision-K0.1e, ' 98.07.30
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Output disable time after S high
5
t
CR
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
t
a
(A)
25
25
70
50
0
60
60
30
0
0
5
5
55
10
5
10
55
55
25
20
M5M5408BFP,TP,RT,
KV,KR-55
20
20
55
40
0
50
50
25
0
0
5
5
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
70
10
5
10
70
70
35
25
25
20
Input rise time and fall time
Reference level
Output loads
5.0V
VIH=2.4V,VIL=0.6V
(FP,TP,RT,KV,KR-70,-10 )
VOH=VOL=1.5V
Transition is measured ±500mV from
steady state voltage.
(for ten,tdis)
5ns
AC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V±10%, unless otherwise noted)
(1) TEST CONDITIONS
(2) READ CYCLE
Symbol
Parameter
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Max
Min
Max
Min
Read cycle time
Address access time
Chip select access time
Output enable access time
Data valid time after address
(3) WRITE CYCLE
Symbol
Parameter
Limits
Max
Min
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Write cycle time
Write pulse width
Address set up time
Address set up time with respect to W high
Chip select set up time
Data set up time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
Supply voltage
Input pulse
M5M5408BFP,TP,RT,
KV,KR-55
M5M5408BFP,TP,RT,
KV,KR-70
VIH=3.0V,VIL=0V
(FP,TP,RT,KV,KR-55 )
Fig.1, CL=100pF
(FP,TP,RT,KV,KR-70,-10 )
CL=30pF
(FP,TP,RT,KV,KR-55 )
CL=5pF
(for ten,tdis)
CL
DQ
Fig.1 Output load
CL Including scope and
jig capacitance
990
Ω
1.8k
Ω
M5M5408BFP,TP,RT,
KV,KR-70
100
10
5
10
100
100
50
35
35
Max
Min
M5M5408BFP,TP,RT,
KV,KR-10
35
35
100
60
0
80
80
35
0
0
5
5
Max
Min
M5M5408BFP,TP,RT,
KV,KR-10
MITSUBISHI ELECTRIC
M5M5408BFP/TP/RT/KV/KR
revision-K0.1e, ' 98.07.30
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
t
en
(W)
6
t
a
(A)
t
a
(S)
t
v
(A)
t
dis
(S)
t
a
(OE)
t
en
(OE)
t
dis
(OE)
t
CR
t
h
(D)
t
su
(D)
DQ
1~8
t
su
(S)
t
su
(A-WH)
t
en
(OE)
t