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MITSUBISHI ELECTRIC
Aug. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.0)
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
Standard 32 pin SOJ, 32 pin TSOP
Standard 50 pin SOJ, 50 pin TSOP
Single 3.3 0.3V supply
Low stand-by power dissipation
1.8mW (Max) LVCMOS input level
Low operating power dissipation
M5M467405Dxx-5,5S / M5M467805Dxx-5,5S 360.0mW (Max)
M5M467405Dxx-6,6S / M5M467805Dxx-6,6S 324.0mW (Max)
M5M465405Dxx-5,5S / M5M465805Dxx-5,5S 468.0mW (Max)
M5M465405Dxx-6,6S / M5M465805Dxx-6,6S 432.0mW (Max)
M5M465165Dxx-5,5S 504.0mW (Max)
M5M465165Dxx-6,6S 468.0mW (Max)
Self refresh capability*
Self refresh current 400µA (Max)
EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode , OE and W to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
:Applicable to self refresh version(M5M467405/465405/467805/465805/465165DJ,DTP-5S,-6S:option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
DESCRIPTION
The M5M467405/465405DJ,DTP is a 16777216-word by 4-bit, M5M467805/465805DJ,DTP is a 8388608-word by 8-bit, and
M5M465165DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are
suitable for large-capacity memory systems with high speed and low power dissipation.
±
*
ADDRESS
M5M465405Dxx
M5M467405Dxx
Part No.
XX=J,TP
FEATURES
Type name
M5M467405DXX-5,5S
M5M467805DXX-5,5S
M5M467405DXX-6,6S
M5M467805DXX-6,6S
M5M465405DXX-5,5S
M5M465805DXX-5,5S
M5M465405DXX-6,6S
M5M465805DXX-6,6S
access
time
(max.ns)
RAS
access
time
(max.ns)
CAS
(max.ns)
access
time
Address
time
(min.ns)
Cycle
dissipa-
(typ.mW)
Power
tion
50
60
50
13
15
13
25
30
25
84
104
84
300
250
390
13
15
13
access
time
(max.ns)
OE
60
15
30
104
325
15
Type name
access
time
(max.ns)
RAS
access
time
(max.ns)
CAS
(max.ns)
access
time
Address
time
(min.ns)
Cycle
access
time
(max.ns)
OE
M5M465165DXX-6,6S
M5M465165DXX-5,5S
50
60
13
15
25
30
84
104
13
15
dissipa-
(typ.mW)
Power
tion
420
390
(M5M467405Dxx/M5M465405Dxx/M5M467805Dxx/M5M465805Dxx)
(M5M465165Dxx)
M5M465805Dxx
M5M467805Dxx
M5M465165Dxx
A0-A12
Row Add. Col. Add.
Refresh
Refresh Cycle
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
A0-A10
A0-A11
A0-A11
8192/64ms
4096/64ms
4096/64ms
8192/128ms
4096/128ms
4096/128ms
Normal
S-version
A0-A12
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
A0-A9
A0-A11
A0-A10
8192/64ms
4096/64ms
4096/64ms
8192/128ms
4096/128ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
A0-A11
A0-A9
4096/64ms 4096/128ms
1
PRELIMINARY
Some of contents are subject to change without notice.
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MITSUBISHI ELECTRIC
Aug. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.0)
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
M5M465405DJ
M5M467405DJ
Outline 32P0N (400mil SOJ)
Vcc
DQ
2
W
RAS
A
11
A
10
A
0
A
1
A
2
A
3
Vcc
Vss
DQ
4
DQ
3
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
Vss
NC
NC
NC
NC
A
12
/NC(Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ
1
NC
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
Note
A12...M5M467405Dxx, NC...M5M465405Dxx
NO CONNECTION
:
:
M5M465405DTP
M5M467405DTP
Outline 32P3N (400mil TSOP Normal Bend)
Vcc
DQ
2
W
RAS
A
11
A
10
A
0
A
1
A
2
A
3
Vcc
Vss
DQ
4
DQ
3
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
Vss
NC
NC
NC
NC
A
12
/NC(Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ
1
NC
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN CONFIGURATION (TOP VIEW)
PIN DESCRIPTION
Pin Name
A
0
-A
12
DQ1-DQ4
RAS
CAS
W
OE
Vcc
Vss
Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Power Supply (+3.3V)
Ground (0V)
Output Enable Input
NC
No Connection
Pin Name
A
0
-A
11
DQ1-DQ16
RAS
UCAS
W
OE
Vcc
Vss
Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Power Supply (+3.3V)
Ground (0V)
Output Enable Input
NC
No Connection
Upper byte control
LCAS
Column Address Strobe Input
Lower byte control
Pin Name
A
0
-A
12
DQ1-DQ8
RAS
CAS
W
OE
Vcc
Vss
Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Power Supply (+3.3V)
Ground (0V)
Output Enable Input
NC
No Connection
M5M467405Dxx / M5M465405Dxx
M5M467805Dxx / M5M465805Dxx
M5M465165Dxx
XX=J, TP
M5M467400/465400DJ, DTP
2
background image
MITSUBISHI ELECTRIC
Aug. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.0)
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
NC
Note
A12...M5M467800Dxx, NC...M5M465800Dxx
NO CONNECTION
:
:
M5M465805DJ
M5M467805DJ
Outline 32P0N (400mil SOJ)
Vcc
DQ
2
W
RAS
A
11
A
10
A
0
A
1
A
2
A
3
Vcc
Vss
DQ
8
DQ
7
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
Vss
A
12
/NC(Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ
1
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ
4
DQ
3
DQ
6
DQ
5
Vss
Vcc
M5M465805DTP
M5M467805DTP
Outline 32P3N (400mil TSOP Normal Bend)
Vcc
DQ
2
W
RAS
A
11
A
10
A
0
A
1
A
2
A
3
Vcc
Vss
CAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
Vss
A
12
/NC(Note)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ
8
DQ
7
NC
DQ
4
DQ
3
DQ
6
DQ
5
Vss
Vcc
NC : NO CONNECTION
Outline 50P0G (400mil SOJ)
11
25
24
23
22
1
10
2
3
4
5
6
9
7
8
36
35
34
33
40
41
42
15
16
20
17
19
18
21
28
27
26
29
30
31
32
43
44
45
46
47
48
49
50
12
NC
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
A
0
A
1
A
2
A
3
NC
A
11
A
10
LCAS
DQ
9
DQ
1
DQ
2
DQ
3
DQ
4
Vss
DQ
8
DQ
7
DQ
6
DQ
5
DQ
15
DQ
14
DQ
13
DQ
10
DQ
11
DQ
12
DQ
16
NC
NC
12
Vcc
13
14
37
38
39
Vss
W
RAS
NC
NC
NC
NC
NC
M5M465165DJ
Vcc
Vcc
Vcc
Vss
Vss
Outline 50P3G (400mil TSOP Normal Bend)
11
25
24
23
22
1
10
2
3
4
5
6
9
7
8
36
35
34
33
40
41
42
15
16
20
17
19
18
21
28
27
26
29
30
31
32
43
44
45
46
47
48
49
50
12
NC
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
A
0
A
1
A
2
A
3
NC
A
11
A
10
LCAS
DQ
9
DQ
1
DQ
2
DQ
3
DQ
4
Vss
DQ
8
DQ
7
DQ
6
DQ
5
DQ
15
DQ
14
DQ
13
DQ
10
DQ
11
DQ
12
DQ
16
NC
NC
12
Vcc
13
14
37
38
39
Vss
W
RAS
NC
NC
NC
NC
NC
M5M465165DTP
Vss
Vss
Vcc
Vcc
Vcc
PIN CONFIGURATION (TOP VIEW)
M5M465165DJ, DTP
PIN CONFIGURATION (TOP VIEW)
M5M467805/465805DJ, DTP
3
background image
MITSUBISHI ELECTRIC
Aug. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.0)
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
FUNCTION
The M5M467405(805)/465405(805,165)DJ, DTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS
CAS
OE
Inputs
Input/Output
Refresh
Remark
W
Row
address
address
Column
Input
Output
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
DNC
DNC
ACT
APD
APD
APD
APD
APD
APD
APD
APD
OPN
VLD
OPN
IVD
VLD
EDO mode
identical
Standby
Hidden refresh
ACT
ACT
NAC
ACT
ACT
DNC
NAC
DNC
ACT
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
OPN
DNC
DNC
VLD
OPN
OPN
YES
YES
NO
CAS before RAS refresh
NO
NO
NO
NO
VLD
VLD
VLD
M5M467405Dxx / M5M465405Dxx / M5M467805Dxx / M5M465805Dxx
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
Operation
RAS
Inputs
UCAS
Lower byte read
Lower byte write
Word write
Stand-by
Hidden refresh
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
OE
W
NAC
DNC
DNC
ACT
DNC
RAS-only refresh
CAS before RAS refresh
ACT
ACT
DNC
LCAS
Upper byte read
NAC
NAC
NAC
ACT
Word read
ACT
ACT
ACT
NAC
ACT
Upper byte write
ACT
ACT
ACT
ACT
NAC
NAC
ACT
ACT
ACT
NAC
ACT
NAC
ACT
NAC
ACT
NAC
NAC
DNC
NAC
ACT
ACT
ACT
ACT
DNC
DNC
Input/Output
DQ1~DQ8
OPN
VLD
OPN
OPN
DQ9~DQ16
VLD
VLD
VLD
DIN
DNC
DIN
DNC
DIN
DIN
OPN
VLD
VLD
OPN
OPN
OPN
OPN
M5M465165Dxx
Row
address
address
Column
APD
APD
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
DNC
DNC
APD
APD
APD
APD
Refresh
Remark
YES
YES
NO
EDO mode
identical
NO
NO
NO
NO
NO
NO
YES
RAS-only refresh
ACT
NAC
DNC
DNC
APD
DNC
OPN
OPN
YES
APD
4
NAC
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MITSUBISHI ELECTRIC
Aug. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.0)
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
ADDRESS INPUTS
CLOCK GENERATOR
CIRCUIT
COLUMN DECODER
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ROW DECODER
ROW & COLUMN
ADDRESS BUFFER
MEMORY CELL
(67108864 BITS)
(4)
DATA IN
BUFFERS
(4)
DATA OUT
BUFFERS
Vcc (3.3V)
Vss (0V)
DQ1
OE
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
OUTPUT ENABLE
INPUT
COLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
WRITE CONTROL
INPUT
CAS
RAS
W
A0~A11
A0~
A12
(Note)
(Note)
Note
Refer to Page 1 (ADDRESS)
:
A12
(Note)
BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5