TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
135-m
Ω
-Maximum (5-V Input) High-Side
MOSFET Switch
D
500 mA Continuous Current per Channel
D
Short-Circuit and Thermal Protection With
Overcurrent Logic Output
D
Operating Range . . . 2.7-V to 5.5-V
D
Logic-Level Enable Input
D
2.5-ms Typical Rise Time
D
Undervoltage Lockout
D
20-
µ
A-Maximum Standby Supply Current
D
Bidirectional Switch
D
16-pin SOIC Package
D
Ambient Temperature Range, –40
°
C to 85
°
C
D
2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection
D
UL Listed – File No. E169910
description
The TPS2044 and TPS2054 quad power-
distribution switches are intended for applications
where heavy capacitive loads and short circuits
are likely to be encountered. The TPS2044 and the TPS2054 incorporate in single packages four 135-m
Ω
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches. Each switch is controlled by a logic enable that is compatible with 5-V logic and 3-V logic. Gate drive
is provided by an internal charge pump that controls the power-switch rise times and fall times to minimize
current surges during switching. The charge pump, requiring no external components, allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS2044 and TPS2054 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage.
Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry
ensures the switch remains off until valid input voltage is present.
The TPS2044 and TPS2054 are designed to limit at
0.9-A load. These power-distribution switches are available
in 16-pin small-outline integrated-circuit (SOIC) packages and operate over an ambient temperature range of
–40
°
C to 85
°
C.
AVAILABLE OPTIONS
RECOMMENDED
MAXIMUM CONTINUOUS
TYPICAL SHORT-CIRCUIT
PACKAGED DEVICES
TA
ENABLE
MAXIMUM CONTINUOUS
LOAD CURRENT
(A)
CURRENT LIMIT AT 25
°
C
(A)
SOIC
(D)†
–40
°
C to 85
°
C
Active low
0.5
0.9
TPS2044D
–40
°
C to 85
°
C
Active high
0.5
0.9
TPS2054D
† The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2044DR)
Copyright
©
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
IN1
EN1
EN2
GND2
IN2
EN3
EN4
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
TPS2044
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
IN1
EN1
EN2
GND2
IN2
EN3
EN4
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
TPS2054
D PACKAGE
(TOP VIEW)
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TPS2044 functional block diagram
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
†
Driver
Current
Limit
CS
†
Thermal
Sense
Charge
Pump
Power Switch
GND1
EN1
IN1
EN2
OC1
OUT1
OUT2
OC2
† Current sense
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
†
Driver
Current
Limit
CS
†
Thermal
Sense
Charge
Pump
Power Switch
GND2
EN3
IN2
EN4
OC3
OUT3
OUT4
OC4
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
TPS2044
TPS2054
EN1
3
–
I
Enable input. logic low turns on power switch, IN1-OUT1.
EN2
4
–
I
Enable input. Logic low turns on power switch, IN1-OUT2.
EN3
7
–
I
Enable input. Logic low turns on power switch, IN2-OUT3.
EN4
8
–
I
Enable input. Logic low turns on power switch, IN2-OUT4.
EN1
–
3
I
Enable input. Logic high turns on power switch, IN1-OUT1.
EN2
–
4
I
Enable input. Logic high turns on power switch, IN1-OUT2.
EN3
–
7
I
Enable input. Logic high turns on power switch, IN2-OUT3.
EN4
–
8
I
Enable input. Logic high turns on power switch, IN2-OUT4.
GND1
1
1
Ground.
GND2
5
5
Ground.
IN1
2
2
I
Input voltage.
IN2
6
6
I
Input voltage.
OC1
16
16
O
Overcurrent. Logic output active low, IN1-OUT1
OC2
13
13
O
Overcurrent. Logic output active low, IN1-OUT2
OC3
12
12
O
Overcurrent. Logic output active low, IN2-OUT3
OC4
9
9
O
Overcurrent. Logic output active low, IN2-OUT4
OUT1
15
15
O
Power-switch output, IN1-OUT1
OUT2
14
14
O
Power-switch output, IN1-OUT2
OUT3
11
11
O
Power-switch output, IN2-OUT3
OUT4
10
10
O
Power-switch output, IN2-OUT4
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
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DALLAS, TEXAS 75265
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 m
Ω
(V
I(INx)
= 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to INx and INx to OUTx
when disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 20
µ
A when a logic high is present on ENx (TPS2044) or a logic low is present
on ENx (TPS2054). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS2044 and TPS2054 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140
°
C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
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POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Input voltage range, V
I(INx)
(see Note1)
–0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O(OUTx)
(see Note1)
–0.3 V to V
I(INx)
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I(ENx)
or V
I(ENx)
–0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O(OUTx)
Internally limited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40
°
C to 125
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C
2 kV
. . . . . . . . . . . . . . . . . . . . . .
Machine model
0.2 kV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
°
C
TA = 70
°
C
POWER RATING
TA = 85
°
C
POWER RATING
D
725 mW
5.6 mW/
°
C
464 mW
377 mW
recommended operating conditions
TPS2044
TPS2054
UNIT
MIN
MAX
MIN
MAX
UNIT
Input voltage, VI(INx)
2.7
5.5
2.7
5.5
V
Input voltage, VI(ENx) or VI(ENx)
0
5.5
0
5.5
V
Continuous output current, IO(OUTx)
0
500
0
500
mA
Operating virtual junction temperature, TJ
–40
125
–40
125
°
C
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, V
I(IN)
= 5.5 V,
I
O
= rated current, V
I(ENx)
= 0 V, V
I(ENx)
= Hi (unless otherwise noted)
power switch
PARAMETER
TEST CONDITIONS†
TPS2044
TPS2054
UNIT
PARAMETER
TEST CONDITIONS†
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VI(INx) = 5 V,
IO = 0.5 A
TJ = 25
°
C,
80
95
80
95
Static drain-source on-state
resistance, 5-V operation
VI(INx) = 5 V,
IO = 0.5 A
TJ = 85
°
C,
90
120
90
120
rDS( )
VI(INx) = 5 V,
IO = 0.5 A
TJ = 125
°
C,
100
135
100
135
m
Ω
rDS(on)
VI(INx) = 3.3 V,
IO = 0.5 A
TJ = 25
°
C,
85
105
85
105
Static drain-source on-state
resistance, 3.3-V operation
VI(INx) = 3.3 V,
IO = 0.5 A
TJ = 85
°
C,
100
135
100
135
VI(INx) = 3.3 V,
IO = 0.5 A
TJ = 125
°
C,
115
150
115
150
t
Rise time output
VI(INx) = 5.5 V,
CL = 1
µ
F,
TJ = 25
°
C,
RL = 10
Ω
2.5
2.5
ms
tr
Rise time, output
VI(INx) = 2.7 V,
CL = 1
µ
F,
TJ = 25
°
C,
RL = 10
Ω
3
3
ms
tf
Fall time output
VI(INx) = 5.5 V,
CL = 1
µ
F,
TJ = 25
°
C,
RL = 10
Ω
4.4
4.4
ms
tf
Fall time, output
VI(INx) = 2.7 V,
CL = 1
µ
F,
TJ = 25
°
C,
RL = 10
Ω
2.5
2.5
ms
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input ENx or ENx
PARAMETER
TEST CONDITIONS
TPS2044
TPS2054
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIH
High-level input voltage
2.7 V
≤
VI(INx)
≤
5.5 V
2
2
V
VIL
Low level input voltage
4.5 V
≤
VI(INx)
≤
5.5 V
0.8
0.8
V
VIL
Low-level input voltage
2.7 V
≤
VI(INx)
≤
4.5 V
0.4
0.4
II
Input current
TPS2044
VI(ENx) = 0 V or VI(ENx) = VI(IN)
–0.5
0.5
µ
A
II
Input current
TPS2054
VI(ENx) = VI(INx) or VI(ENx) = 0 V
–0.5
0.5
µ
A
ton
Turnon time
CL = 100
µ
F, RL=10
Ω
20
20
ms
toff
Turnoff time
CL = 100
µ
F, RL=10
Ω
40
40
current limit
PARAMETER
TEST CONDITIONS†
TPS2044
TPS2054
UNIT
PARAMETER
TEST CONDITIONS†
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
IOS
Short-circuit output current
VI(INx) = 5 V, OUT connected to GND,
Device enable into short circuit
0.7
0.9
1.1
0.7
0.9
1.1
A
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range, V
I(IN)
= 5.5 V,
I
O
= rated current, V
I(ENx)
= 0 V, V
I(ENx)
= Hi (unless otherwise noted) (continued)
supply current
PARAMETER
TEST CONDITIONS
TPS2044
TPS2054
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Supply
TJ = 25
°
C
TPS2044
0.03
2
Su
ly
current,
No Load
VI(ENx) = VI(INx) –40
°
C
≤
TJ
≤
125
°
C
TPS2044
20
µ
A
,
low-level
t
t
on OUTx
VI(EN ) = 0 V
TJ = 25
°
C
TPS2054
0.03
2
µ
A
output
VI(ENx) = 0 V
–40
°
C
≤
TJ
≤
125
°
C
TPS2054
20
Supply
V
0 V
TJ = 25
°
C
TPS2044
160
200
Su
ly
current,
No Load
VI(ENx) = 0 V
–40
°
C
≤
TJ
≤
125
°
C
TPS2044
200
µ
A
,
high-level
t
t
on OUTx
VI(EN ) = VI(IN )
TJ = 25
°
C
TPS2054
160
200
µ
A
output
VI(ENx) = VI(INx)
–40
°
C
≤
TJ
≤
125
°
C
TPS2054
200
Leakage
OUTx
connected
VI(ENx) = VI(INx) –40
°
C
≤
TJ
≤
125
°
C
TPS2044
200
µ
A
g
current
connected
to ground
VI(ENx) = 0 V
–40
°
C
≤
TJ
≤
125
°
C
TPS2054
200
µ
A
Reverse
leakage
IN = high
VI(EN) = 0 V
TJ = 25
°
C
TPS2044
0.3
µ
A
leakage
current
g
impedance
VI(EN) = Hi
TJ = 25
°
C
TPS2054
0.3
µ
A
undervoltage lockout
PARAMETER
TEST CONDITIONS
TPS2044
TPS2054
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Low-level input voltage
2
2.5
2
2.5
V
Hysteresis
TJ = 25
°
C
100
100
mV
overcurrent OCx
PARAMETER
TEST CONDITIONS
TPS2044
TPS2054
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Sink current†
VO = 5 V
10
10
mA
Output low voltage
IO = 5 mA, VOL(OCx)
0.5
0.5
V
Off-state current†
VO = 5 V, VO = 3.3 V
1
1
µ
A
† Specified by design, not production tested.
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
8
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
RL
CL
OUTx
tr
tf
90%
90%
10%
10%
50%
50%
90%
10%
VO(OUTx)
VI(ENx)
VO(OUTx)
VOLTAGE WAVEFORMS
TEST CIRCUIT
ton
toff
50%
50%
90%
10%
VI(ENx)
VO(OUTx)
ton
toff
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time
with 0.1-
µ
F Load
Figure 3. Turnoff Delay and Fall Time
with 0.1-
µ
F Load
VO(OUT)
(2 V/div)
0
1
2
3
4
5
6
t – Time – ms
7
8
9
10
VI(IN) = 5 V
TA = 25
°
C
CL = 0.1
µ
F
VI(EN)
(5 V/div)
0
1000
2000
3000
t – Time – ms
4000
5000
VI(IN) = 5 V
TA = 25
°
C
CL = 0.1
µ
F
VI(EN)
(5 V/div)
VO(OUT)
(2 V/div)
TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999
9
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Turnon Delay and Rise Time
with 1-
µ
F Load
Figure 5. Turnoff Delay and Fall T