PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iv
182
14.4.2 LOOP TRANSMIT PORT POLLING WEIGHT RECORD
183
14.4.3 LOOP TRANSMIT CLASS STATUS RECORD
............... 184
15
TEST FEATURES DESCRIPTION
...................................................... 186
15.1 JTAG TEST PORT
.................................................................... 186
16
OPERATION
......................................................................................... 190
17
FUNCTIONAL TIMING
......................................................................... 191
17.1 MICROPROCESSOR INTERFACE
.......................................... 191
17.2 SDRAM INTERFACE
................................................................ 193
17.3 ZBT SSRAM INTERFACE
......................................................... 195
17.4 LATE WRITE SSRAM INTERFACE
.......................................... 196
17.5 ANY-PHY/UTOPIA INTERFACES
............................................. 197
17.5.1 RECEIVE MASTER/TRANSMIT SLAVE INTERFACES
. 197
17.5.2 TRANSMIT MASTER/RECEIVE SLAVE INTERFACES
. 200
18
ABSOLUTE MAXIMUM RATINGS
....................................................... 205
19
D.C. CHARACTERISTICS
................................................................... 206
20
A.C. TIMING CHARACTERISTICS
...................................................... 208
20.1 JTAG INTERFACE
.................................................................... 213
21
ORDERING AND THERMAL INFORMATION
...................................... 215
22
MECHANICAL INFORMATION
............................................................ 216
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
1
1 DEFINITIONS
Table 1
- Terminology
Term
Definition
AAL5
ATM Adaptation Layer
ABR
Available Bit Rate
Any-PHY
Interoperable version of UTOPIA and SCI-PHY, with
inband addressing.
ATM
Asynchronous Transfer Mode
BOM
Beginning of Message
CBI
Common Bus Interface
CBR
Constant Bit Rate
CDV
Cell Delay Variation
CDVT
Cell Delay Variation Tolerance
CES
Circuit Emulation Service
CLP
Cell Loss Priority
COM
Continuation of Message
COS
Class of Service
CTD
Cell Transfer Delay
DLL
Delay Locked Loop
DSL
Digital Subscriber Loop
DSLAM
DSL access Multiplexer
DUPLEX
PMC UTOPIA deserializer
ECI
Egress Connection Identifier
EFCI
Early forward congestion indicator
EOM
End of Message
EPD
Early Packet Discard
FIFO
First-In-First-Out
GCRA
Generic Cell Rate Algorithm
GFR
Guaranteed Frame Rate
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2
IBT
Intrinsic Burst Tolerance
ICI
Ingress Connection Identifier
MBS
Maximum Burst Size
MCR
Minimum Cell Rate
OAM
Operation, Administration and Maintenance
PCR
Peak Cell Rate
PDU
Packet Data Unit
PHY
Physical Layer Device
PPD
Partial Packet Discard
PTI
Payload Type Indicator
QOS
Quality of Service
QRT
PMC’s traffic management device
QSE
PMC’s switch fabric device
RRM
Reserved or Resource Management
SAR
Segmentation and Re-assembly
SCI-PHY
PMC-Sierra enhanced UTOPIA bus
SCR
Sustained Cell Rate
S/UNI-ATLAS PMC’s OAM and Address Resolution device
UBR
Unspecified Bit Rate
UTOPIA
Universal Test & Operations PHY Interface for ATM
VBR
Variable Bit Rate
VCC
Virtual Channel Connection
VORTEX
PMC UTOPIA/Any-PHY slave serializer
VPC
Virtual Path Connection
WAN
Wide Area Network
WIRR
Weighted Interleaved Round Robin
WRR
Weighted Round Robin
ZBT
Zero Bus Turnaround
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
3
2 FEATURES
• Monolithic single chip ATM traffic manager providing VC queuing/shaping and
VC, Class Of Service(COS), and Port scheduling, congestion management,
and switching across 128 ports.
• Targeted at systems where many low speed ATM data ports are multiplexed
onto few high speed ports.
• 869 Kcells/s non shaped throughput in full duplex.
• 1.73 Mcells/s non shaped throughput in half duplex.
• 1.42 Mcells/s shaped throughput (aggregate of the four shapers).
• Supports four WAN uplink ports, with port aliasing.
• Supports 128 loop ports. Loop port can support an uncongested rate up to
230Kcells/sec.
• Provides 4 Classes of Service per port with configurable traffic parameters
enabling support for a mix of CBR, VBR, GFR, and UBR classes.
• Provides 1024 per-VC queues individually assignable to any COS in any port.
• Provides support of up to 256k cells of shared buffer.
• Provides 2 independent cell emission schedulers, 1 for the WAN ports, and 1
for the Loop ports. The schedulers have the following features: Three level
hierarchical cell emission scheduling at the port, class, and VC levels.
• WAN Port Scheduling:
• Weighted Interleaved Round Robin WAN port scheduling.
• Per port Priority Fair Queued class scheduling with port
independence.
• Per
Class:
• Weighted Fair Queued VC scheduling with class independence
or,
PM7329 S/UNI-APEX-1K800
DATASHEET
PMC-2010141
ISSUE 2
ATM TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
4
• Shaped Fair Queued VC scheduling applying rate based per VC
shaping or,
• Frame Continuous Queued VC scheduling for VC Merge and
packet re-assembly.
• Loop Port Scheduling:
• Weighted Interleaved Round Robin Loop port scheduling.
• Per port Priority Fair Queued class scheduling with port
independence.
• Per
Class:
• Weighted Fair Queued VC scheduling with class independence
or,
• Frame Continuous Queued scheduling for VC Merge and
packet re-assembly.
• Congestion Control applied per-VC, per-class, per-port and per-direction.
• Flexible, progressive hierarchical throttling of buffer consumption.
Provides sharing of resources during low congestion, memory reservation
during high congestion.
• Applies EPD and PPD on a per-VC, per-class, per-port, and per-direction
basis with CLP differentiation, following emerging GFR standards.
• Provides EFCI marking on a per VC basis.
• Provides interrupts and indication of most recent VC/Class/Port that
exceeded maximum thresholds.
• Provides flexible VPC or VCC switching selectable on a per VC basis as
follows:
• Any WAN port to any WAN port.
• Any WAN port to any Loop port.
• Any Loop port to any WAN port.
• Any Loop port to any Loop port.
