PM5372
Preliminary
PMC-Sierra,Inc.
40 Gbit/s Transport Switching Element
TSE
PMC-2000328 (P1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2000
FEATURES
• Implements a Time-Space-Time fabric
with STS-1/AU-3 granularity.
• Provides 64 ingress STS-12 equivalent
ports for a total of 64*12 = 768 STS-1
flows.
• Supports non-blocking permutation
switching of 768 STS-1 flows at STS-1
granularity.
• Provides 64 egress STS-12 equivalent
ports consisting of 768 STS-1 flows.
• Interfaces to STS-48 and STS-192
devices by aggregating 4 and 16 STS-
12 equivalent flows respectively.
• Supports multicast and broadcast of
STS-1 streams.
• Supports STS-12 equivalent flows with
an extended 8B/10B protocol over
777.6 MHz LVDS links.
• Supports multi-plane (inverse
multiplexed) switch architectures in
conjunction with the PM5310 TBS
device and PM7390 S/UNI
®
-MACH48.
• Recovers clock and data at each
ingress port, synchronizes with an
internal 77.76 MHz clock, and
produces egress streams with a
common 777.6 MHz clock.
• Detects and reports inactive or erred
LVDS links via the microprocessor
interface.
• Supports two sets of switch settings
and a controlled method of changing
settings on STS-1 frame boundaries.
• Supports multiple fabric architectures
that range from 40 Gbit/s (1 TSE) to
160 Gbit/s (4 TSE devices) in a single
stage, and up to 2.5 Tbit/s using multi-
stage fabrics.
• Ingress to egress STS-1 switching
latency of approximately 900 ns.
• Supported by an efficient algorithm to
compute control settings for all
permutation loads for all supported
fabric architectures. Algorithms are
also available for multicast/broadcast
allocation.
• 1.8 V CMOS core and 3.3 V
CMOS/LVDS input/output.
• Requires no external RAMs or logic
parts.
• Provides a standard IEEE 1149.1
JTAG port.
• Power Consumption of 13 W
(maximum).
• Packaged in a 520 pin 40mm by 40mm
UltraBGA.
• Supports a 16-bit microprocessor
interface which is used to initialize the
device, to write switch settings into on-
chip control tables, and to monitor
device performance.
J T A G
TRSTB
TCK
TDI
TMS
TDO
RN[4]
Rx 8b/10b
Frame Aligner
R 8 F A # 3
Data
Recovery Unit
D R U # 3
L V D S
Receiver
RXLV #3
Rx 8b/10b
Frame Aligner
R 8 F A # 4
Data
Recovery Unit
D R U # 4
L V D S
Receiver
RXLV #4
Rx 8b/10b
Frame Aligner
R 8 F A # 2
Data
Recovery Unit
D R U # 2
L V D S
Receiver
RXLV #2
Rx 8b/10b
Frame Aligner
R 8 F A # 1
Data
Recovery Unit
D R U # 1
L V D S
Receiver
RXLV #1
RP[4]
RN[3]
RP[3]
RN[2]
RP[2]
RN[1]
RP[1]
Egress
T i m e
Switch
Element
E T S E
#16
L V D S
Transmitter
TXLV #63
Serializer
PISO #63
Tx 8b/10b
Disp. Encoder
T 8 D E # 6 3
L V D S
Transmitter
TXLV #64
Serializer
PISO #64
Tx 8b/10b
Disp. Encoder
T 8 D E # 6 4
L V D S
Transmitter
TXLV #62
Serializer
PISO #62
Tx 8b/10b
Disp. Encoder
T 8 D E # 6 2
L V D S
Transmitter
TXLV #61
Serializer
PISO #61
Tx 8b/10b
Disp. Encoder
T 8 D E # 6 1
TP[61]
TN[61]
TP[62]
TN[62]
TP[63]
TN[63]
TP[64]
TN[64]
Egress
T i m e
Switch
Element
E T S E
#1
L V D S
Transmitter
TXLV #3
Serializer
PISO #3
Tx 8b/10b
Disp. Encoder
T 8 D E # 3
L V D S
Transmitter
TXLV #4
Serializer
PISO #4
Tx 8b/10b
Disp. Encoder
T 8 D E # 4
L V D S
Transmitter
TXLV #2
Serializer
PISO #2
Tx 8b/10b
Disp. Encoder
T 8 D E # 2
L V D S
Transmitter
TXLV #1
Serializer
PISO #1
Tx 8b/10b
Disp. Encoder
T 8 D E # 1
TP[1]
TN[1]
TP[2]
TN[2]
TP[3]
TN[3]
TP[4]
TN[4]
D[15:0]
A[12:0]
CSB
ALE
RDB
WRB
INTB
RSTB
SYSCLK
CMP
RJOFP
TJOFP
C S T R
Clock
Synthesizer
C S U
LVDS Transmit
Reference
T X R E F
Cross-
bar
Space
Switch
Element
S S W T
Rx 8b/10b
Frame Aligner
R 8 F A # 6 3
Data
Recovery Unit
DRU #63
L V D S
Receiver
RXLV #63
RN[63]
RP[63]
RN[64]
Rx 8b/10b
Frame Aligner
R 8 F A # 6 4
Data
Recovery Unit
DRU #64
L V D S
Receiver
RXLV #64
RP[64]
Rx 8b/10b
Frame Aligner
R 8 F A # 6 1
Data
Recovery Unit
DRU #61
L V D S
Receiver
RXLV #61
RN[61]
RP[61]
Rx 8b/10b
Frame Aligner
R 8 F A # 6 2
Data
Recovery Unit
DRU #62
L V D S
Receiver
RXLV #62
RN[62]
RP[62]
• •
•
• •
•
Microprocessor
Interface
Ingress
T i m e
Switch
Element
I T S E
#16
Ingress
T i m e
Switch
Element
ITSE #1
BLOCK DIAGRAM
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
40 Gbit/s Transport Switching Element
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-2000328 (P1)
© Copyright PMC-Sierra,
Inc. 2000. All rights reserved.
March 2000
S/UNI is a registered
trademark of PMC-Sierra,
Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Preliminary
PM5372 TSE
APPLICATIONS
In combination with the PM5310 TBS
(TelecomBus Serializer and Time-Space
switching stage), the PM5315
SPECTRA-2488, the PM5316
SPECTRA-4X155, and the PM7390
S/UNI-MACH48, the PM5372 TSE
supports a variety of flexible Layer 1 /
Layer 2 architectures. These architec-
tures can implement features commonly
found in DCS, ADM, and multi-service
switch/router equipment.
The PM5372 TSE provides the function-
ality that enables networking equipment
to:
• Connect to (multiple) SONET rings.
• Participate in mesh-connected
architectures.
• Serve as SONET-connected terminal
multiplexers.
• Groom traffic at STS-1/AU-3
granularity.
• Support channelization of OC-
3/12/48/192 line rates.
• Support concatenated lines rates
including STS-1 (DS-3), STS-3c, STS-
12c, STS-48c and STS-192c.
• Support add, drop, and drop-and-
continue.
• Support UPSR, 2-BLSR, 4-BLSR, and
1+1 or 1:N APS.
• Support mesh-based APS systems.
TYPICAL APPLICATIONS
MULTI-SERVICE ATM/POS SWITCH PORT APPLICATION
P M 5 3 7 2
TSE
(Protection X-
Connect)
P M 5 3 7 2
TSE
(Working X-
Connect)
4x777.6 MHz
LVDS Links
4x777.6 MHz
LVDS Links
4x777.6 MHz
LVDS Links
4x777.6 MHz
LVDS Links
SONET Ring/PHY Layer
40 Gbit/s STS-1 Fabric
Multi-Service Layer
P M 5 3 1 0
T B S
P M 5 3 1 0
T B S
P M 5 3 1 0
T B S
•
•
•
•
•
•
Optical
Transceiver
P M 5 3 1 5
SPECTRA-2488
SERDES
N
Optical
Transceiver
P M 5 3 1 5
SPECTRA-2488
SERDES
8
1
Optical
Transceiver
P M 5 3 1 5
SPECTRA-2488
SERDES
OC-48
P M 7 3 9 0
S/UNI-MACH48
P M 7 3 9 0
S/UNI-MACH48
ATM Layer
Device
P M 7 3 9 0
S/UNI-MACH48
1
N
8
POS-PHY
Level 3/
UTOPIA
Level 3
•
•
•
•
•
•
OC-48
OC-48
IP Layer
Device
POS-PHY
Level 3
ATM or
IP Layer
Device
POS-PHY
Level 3