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PM7366
FREEDM™-8
EIGHT CHANNEL FRAME ENGINE AND
DATALINK MANAGER
PROPRIETARY AND CONFIDENTIAL
ISSUE 4: AUGUST 2001
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
REVISION HISTORY
Issue No.
Issue Date
Details of Change
Issue 4
August 2001
Added patent information to legal footer, last page. Change
bars pertain to issue 3.
Issue 3
August 1999
Updated to include PBGA package option
· Addition of new pinout, pin description, and mechanical
diagram.
Incorporated Documentation Errata from PMC-980452,
“PM7366 FREEDM-8 Revision D Device Errata Sheet” Issue 4.
Issue 2
May 1998
Updated for Freedm-8 Release to Production
Issue 1
Sept. 1997
Document created for Prototype release
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CONTENTS
1 FEATURES ....................................................................................................................... 1
2 APPLICATIONS ................................................................................................................ 3
3 REFERENCES.................................................................................................................. 4
4 APPLICATION
EXAMPLES .............................................................................................. 5
5 BLOCK
DIAGRAM ............................................................................................................ 6
6 DESCRIPTION.................................................................................................................. 7
7 PIN
DIAGRAM................................................................................................................... 9
8 PIN
DESCRIPTION..........................................................................................................11
9 FUNCTIONAL
DESCRIPTION........................................................................................ 33
9.1
HIGH-LEVEL DATA LINK CONTROL PROTOCOL ........................................... 33
9.2 RECEIVE
CHANNEL ASSIGNER ...................................................................... 34
9.2.1 LINE
INTERFACE............................................................................. 34
9.2.2 PRIORITY
ENCODER...................................................................... 34
9.2.3 CHANNEL
ASSIGNER ..................................................................... 35
9.2.4 LOOPBACK
CONTROLLER ............................................................ 35
9.3
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ........................ 35
9.3.1 HDLC
PROCESSOR ........................................................................ 36
9.3.2 PARTIAL
PACKET BUFFER PROCESSOR..................................... 36
9.4
RECEIVE DMA CONTROLLER ......................................................................... 38
9.4.1 DATA
STRUCTURES ....................................................................... 38
9.4.2 DMA
TRANSACTION
CONTROLLER ............................................. 48
9.4.3
WRITE DATA PIPELINE/MUX .......................................................... 48
9.4.4
DESCRIPTOR INFORMATION CACHE........................................... 48
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9.4.5
FREE QUEUE CACHE..................................................................... 48
9.5 PCI
CONTROLLER............................................................................................ 49
9.5.1 MASTER
MACHINE ......................................................................... 49
9.5.2 MASTER
LOCAL
BUS INTERFACE................................................. 51
9.5.3 TARGET
MACHINE.......................................................................... 52
9.5.4
CBI BUS INTERFACE ...................................................................... 54
9.5.5
ERROR / BUS CONTROL................................................................ 54
9.6
TRANSMIT DMA CONTROLLER ...................................................................... 54
9.6.1 DATA
STRUCTURES ....................................................................... 55
9.6.2 TASK
PRIORITIES ........................................................................... 66
9.6.3 DMA
TRANSACTION
CONTROLLER ............................................. 66
9.6.4
READ DATA PIPELINE..................................................................... 66
9.6.5
DESCRIPTOR INFORMATION CACHE........................................... 66
9.6.6
FREE QUEUE CACHE..................................................................... 66
9.7
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER .................... 67
9.7.1
TRANSMIT HDLC PROCESSOR..................................................... 67
9.7.2
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR ................. 67
9.8 TRANSMIT
CHANNEL ASSIGNER ................................................................... 69
9.8.1 LINE
INTERFACE............................................................................. 70
9.8.2 PRIORITY
ENCODER...................................................................... 70
9.8.3 CHANNEL
ASSIGNER ..................................................................... 71
9.9 PERFORMANCE
MONITOR ............................................................................. 71
9.10 JTAG
TEST
ACCESS
PORT INTERFACE ........................................................ 71
9.11
PCI HOST INTERFACE ..................................................................................... 71
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10
NORMAL MODE REGISTER DESCRIPTION ................................................................ 76
10.1 PCI
HOST
ACCESSIBLE REGISTERS ............................................................. 76
11
PCI CONFIGURATION REGISTER DESCRIPTION .................................................... 216
11.1
PCI CONFIGURATION REGISTERS .............................................................. 216
12 TEST
FEATURES
DESCRIPTION ............................................................................... 226
12.1 TEST
MODE
REGISTERS .............................................................................. 226
12.2 JTAG
TEST
PORT ........................................................................................... 227
12.2.1 IDENTIFICATION
REGISTER........................................................ 228
12.2.2 BOUNDARY
SCAN REGISTER ..................................................... 228
13 OPERATIONS............................................................................................................... 241
13.1 EQUAD
CONNECTIONS................................................................................. 241
13.2 TOCTL
CONNECTIONS.................................................................................. 241
13.3 JTAG
SUPPORT.............................................................................................. 242
14 FUNCTIONAL
TIMING.................................................................................................. 248
14.1
RECEIVE LINK INPUT TIMING ....................................................................... 248
14.2
TRANSMIT LINK OUTPUT TIMING ................................................................ 249
14.3 PCI
INTERFACE .............................................................................................. 250
14.4 BERT
INTERFACE .......................................................................................... 258
15
ABSOLUTE MAXIMUM RATINGS................................................................................ 260
16 D.C.
CHARACTERISTICS ............................................................................................ 261
17 FREEDM-8
TIMING
CHARACTERISTICS ................................................................... 263
18 ORDERING
AND
THERMAL
INFORMATION .............................................................. 269
19 MECHANICAL
INFORMATION..................................................................................... 270
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LIST OF REGISTERS
REGISTER 0X000 : FREEDM-8 MASTER RESET ..................................................................... 77
REGISTER 0X004 : FREEDM-8 MASTER INTERRUPT ENABLE ............................................. 79
REGISTER 0X008 : FREEDM-8 MASTER INTERRUPT STATUS.............................................. 83
REGISTER 0X00C : FREEDM-8 MASTER CLOCK / BERT ACTIVITY MONITOR AND
ACCUMULATION TRIGGER .......................................................................................... 87
REGISTER 0X010 : FREEDM-8 MASTER LINK ACTIVITY MONITOR...................................... 89
REGISTER 0X014 : FREEDM-8 MASTER LINE LOOPBACK .................................................... 91
REGISTER 0X020 : FREEDM-8 MASTER BERT CONTROL..................................................... 93
REGISTER 0X024 : FREEDM-8 MASTER PERFORMANCE MONITOR CONTROL ................ 95
REGISTER 0X040 : GPIC CONTROL......................................................................................... 98
REGISTER 0X100 : RCAS INDIRECT LINK AND TIME-SLOT SELECT.................................. 101
REGISTER 0X104 : RCAS INDIRECT CHANNEL DATA .......................................................... 103
REGISTER 0X108 : RCAS FRAMING BIT THRESHOLD ......................................................... 105
REGISTER 0X10C : RCAS CHANNEL DISABLE...................................................................... 107
REGISTER 0X180 : RCAS LINK #0 CONFIGURATION ........................................................... 109
REGISTER 0X184 - 0X188 : RCAS LINK #1 TO #2 CONFIGURATION....................................111
REGISTER 0X18C : RCAS LINK #3 CONFIGURATION............................................................113
REGISTER 0X190-0X19C : RCAS LINK #4 TO LINK #7 CONFIGURATION ............................115
REGISTER 0X200 : RHDL INDIRECT CHANNEL SELECT.......................................................117
REGISTER 0X204 : RHDL INDIRECT CHANNEL DATA REGISTER #1 ...................................119
REGISTER 0X208 : RHDL INDIRECT CHANNEL DATA REGISTER #2 .................................. 122
REGISTER 0X210 : RHDL INDIRECT BLOCK SELECT .......................................................... 124
REGISTER 0X214 : RHDL INDIRECT BLOCK DATA ............................................................... 126
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REGISTER 0X220 : RHDL CONFIGURATION.......................................................................... 128
REGISTER 0X224 : RHDL MAXIMUM PACKET LENGTH........................................................ 130
REGISTER 0X280 : RMAC CONTROL ..................................................................................... 131
REGISTER 0X284 : RMAC INDIRECT CHANNEL PROVISIONING ........................................ 134
REGISTER 0X288 : RMAC PACKET DESCRIPTOR TABLE BASE LSW ................................ 136
REGISTER 0X28C : RMAC PACKET DESCRIPTOR TABLE BASE MSW ............................... 137
REGISTER 0X290 : RMAC QUEUE BASE LSW ...................................................................... 139
REGISTER 0X294 : RMAC QUEUE BASE MSW ..................................................................... 140
REGISTER 0X298 : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE
QUEUE START ............................................................................................................. 142
REGISTER 0X29C : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE
QUEUE WRITE............................................................................................................. 143
REGISTER 0X2A0 : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE
QUEUE READ............................................................................................................... 144
REGISTER 0X2A4 : RMAC PACKET DESCRIPTOR REFERENCE LARGE BUFFER FREE
QUEUE END................................................................................................................. 145
REGISTER 0X2A8 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE
QUEUE START ............................................................................................................. 146
REGISTER 0X2AC : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE
QUEUE WRITE............................................................................................................. 147
REGISTER 0X2B0 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE
QUEUE READ............................................................................................................... 148
REGISTER 0X2B4 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE
QUEUE END................................................................................................................. 149
REGISTER 0X2B8 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE START. 150
REGISTER 0X2BC : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE WRITE 151
REGISTER 0X2C0 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE READ .. 152
REGISTER 0X2C4 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE END..... 153
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REGISTER 0X300 : TMAC CONTROL...................................................................................... 154
REGISTER 0X304 : TMAC INDIRECT CHANNEL PROVISIONING......................................... 156
REGISTER 0X308 : TMAC DESCRIPTOR TABLE BASE LSW ................................................ 158
REGISTER 0X30C : TMAC DESCRIPTOR TABLE BASE MSW .............................................. 159
REGISTER 0X310 : TMAC QUEUE BASE LSW ....................................................................... 161
REGISTER 0X314 : TMAC QUEUE BASE MSW ...................................................................... 162
REGISTER 0X318 : TMAC DESCRIPTOR REFERENCE FREE QUEUE START ................... 164
REGISTER 0X31C TMAC DESCRIPTOR REFERENCE FREE QUEUE WRITE .................... 165
REGISTER 0X320 : TMAC DESCRIPTOR REFERENCE FREE QUEUE READ ..................... 166
REGISTER 0X324 : TMAC DESCRIPTOR REFERENCE FREE QUEUE END ....................... 167
REGISTER 0X328 :TMAC DESCRIPTOR REFERENCE READY QUEUE START.................. 168
REGISTER 0X32C : TMAC DESCRIPTOR REFERENCE READY QUEUE WRITE................ 169
REGISTER 0X330 : TMAC DESCRIPTOR REFERENCE READY QUEUE READ .................. 170
REGISTER 0X334 : TMAC DESCRIPTOR REFERENCE READY QUEUE END..................... 171
REGISTER 0X380 : THDL INDIRECT CHANNEL SELECT ...................................................... 172
REGISTER 0X384 : THDL INDIRECT CHANNEL DATA #1 ...................................................... 174
REGISTER 0X388 : THDL INDIRECT CHANNEL DATA #2 ...................................................... 177
REGISTER 0X38C : THDL INDIRECT CHANNEL DATA #3...................................................... 179
REGISTER 0X3A0 : THDL INDIRECT BLOCK SELECT .......................................................... 183
REGISTER 0X3A4 : THDL INDIRECT BLOCK DATA ............................................................... 185
REGISTER 0X3B0 : THDL CONFIGURATION.......................................................................... 187
REGISTER 0X400 : TCAS INDIRECT LINK AND TIME-SLOT SELECT .................................. 189
REGISTER 0X404 : TCAS INDIRECT CHANNEL DATA........................................................... 191
REGISTER 0X408 : TCAS FRAMING BIT THRESHOLD ......................................................... 193
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REGISTER 0X40C : TCAS IDLE TIME-SLOT FILL DATA......................................................... 195
REGISTER 0X410 : TCAS CHANNEL DISABLE....................................................................... 196
REGISTER 0X480 : TCAS LINK #0 CONFIGURATION............................................................ 198
REGISTER 0X484-0X488 : TCAS LINK #1 TO LINK #2 CONFIGURATION ............................ 200
REGISTER 0X48C : TCAS LINK #3 CONFIGURATION ........................................................... 202
REGISTER 0X490-0X49C : TCAS LINK #4 TO LINK #7 CONFIGURATION ........................... 204
REGISTER 0X500 : PMON STATUS......................................................................................... 206
REGISTER 0X504 : PMON RECEIVE FIFO OVERFLOW COUNT.......................................... 208
REGISTER 0X508 : PMON RECEIVE FIFO UNDERFLOW COUNT ....................................... 210
REGISTER 0X50C : PMON CONFIGURABLE COUNT #1....................................................... 212
REGISTER 0X510 : PMON CONFIGURABLE COUNT #2 ....................................................... 214
REGISTER 0X00 : VENDOR IDENTIFICATION/DEVICE IDENTIFICATION............................ 217
REGISTER 0X04 : COMMAND/STATUS................................................................................... 218
REGISTER 0X08 : REVISION IDENTIFIER/CLASS CODE ...................................................... 221
REGISTER 0X0C : CACHE LINE SIZE/LATENCY TIMER/HEADER TYPE ............................. 222
REGISTER 0X10 : CBI MEMORY BASE ADDRESS REGISTER ............................................. 223
REGISTER 0X3C : INTERRUPT LINE / INTERRUPT PIN / MIN_GNT / MAX_LAT ................. 225
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LIST OF FIGURES
FIGURE 1 – HDLC FRAME ......................................................................................................... 33
FIGURE 2 – CRC GENERATOR ................................................................................................. 33
FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ............................................................ 37
FIGURE 4 – RECEIVE PACKET DESCRIPTOR ......................................................................... 39
FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE ............................................................. 42
FIGURE 6 – RPDRF AND RPDRR QUEUES.............................................................................. 44
FIGURE 7 – RPDRR QUEUE OPERATION ................................................................................ 46
FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE................................... 47
FIGURE 9 – GPIC ADDRESS MAP ............................................................................................. 53
FIGURE 10 – TRANSMIT DESCRIPTOR.................................................................................... 55
FIGURE 11 – TRANSMIT DESCRIPTOR TABLE........................................................................ 58
FIGURE 12 – TDRR AND TDRF QUEUES ................................................................................. 60
FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE .............................. 62
FIGURE 14 – TD LINKING .......................................................................................................... 65
FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE .......................................................... 68
FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) ........................................................... 238
FIGURE 17 – OUTPUT CELL (OUT_CELL).............................................................................. 239
FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL).................................................................... 239
FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS....................... 240
FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ................................................................ 242
FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE .................................................. 244
FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ...................................................... 248
FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ...................................................... 248
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FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING ...................................................... 249
FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING.................................................... 249
FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING.................................................... 250
FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING.................................................... 250
FIGURE 28 – PCI READ CYCLE............................................................................................... 252
FIGURE 29 – PCI WRITE CYCLE............................................................................................. 253
FIGURE 30 – PCI TARGET DISCONNECT .............................................................................. 254
FIGURE 31 – PCI TARGET ABORT .......................................................................................... 254
FIGURE 32 – PCI BUS REQUEST CYCLE ............................................................................... 255
FIGURE 33 – PCI INITIATOR ABORT TERMINATION ............................................................. 255
FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE.......................................................................... 256
FIGURE 35 – PCI FAST BACK TO BACK ................................................................................. 258
FIGURE 36 – RECEIVE BERT PORT TIMING.......................................................................... 258
FIGURE 37 – TRANSMIT BERT PORT TIMING ....................................................................... 259
FIGURE 38 – RECEIVE LINK INPUT TIMING .......................................................................... 264
FIGURE 39 – BERT INPUT TIMING.......................................................................................... 264
FIGURE 40 – TRANSMIT LINK OUTPUT TIMING.................................................................... 265
FIGURE 41 – BERT OUTPUT TIMING...................................................................................... 266
FIGURE 42 – PCI INTERFACE TIMING.................................................................................... 267
FIGURE 43 – JTAG PORT INTERFACE TIMING...................................................................... 268
FIGURE 44 – 256 PIN ENHANCED BALL GRID ARRAY (SBGA)............................................. 270
FIGURE 45 – 272 PIN PLASTIC BALL GRID ARRAY (PBGA).................................................. 271
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LIST OF TABLES
TABLE 1 – LINE SIDE INTERFACE SIGNALS (36)......................................................................11
TABLE 2 – PCI HOST INTERFACE SIGNALS (51)..................................................................... 15
TABLE 3 – MISCELLANEOUS INTERFACE SIGNALS (12) ....................................................... 24
TABLE 4 – PRODUCTION TEST INTERFACE SIGNALS (30) ................................................... 25
TABLE 5 – DON’T CARE SIGNALS (58) ..................................................................................... 27
TABLE 6 – NO-CONNECT SIGNALS (9)..................................................................................... 29
TABLE 7 – POWER AND GROUND SIGNALS (60).................................................................... 30
TABLE 8 – RECEIVE PACKET DESCRIPTOR FIELDS .............................................................. 39
TABLE 9 – RPDRR QUEUE ELEMENT....................................................................................... 45
TABLE 10 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS...................... 47
TABLE 11 – TRANSMIT DESCRIPTOR FIELDS......................................................................... 55
TABLE 12 – TRANSMIT DESCRIPTOR REFERENCE............................................................... 61
TABLE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS ................... 62
TABLE 14 – NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY MAP ............... 72
TABLE 15 – PCI CONFIGURATION REGISTER MEMORY MAP............................................... 75
TABLE 16 – BIG ENDIAN FORMAT ............................................................................................ 99
TABLE 17 – LITTLE ENDIAN FORMAT....................................................................................... 99
TABLE 18 – CRC[1:0] SETTINGS ............................................................................................. 120
TABLE 19 – RPQ_RDYN[2:0] SETTINGS ................................................................................. 132
TABLE 20 – RPQ_LFN[1:0] SETTINGS .................................................................................... 133
TABLE 21 – RPQ_SFN[1:0] SETTINGS .................................................................................... 133
TABLE 22 – TDQ_RDYN[2:0] SETTINGS ................................................................................. 155
TABLE 23 – TDQ_FRN[1:0] SETTINGS .................................................................................... 155
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TABLE 24 – CRC[1:0] SETTINGS ............................................................................................. 175
TABLE 25 – FLAG[2:0] SETTINGS............................................................................................ 180
TABLE 26 – LEVEL[3:0]/TRANS SETTINGS............................................................................. 181
TABLE 27 – TEST MODE REGISTER MEMORY MAP............................................................. 227
TABLE 28 – INSTRUCTION REGISTER ................................................................................... 228
TABLE 29 – BOUNDARY SCAN CHAIN.................................................................................... 228
TABLE 30 – FREEDM–EQUAD CONNECTIONS ..................................................................... 241
TABLE 31 – FREEDM–TOCTL CONNECTIONS ...................................................................... 241
TABLE 32 – FREEDM-8 ABSOLUTE MAXIMUM RATINGS ..................................................... 260
TABLE 33 – FREEDM-8 D.C. CHARACTERISTICS ................................................................. 261
TABLE 34 – FREEDM-8 LINK INPUT (FIGURE 38, FIGURE 39) ............................................. 263
TABLE 35 – FREEDM-8 LINK OUTPUT (FIGURE 40, FIGURE 41) ......................................... 264
TABLE 36 – PCI INTERFACE (FIGURE 42).............................................................................. 266
TABLE 37 – JTAG PORT INTERFACE (FIGURE 43)................................................................ 267
TABLE 38 – FREEDM-8 ORDERING INFORMATION .............................................................. 269
TABLE 39 – FREEDM-8 THERMAL INFORMATION................................................................. 269
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1
1 FEATURES
· Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.
· Supports up to 128 bi-directional HDLC channels assigned to a maximum of 8 channelised T1
or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1
to 24 (for T1) and from 1 to 31 (for E1).
· Supports up to 8 bi-directional HDLC channels each assigned to an unchannelised arbitrary
rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction.
Channels assigned to links 0 to 2 can have a clock rate of up 52 MHz when SYSCLK is at 33
MHz. Channels assigned to links 3 to 7 can have a clock rate of up to 10 MHz.
· Supports up to two bi-directional HDLC Channels each assigned to an unchannelised arbitrary
rate link of up to 52 MHz when SYSCLK is at 33 MHz.
· Supports a mix of up to 8 channelised and unchannelised links; subject to the constraint of a
maximum of 128 channels and a maximum aggregate link clock rate of 64 MHz in each
direction.
· For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and
frame check sequence validation. The receiver supports the validation of both CRC-CCITT
and CRC-32 frame check sequences. The receiver also checks for packet abort sequences,
octet aligned packet length and for minimum and maximum packet length.
· Alternatively, for each channel, the receiver supports a transparent mode where each octet is
transferred transparently to host memory. For channelised links, the octets are aligned with
the receive time-slots.
· For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear
channel format.
· For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and,
optionally, frame check sequence generation. The transmitter supports the generation of
both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets
under the direction of the host or automatically when the channel underflows.
· Supports two levels of non-preemptive packet priority on each transmit channel. Low priority
packets will not begin transmission until all high priority packets are transmitted.
· Alternatively, for each channel, the transmitter supports a transparent mode where each octet
is inserted transparently from host memory. For channelised links, the octets are aligned with
the transmit time-slots.
· Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer
of packet data, with an on-chip DMA controller with scatter/gather capabilities.
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· Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This
memory can be configured to support a variety of different channel configurations from a
single channel with 8 kbytes of buffering to 128 channels, each with a minimum of 48 bytes of
buffering.
· Supports PCI burst sizes of up to 128 bytes for transfers of packet data.
· Pin compatible with PM7364 (FREEDM-32) device.
· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
· Supports 3.3 and 5 Volt PCI signaling environments.
· Low power CMOS technology.
· 256 pin enhanced ball grid array (SBGA) or 272 pin plastic ball grid array (PBGA) packages
(27 mm X 27 mm).
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2 APPLICATIONS
· IETF PPP interfaces for routers
· Frame Relay interfaces for ATM or Frame Relay switches and multiplexors
· FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors.
· D-channel processing in ISDN terminals and switches.
· Internet/Intranet access equipment.
· Packet-based DSLAM equipment.
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3 REFERENCES
1. International Organization for Standardization, ISO Standard 3309-1993, "Information
Technology - Telecommunications and information exchange between systems - High-level
data link control (HDLC) procedures - Frame structure", December 1993.
2. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994.
3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1.
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4 APPLICATION
EXAMPLES
DS3/E3/J2
HSSI
Micro-
processor
PCI Bus
Packet
Memory
Processor Module
FREEDM
PM4314
QDSX
E1 Access Module
PM6344
EQUAD
PM4314
QDSX
PM4388
TOCTL
T1 Access Modu le
M13 Access Module
PM8313
D3MX
PM4388
TOCTL
E1
T1
DS3
ACCESS SIDE
HDLC BASED UPLINK SIDE
HSSI
Module
HDLC Based
Uplink Module
DS3/E3
Framer
LIU
PM7366
FREEDM-8
OC-3
xDSL Access Module
xDSL
XDSL
PHY
T3/E3
OC-3
Micro-
processor
PM7366
FREEDM-8
PCI Bus
Packet
Memory
SAR
PM7322
RCMP
Processor Module
OC-12
ACCESS SIDE
ATM CELL BASED UPLINK SIDE
STS-3c ATM UNI
PM5346
S/UNI-LITE
PM5348
S/UNI-DUAL
PM5355
S/UNI-622
STS-12c ATM UNI/NNI
PM5347
S/UNI-PLUS
STS-3c ATM NNI
PM7345
S/UNI-PDH
DS-3/E3 ATM
background image
RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
6
5 BLOCK
DIAGRAM
.
PCI
Contr
o
ller
(GP
IC)
TDO
TDI
TCK
TMS
TRSTB
TBCLK
TBD
AD[3
1:0]
C/B
EB[
3:0]
PAR
F
R
AM
EB
TRDYB IRDY
B
ST
O
P
B
D
E