SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
Operates With Single 5-V Power Supply
D
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
D
Improved Performance Replacement for
MAX241
D
Operates at Data Rates up to 100 kbit/s
Over a 3-m Cable
D
Low-Power Shutdown Mode . . .
≤
1
µ
A Typ
D
LinBiCMOS
™
Process Technology
D
Four Drivers and Five Receivers
D
±
30-V Input Levels
D
3-State TTL/CMOS Receiver Outputs
D
±
9-V Output Swing With a 5-V Supply
D
Applications
– TIA/EIA-232-F Interface
– Battery-Powered Systems
– Terminals
– Modems
– Computers
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages
description
The SN75LBC241
†
is a low-power LinBiCMOS
™
line-interface device containing four independent drivers and
five receivers. It is designed as a plug-in replacement for the Maxim MAX241. The SN75LBC241 provides a
capacitive-charge-pump voltage generator to produce RS-232 voltage levels from a 5-V supply. The
charge-pump oscillator frequency is 20 kHz. Each receiver converts RS-232 inputs to 5-V TTL/CMOS levels.
The receivers have a typical threshold of 1.2 V and a typical hysteresis of 0.5 V and can accept
±
30-V inputs.
Each driver converts TTL/CMOS input levels into RS-232 levels.
The SN75LBC241 includes a receiver, a 3-state control line, and a low-power shutdown control line. When the
EN line is high, receiver outputs are placed in the high-impedance state. When EN is low, normal operation is
enabled.
The shutdown mode reduces power dissipation to less than 5
µ
W typically. In this mode, receiver outputs have
high impedance, driver outputs are turned off, and the charge-pump circuit is turned off. When SHUTDOWN
is high, the shutdown mode is enabled. When SHUTDOWN is low, normal operation is enabled.
This device has been designed to conform to TIA/EIA-232-F and ITU Recommendation V.28.
The SN75LBC241 has been designed using LinBiCMOS technology and cells contained in the Texas
Instruments LinASIC
™
library. Use of LinBiCMOS circuitry increases latch-up immunity in this device over an
all-CMOS design.
The SN75LBC241 is characterized for operation from 0
°
C to 70
°
C.
Copyright
©
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOUT3
TOUT1
TOUT2
RIN2
ROUT2
TIN2
TIN1
ROUT1
RIN1
GND
V
CC
C1+
V
DD
C1–
TOUT4
RIN3
ROUT3
SHUTDOWN
EN
RIN4
ROUT4
TIN4
TIN3
ROUT5
RIN5
V
SS
C2–
C2+
DB OR DW PACKAGE
(TOP VIEW)
† Patent pending
LinBiCMOS and LinASIC are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
logic symbol
†
ROUT1
8
9
RIN1
4
RIN2
27
RIN3
23
RIN4
18
RIN5
DRV/RCV
CX
12
C1+
CX
14
C1–
CX
15
C2+
CX
16
C2–
13
TIN1
7
TIN2
6
TIN3
20
TIN4
21
EN1
24
EN2
25
SHUTDOWN
17
2
2
TOUT1
2
3
TOUT2
2
1
TOUT3
2
28
TOUT4
1,2
1,2
1,2
1,2
1,2
ROUT2
5
ROUT3
26
ROUT4
22
ROUT5
19
EN
VDD
VSS
VDD
VSS
VCC
11
GND
10
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
8
7
9
2
5
6
4
3
26
20
27
1
22
21
23
28
19
18
24
EN
RIN1
TOUT1
RIN2
TOUT2
RIN3
TOUT3
RIN4
TOUT4
RIN5
ROUT1
TIN1
ROUT2
TIN2
ROUT3
TIN3
ROUT4
TIN4
ROUT5
SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
3
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Input supply voltage range, V
CC
(see Note 1)
–0.3 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive output supply voltage range, V
DD
V
CC
– 0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative output supply voltage range, V
SS
0.3 V to –15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Driver
–0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver
±
30 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
: TOUT V
SS
– 0.3 V to V
DD
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROUT
–0.3 V to V
CC
+ 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-circuit duration: TOUT
Unlimited
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation
See Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA
≤
25
°
C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25
°
C
TA = 70
°
C
POWER RATING
DB
1348 mW
10.8 mW/
°
C
862 mW
DW
1603 mW
12.8 mW/
°
C
1026 mW
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.5
5
5.5
V
High level input voltage VIH
TIN
2
V
High-level input voltage, VIH
EN, SHUTDOWN
2.4
V
Low-level input voltage, VIL
TIN, EN, SHUTDOWN
0.8
V
External charge-pump capacitor
C1–C4 (see Figure 1)
1
µ
F
External charge pump capacitor voltage rating
C1, C3 (see Figure 1)
6.3
V
External charge-pump capacitor voltage rating
C2, C4 (see Figure 1)
16
V
Receiver input voltage, VI
±
30
V
Operating free-air temperature, TA
0
70
°
C
SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VOH
High level output voltage
TOUT
RL = 3 k
Ω
to GND, See Note 2
5
9
V
VOH
High-level output voltage
ROUT
IOH = –1 mA
3.5
V
VOL
Low level output voltage
TOUT
RL = 3 k
Ω
to GND, See Note 3
–9‡
–5
V
VOL
Low-level output voltage
ROUT
IOL = 3.2 mA
0.4
V
VIT+
Receiver positive-going input threshold voltage
RIN
VCC = 5 V,
TA = 25
°
C
1.7
2.4
V
VIT–
Receiver negative-going input threshold voltage
RIN
VCC = 5 V,
TA = 25
°
C
0.8
1.2
V
Vhys
Input hysteresis voltage (VIT+ – VIT–)
RIN
VCC = 5 V
0.5
1
V
ri
Receiver input resistance
RIN
VCC = 5 V,
TA = 25
°
C
3
5
7
k
Ω
ro
Output resistance
TOUT
VDD = VSS = VCC = 0,
VO =
±
2 V
300
Ω
IOS
Short circuit output current§
TOUT
VCC = 5.5 V,
VO = 0
±
10
mA
IIS
Short circuit input current
TIN
VI = 0
200
µ
A
ICC
Supply current
VCC = 5.5 V, TA = 25
°
C,
All outputs open
4
8
mA
ICC
Supply current
All outputs open, TA = 25
°
C,
SHUTDOWN high
1
10
mA
† All typical values are at VCC = 5 V, TA = 25
°
C.
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage
levels only.
§ Not more than one output should be shorted at one time.
NOTES:
2. Total IOH drawn from TOUT1, TOUT2, TOUT3, TOUT4, and VDD terminals should not exceed 12 mA.
3. Total IOL drawn from TOUT1, TOUT2, TOUT3, TOUT4, and VSS terminals should not exceed –12 mA.
switching characteristics, V
CC
= 5 V, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH(R)
Receiver propagation-delay time,
low- to high-level output
See Figure 2
500
ns
tPHL(R)
Receiver propagation-delay time,
high- to low-level output
See Figure 2
500
ns
tPZH
Receiver output-enable time to high level
See Figure 5
100
ns
tPZL
Receiver output-enable time to low level
See Figure 5
100
ns
tPHZ
Receiver output-disable time from high level
See Figure 5
50
ns
tPLZ
Receiver output-disable time from low level
See Figure 5
50
ns
SR
Driver slew rate
RL = 3 k
Ω
to 7 k
Ω
, CL = 2500 pF,
See Figure 4
30
V/
µ
s
SR(tr)
Driver transition region slew rate
RL = 3 k
Ω
to 7 k
Ω
, CL = 2500 pF,
See Figure 4
4
6
V/
µ
s
SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
5
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
APPLICATION INFORMATION
C1
1
µ
F
6.3 V
C2
1
µ
F
16 V
C3
1
µ
F
6.3 V
C4
1
µ
F
16 V
400 k
Ω
5 k
Ω
EN
VCC
5-V to 10-V
Voltage Doubler
10-V to –10-V
Voltage Inverter
5-V Input
RS-232
Outputs
RS-232
Inputs
TTL/CMOS
Outputs
TTL/CMOS
Inputs
VDD
VSS
+
+
+
+
11
VCC
VCC
VCC
VCC
400 k
Ω
400 k
Ω
400 k
Ω
C1+
C1–
C2+
C2–
12
14
15
16
13
17
T1
T2
T3
T4
2
3
1
28
9
4
27
23
18
25
5 k
Ω
5 k
Ω
5 k
Ω
5 k
Ω
R1
R2
R3
R4
R5
GND
10
7
6
20
21
8
5
26
22
19
24
TOUT1
TOUT2
TOUT3
TOUT4
RIN1
RIN2
RIN3
RIN4
RIN5
SHUTDOWN
TIN1
TIN2
TIN3
TIN4
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
Figure 1. Typical Operating Circuit
SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
6
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
VOLTAGE WAVEFORMS
CL = 50 pF
(see Note B)
RL = 1.3 k
Ω
0 V
3 V
Output
Input
VOL
VOH
tPHL(R)
Generator
(see Note A)
tPLH(R)
500 ns
≤
10 ns
≤
10 ns
VCC
NOTES: A. The pulse generator has the following characteristics: ZO = 50
Ω
, duty cycle
≤
50%.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
RIN
ROUT
See Note C
90%
90%
50%
50%
10%
10%
1.5 V
1.5 V
Figure 2. Receiver Test Circuit and Waveforms for t
PHL
and t
PLH
Measurement
CL = 10 pF
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORMS
Output
VOL
VOH
tPHL
tTLH
Generator
(see Note A)
RL
RS-232
Output
tPLH
tTHL
5
µ
s
0 V
NOTES: A. The pulse generator has the following characteristics: ZO = 50
Ω
, duty cycle
≤
50%.
B. CL includes probe and jig capacitance.
TIN
TOUT
3 V
Input
≤
10 ns
≤
10 ns
90%
90%
50%
50%
10%
10%
90%
90%
10%
10%
Figure 3. Driver Test Circuit and Waveforms for t
PHL
and t
PLH
Measurement (5-
µ
s Input)
NOTES: A. The pulse generator has the following characteristics: ZO = 50
Ω
, duty cycle
≤
50%.
B. CL includes probe and jig capacitance.
SR
+
6 V
t
THL
or t
TLH
CL
(see Note B)
TEST CIRCUIT
Generator
(see Note A)
RL
RS-232
Output
VOLTAGE WAVEFORMS
0 V
3 V
Output
Input
VOL
VOH
tTHL
tTLH
20
µ
s
≤
10 ns
≤
10 ns
90%
90%
1.5 V
1.5 V
10%
10%
–3 V
–3 V
3 V
3 V
Figure 4. Test Circuit and Waveforms for t
THL
and t
TLH
Measurement (20-
µ
s Input)
SN75LBC241
LOW-POWER LinBiCMOS
™
MULTIPLE DRIVERS AND RECEIVERS
SLLS137E – MAY 1992 – REVISED JANUARY 1999
7
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
EN
VOH – 0.1 V
VOL + 0.1 V
tPHZ
tPZH
tPZL
tPLZ
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: ZO = 50
Ω
, duty cycle
≤
50%.
B. CL includes probe and jig capacitance.
CL = 150 pF
(see Note B)
RL = 1 k
Ω
Generator
(see Note A)
RIN
ROUT
2.5 V
EN
3 V
0 V
3 V
0 V
3.5 V
0.8 V
2.5 V
Figure 5. Receiver Output Enable and Disable Timing
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright
©
1999, Texas Instruments Incorporated