KC74125C 1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
1
INTRODUCTION
The KC74125C is an interline transfer CCD area image
sensor developed for NTSC 1/4 inch optical format video
cameras, surveillance cameras, object detectors and image
pattern recognizers. High sensitivity is achieved through the
adoption of Ye, Cy, Mg and G complementary color mosaic
filters, on-chip micro lenses and HAD (Hole Accumulated
Diode) photosensors. This chip features a field integration
read out system and an electronic shutter with variable charge
storage time.
FEATURES
•
High Sensitivity
•
Optical Size 1/4 inch Format
•
No adjust Substrate Bias
•
Ye, Cy, Mg, G On-chip Complementary Color Mosaic Filter
•
Variable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10,000sec)
•
Low Dark Current
•
Horizontal Register 3.3 to 5.0V Drive
•
14pin Ceramic DIP Package
•
Field Integration Read Out System
•
No DC Bias on Reset Gate
STRUCTURE
•
Number of Total Pixels:
537(H)
×
505(V)
•
Number of Effective Pixels:
510(H)
×
492(V)
•
Chip Size:
4.83mm(H)
×
4.04mm(V)
•
Unit Pixel Size:
7.15
µ
m(H)
×
5.55
µ
m(V)
•
Optical Blacks & Dummies:
Refer to Figure Below
Vertical 1 Line (Even Field Only)
14Pin Cer DIP
ORDERING INFORMATION
Device
Package
Operating
KC74125C
14Pin Cer DIP
-10
°
C ~ +60
°
C
16 2
510
25
1
4
9
2
1
2
V
-C
C
D
OUTPUT
Dummy Pixels
Optical Black Pixels
Effective Pixels
Effective
Imaging
Area
H-CCD
1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC74125C
2
BLOCK DIAGRAM
PIN DESCRIPTION
Figure 1. Block Diagram
Table 1. Pin Description
Pin
Symbol
Description
Pin
Symbol
Description
1
Φ
V4
Vertical register transfer clock
8
V
DD
Signal output
2
Φ
V3
Vertical register transfer clock
9
GND
GND
3
Φ
V2
Vertical register transfer clock
10
Φ
SUB
Substrate clock
4
Φ
V1
Vertical register transfer clock
11
V
L
Protection transistor bias
5
NC
No connection
12
Φ
RG
Reset gate clock
6
GND
Ground
13
Φ
H1
Horizontal register transfer clock
7
V
OUT
Signal output
14
Φ
H2
Horizontal register transfer clock
7
V
OUT
6
5
4
3
2
1
8
9
10
11
12
13
14
GND
NC
Φ
V1
Φ
V2
Φ
V3
Φ
V4
V
DD
V
L
GND
Φ
H1
Φ
H2
Φ
RG
Φ
SUB
V
e
rti
c
a
l
S
h
ift
R
e
g
is
te
r C
C
D
V
e
rti
c
a
l
S
h
ift
R
e
g
is
te
r C
C
D
V
e
rti
c
a
l
S
h
ift
R
e
g
is
te
r C
C
D
V
e
rti
c
a
l
S
h
ift
R
e
g
is
te
r C
C
D
Horizontal Shift Register CCD
Cy
Ye
Mg
Mg
Mg
Mg
Mg
Ye
Ye
Ye
Ye
Ye
Ye
Ye
G
G
G
G
Cy
Cy
Cy
Cy
Cy
G
Mg
G
Cy
Cy
(Top View)
KC74125C 1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
3
ABSOLUTE MAXIMUM RATINGS
(NOTE)
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
Table 2. Absolute Maximum Ratings
Characteristics
Symbols
Min.
Max.
Unit
Substrate voltage
SUB - GND
-0.3
40
V
V
DD
, V
OUT
- SUB
-40
10
V
Vertical clock input voltage
Φ
V1
,
Φ
V3
, - GND
-0.3
30
V
Φ
V2
,
Φ
V4
- GND
-0.3
17
V
Φ
V1
,
Φ
V3
, - V
L
-0.3
30
V
Φ
V2
,
Φ
V4
- V
L
-0.3
17
V
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
- SUB
-40
10
V
Horizontal clock input voltage
Φ
H1
,
Φ
H2
- V
L
-0.3
7
V
Φ
H1
,
Φ
H2
- SUB
-30
7
V
Voltage difference between vertical and
horizontal clock input pins
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
15
V
Φ
H1
,
Φ
H2
16
V
Φ
H1
,
Φ
H2
-
Φ
V4
-17
16
V
Output clock input voltage
Φ
RG
- GND
-0.3
16
V
Φ
RG
- SUB
-40
16
V
Protection circuit bias voltage
V
L
- SUB
-40
10
V
Operating temperature
T
OP
-10
60
°
C
Storage temperature
T
STG
-30
80
°
C
1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC74125C
4
DC CHARACTERISTICS
CLOCK VOLTAGE CONDITIONS
Table 3. DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Output stage drain bias
V
DD
14.55
15.0
15.45
V
Protection circuit bias voltage
V
L
The lowest vertical clock level
Output stage drain current
I
DD
5
mA
Table 4. Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Read-out clock voltage
V
VH1
, V
VH3
14.55
15.0
15.45
V
High level
Vertical transfer clock voltage
V
VM1
~ V
VM4
-0.2
0.0
0.2
V
Middle
V
VL1
~ V
VL4
-8.0
-7.5
-7.0
V
Low
Horizontal transfer clock voltage
V
HH1
, V
HH2
3.0
5.0
5.25
V
High
V
HL1
, V
HL2
-0.05
0.0
0.05
V
Low
Charge reset clock voltage
V
RGH
4.75
5.0
5.25
V
High
V
RGL
-0.2
0.0
0.2
V
Low
Substrate clock voltage
V
Φ
SUB
21.5
22.5
23.5
V
Shutter
KC74125C 1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
5
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
Vertical Transfer Clock Waveform
0V
100%
90%
10%
0%
V
VH 1,
V
VH3
tr
twh
tf
V
V H 1
V
VH
V
V H H
V
VL L
V
VL
V
VL 1
V
VL H
V
V H L
V
V H L
V
V H H
¥Õ V 1
V
VH
V
VHL
V
VH H
V
V HH
V
VHL
V
VH 4
V
VL
V
VL H
V
VL L
V
V L 4
¥Õ V 4
V
VH H
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VL
V
VL L
V
VL H
V
VL 2
¥Õ V 2
V
VL 3
V
VHH
V
VL
V
V HL
V
VH L
V
VH3
V
VH H
V
VH
V
VL H
V
VL L
¥Õ V 3
V
V H
= ( V
V H 1
+ V
V H 2
)/ 2
V
V L
= (V
V L 3
+ V
V L 4
)/ 2
V
¥Õ
V
= V
V H n
- V
V L n
(n =1~4)
V
V H H
= V
V H
+ 0 . 3 V
V
V H L
= V
V H
- 0 . 3 V
V
V L H
= V
V L
+ 0 . 3 V
V
V L L
= V
V L
- 0 . 3 V
1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC74125C
6
Horizontal Transfer Clock Waveform Diagram
Reset Gate Clock Waveform Diagram
V
RGLH
is the maximum value and V
RGLL
the minimum value of the coupling waveform in the period from Point A in
the diagram about to R
G
rise
V
RGL
= (V
RGLH
+ V
RGLL
)/2, V
FRG
= V
RGH
- V
RGL
Substrate Clock Waveform
90%
10%
tr
twh
tf
twl
V
¥Õ
H
V
H L
V
R GL
+ 0.5V
twl
Point
A
twh
tf
tr
V
R GH
V
R GL
RG waveform
V
R GLH
V
R GLL
¥Õ
H1 waveform
10%
V
¥Õ
R G
100%
90%
10%
0%
twh
tr
tf
V
¥Õ
SU B
V
S U B
KC74125C 1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
7
CLOCK EQUIVALENT CIRCUIT CONSTANT
Table 5. Clock Equivalent Circuit Constant
Item
Symbol
twh
twl
tr
tf
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Read-out clock
Φ
VH
2.5
0.5
0.5
µ
s
Vertical clock
Φ
V1
,
Φ
V2
Φ
V3
,
Φ
V4
15
250
ns
Horizontal clock
Φ
H1
41
46
41
46
6.5
9.5
6.5
9.5
ns
Φ
H2
41
46
41
46
6.5
9.5
6.5
9.5
ns
Reset clock
Φ
RG
11
15
75
79
6.5
4.5
ns
Substrate clock
Φ
SUB
1.5
2.0
0.5
0.5
µ
s
1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC74125C
8
EQUIVALENT CIRCUIT PARAMETERS
Table 6. Equivalent Circuit Parameters
Item
Symbol
Typ.
Unit
Remark
Capacitance between vertical transfer clock and GND
C
Φ
V1
, C
Φ
V3
680
pF
C
Φ
V2
, C
Φ
V4
820
pF
Capacitance between vertical transfer clocks
C
Φ
V12
, C
Φ
V34
180
pF
C
Φ
V23
, C
Φ
V41
180
pF
C
Φ
V13
60
pF
C
Φ
V24
60
pF
Capacitance between horizontal transfer clock and GND
C
Φ
H1
, C
Φ
H2
30
pF
Capacitance between horizontal transfer clocks
C
Φ
H12
30
pF
Capacitance between substrate clock and GND
C
Φ
SUB
180
pF
Vertical transfer clock serial resistor
R
Φ
V1
~ R
Φ
V4
40
Ω
Vertical transfer clock ground resistor
R
Φ
VGND
15
Ω
Horizontal transfer clock serial resistor
R
Φ
H1
, R
Φ
H2
10
Ω
Reset gate clock serial resistor
R
Φ
RG
100
Ω
R
¥Õ
H1
R
¥Õ
H2
C
¥Õ
H12
C
¥Õ
H1
C
¥Õ
H2
C
¥Õ
V23
C
¥Õ
V41
C
¥Õ
V12
C
¥Õ
V34
C
¥Õ
V4
C
¥Õ
V1
C
¥Õ
V2
C
¥Õ
V3
R
¥Õ
V4
R
¥Õ
V2
R
¥Õ
V3
R
¥Õ
VGND
¥Õ
V3
¥Õ
V4
¥Õ
V2
¥Õ
H1
¥Õ
H2
¥Õ
V1
R
¥Õ
V1
C
¥Õ
V24
C
¥Õ
V13
KC74125C 1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
9
OPERATING CHARACTERISTICS
Device Temperature = 25
°
C
NOTE: Test Temperature = 60
°
C
TESTING SYSTEM
Table 7. Operating Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Sensitivity
S
45
50
mV/lux
1
Saturation signal
Y
SAT
800
mV
2
Smear
SM
0.007
0.01
%
3
Blooming margin
BM
1,000
times
4
Uniformity
U
20
%
5
Dark signal
(NOTE)
D
2
mV
6
Dark shading
(NOTE)
∆
D
2
mV
7
Image lag
Y
LAG
0.5
%
8
Flicker Y
F
Y
2
%
9
Flicker red, blue
F
CR
, F
CB
5
%
10
Color uniformity
D
SR
, D
SB
10
%
11
Line stripe W, R, G, B
L
CW
, L
CR
, L
CG
, L
CB
3
%
12
Figure 2. Testing System
CCD
AMP
LPF1
S/H
S/H
LPF2
A
Y
C
(3dB down at 4MHz)
Chroma
Signal
Output
Illuminance
Signal
Output
CCD Signal
Output
C. D. S
(3dB down at 1MHz)
1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC74125C
10
TEST CONDITION
1. Use a light source with color temperature of 3,200K hallogen lamp and CM-500S for IR cut filter.
The light source is adjusted in accordance with the average value of Y signals indicated in each item.
COLOR FILTER ARRAY
The color filter array of this image sensor is shown in the right figure. this complementary mosaic CFA is used with
the operation of field integration mode, where all of the photosensors are read out during each video field. The
signals from two vertically-adjacent photosensor lines, such as line couple A1 or A2 for field A are summed when
the signal charges are transferred into the vertical transfer CCD column. The read out line pairing is shifted down
by one line for field B.
The sensor output signals through the horizontal register (H-CCD) at line A1 are [G+Cy], [MG+Ye], [G+CY],
[Mg+Ye]. These signals are processed in order to compose Y and C signals. By adding the two adjacent signals at
line A1, Y signal is formed as follows
C signal is composed by substracting the two adjacent signals at line A1
Figure 3. Color Filter Array
Y
1
2
--- G
Cy
+
(
)
Mg
Ye
+
(
)
+
[
]
1
2
--- 2B
3G
2R
+
+
(
)
=
=
H - CCD
A1
A2
B
Cy
Ye
G
Mg
Cy
Cy
Cy
Ye
Ye
Ye
G
G
G
Mg
Mg
Mg
KC74125C 1/4 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
11
Next, the signals through H-CCD at line A2 are [Mg+Cy], [G+Ye], [Mg+Cy], [G+Ye]. Simmilary, Y and C signals are
composed at line A2 as follows
Accordingly, Y signal is balanced in relation to scanning lines, and C signal takes the form of R-Y and -(B-Y) on
alternate lines.
It i