Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9179-12
Block Diagram
PentiumPro is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
3 DIMM Buffer
9179-12 Rev C 7/16/99
Pin Configuration
The ICS9179-12 is a buffer intended for reduced pin count
2 - chip Intel BX chipset designs
An I
2
C interface is included, enabling individual outputs to be
turned on or off. With 13 outputs, up to 3 DIMMs are supported.
Thirteen high speed, low noise buffers, supports up to
three SDRAM DIMMs.
Buffer outputs skew matched to within 250ps.
I
2
C Serial Configuration interface to allow individual
OUTPUTs to be stopped low.
Multiple VDD, VSS pins for noise reduction
3.3V±5% supply voltage
28-pin SOIC and SSOP package
Propagation delay between 1 to 5.5ns
Operation to 133MHz at 3.3V±5%
28-Pin SOIC and SSOP
* Internal pull-up resistor of 100K
Ohms to 3.3V on indicated inputs
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Power Groups
VDD (0:4), GND (0:4) = Power supply for OUTPUT buffer
VDDI, GNDI = Power supply for I
2
C circuitry
2
ICS9179-12
Pin Descriptions
Notes:
1.
At power up all thirteen OUTPUTs are enabled and active.
2.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3.
The SDATA and SCLK inputs both have internal pull-up resistors with values above 100K Ohms.
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C
3
ICS9179-12
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for OUTPUT (0:12).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from Ground
to this level. For the actual guaranteed high and low voltage
levels for the Clocks, please consult the DC parameter table
in this data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
OUTPUT (0:12)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing
of the OUTPUTs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I
2
C
The SDATA and SCLOCK Inputs are used to program the
device. The clock generator is a slave-receiver device in the
I
2
C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I
2
C
specification in Philips I
2
C Peripherals Data Handbook
(1996) should be followed.
BUF_IN
Input for Fanout buffers (OUTPUT 0:12).
VDDI
This is the power supply to I
2
C circuitry.
Technical Pin Function Descriptions
4
ICS9179-12
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
5
ICS9179-12
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Byte 1: OUTPUT Clock Register
Functionality
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ICS9279-12 Power Consumption
The values below are estimates of target specifications.
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1
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (Default=0)
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Byte 2: OUTPUT Clock Register
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