SPT561 D/S

Typical Distortion Performance

Output

20MHz

50MHz

100MHz

Power

2nd

3rd

2nd

3rd

2nd

3rd

10dBm

-59

-62

-52

-60

-35

-49

18dBm

-52

-48

-45

-46

-30

-36

24dBm

-50

-41

-36

-32

-40

-30

Frequency Response vs. Output Power

Gain (dB)

Frequency (MHz)

120

160

200

= 10dBm

= 2V

= 24dBm

= 10V

= 27.5dBm

= 15V

= 18dBm

= 5V

Features

150MHz bandwidth at +24dBm output

Low distortion (2nd/3rd:

-59/-62dBc @ 20MHz and 10dBm)

Output short circuit protection

User-definable output impedance, gain,

and compensation

Internal current limiting

Direct replacement for CLC561

Applications

Output amplification

Arbitrary waveform generation

ATE systems

Cable/line driving

Function generators

SAW drivers

Flash A/D driving and testing

4755 Forge Road, Colorado Springs, Colorado 80907, USA

Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com

WIDEBAND, LOW DISTORTION DRIVER AMPLIFIER

General Description

The SPT561 is a wideband DC coupled, amplifier that combines high

output drive and low distortion. At an output of +24dBm (10V

into

Ω

), the -3dB bandwidth is 150MHz. As illustrated in the table

below, distortion performance remains excellent even when amplify-

ing high-frequency signals to high output power levels.

With the output current internally limited to 250mA, the SPT561 is

fully protected against shorts to ground and can, with the addition of a

series limiting resistor at the output, withstand shorts to the

15V

supplies.

The SPT561 has been designed for maximum flexibility in a wide

variety of demanding applications. The two resistors comprising the

feedback network set both the gain and the output impedance,

without requiring the series backmatch resistor needed by most op

amps. This allows driving into a matched load without dropping half

the voltage swing through a series matching resistor. External

compensation allows user adjustment of the frequency response.

The SPT561 is specified for both maximally flat frequency response

and 0% pulse overshoot compensations.

The combination of wide bandwidth, high output power, and low

distortion, coupled with gain, output impedance and frequency

response flexibility, makes the SPT561 ideal for waveform generator

applications. Excellent stability driving capacitive loads yields supe-

rior performance driving ADC’s, long transmission lines, and SAW

devices.

The SPT561 is constructed using thin film resistor/bipolar transistor

technology, and is available in the following versions:

SPT561AIJ

-25

C to +85

24-pin Ceramic DIP

SPT561AMJ

-55

C to +125

24-pin Ceramic DIP, features

burn-in and hermetic testing

Compensation

-V

All undesignated

pins are internally

unconnected. May

be grounded if

desired.

V+

V-

Block Diagram

10/9/98

SPT561

PARAMETERS

CONDITIONS

TYP

MIN & MAX RATINGS

UNITS

SYM

Case Temperature

SPT561AIJ

+25

-25

+25

+85

Case Temperature

SPT561AMJ

+25

-55

+25

+125

FREQUENCY DOMAIN RESPONSE (Max. Flat Compensation)

-3dB bandwidth

maximally flat compensation

<2V

(+10dBm)

215

>175

>185

>175

MHz

SSBW

0% overshoot compensation

<2V

(+10dBm)

210

>170

>180

>170

MHz

large signal bandwidth

Vo <10V

(+24dBm)

150

>145

>135

>120

MHz

FPBW

(see Frequency Response vs. Output Power plot)

gain flatness

<2V

(+10dBm)

peaking

0.1 -50MHz

<0.50

<0.40

<0.50

GFPL

peaking

>50MHz

<1.75

<0.75

<1.00

GFPH

rolloff

at 100MHz

0.1

<1.00

<0.75

<1.00

GFR

group delay

to 100MHz

2.9

–

linear phase deviation

to 100MHz

0.6

<1.7

<1.2

<1.7

LPD

return loss (

see discussion of R

)

to 100MHz

-15

<-11

DISTORTION (Max. Flat Compensation)

2nd harmonic distortion

24dBm (10V

20MHz

-50

<-38

<-40

<-38

dBc

HD2HL

50MHz

-36

<-29

<-22

dBc

HD2HM

100MHz

-40

<-25

dBc

HD2HH

18dBm (5V

20MHz

-52

<-42

<-44

<-42

dBc

HD2ML

50MHz

-45

<-30

<-35

<-30

dBc

HD2MM

100MHz

-30

<-22

<-25

dBc

HD2MH

10dBm (2V

20MHz

-59

<-48

<-52

<-48

dBc

HD2LL

50MHz

-52

<-36

<-40

dBc

HD2LM

100MHz

-35

<-27

<-28

dBc

HD2LH

3rd harmonic distortion

24dBm (10V

20MHz

-41

<-34

<-30

dBc

HD3HL

50MHz

-32

<-26

<-21

dBc

HD3HM

100MHz

-30

<-24

dBc

HD3HH

18dBm (5V

20MHz

-48

<-40

<-44

dBc

HD3ML

50MHz

-46

<-37

<-35

dBc

HD3MM

100MHz

-36

<-30

dBc

HD3MH

10dBm (2V

20MHz

-62

<-54

<-57

dBc

HD3LL

50MHz

-60

<-49

<-52

<-49

dBc

HD3LM

100MHz

-49

<-45

dBc

HD3LH

2-tone 3rd order

intermod intercept

20MHz

>36

dBm

IM3L

50MHz

>32

dBm

IM3M

100MHZ

>27

>23

dBm

IM3H

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are

determined from tested parameters.

SPT561 Electrical Characteristics

= +10V, V

15V, R

= 50

Ω

, R

= 410

Ω

, R

= 40

Ω

, R

= 50

Ω

; unless specified)

NOTES TO THE ELECTRICAL SPECIFICATIONS

The electrical characteristics shown here apply to the specific test conditions shown above (see also Figure 1 in

description of the operation). The SPT561 provides an equivalent, non-zero, output impedance determined by the

external resistors. The signal gain to the load is therefore load dependent. The signal gain shown above (A

= +10)

is the no load gain. The actual gain to the matching 50

Ω

load used in these specifications is half of this (+5).

The SPT561 requires an external compensation capacitor. Unless otherwise noted, this has been set to 10.5pF for

the frequency domain specifications (yielding a maximally flat frequency response) and 12.5pF for the time domain

specifications (yielding a 0% small signal pulse overshoot response).

10/9/98

SPT561

PARAMETERS

CONDITIONS

TYP

MIN & MAX RATINGS

UNITS

SYM

Case Temperature

SPT561AIJ

+25

-25

+25

+85

Case Temperature

SPT561AMJ

+25

-55

+25

+125

TIME DOMAIN RESPONSE (0% Overshoot Compensation)

rise and fall time

2V step

1.5

<2.0

<1.9

<2.0

TRS

10V step

2.4

<2.8

<3.4

TRL

settling time to 0.5% (time <1

5V step

<12

<15

long term thermal tail (time >1

5V step

1.5

<2.0

slew rate

10V

, 175MHz

3300

>3000

>2900

>2500

overshoot

2V step

maximally flat compensation

<13

<10

<13

OSMF

0% overshoot compensation

OSZO

EQUIVALENT INPUT NOISE

voltage

>100KHz

2.1

<2.5

nV/

√

inverting current

>100KHz

<40

<45

pA/

√

ICN

non-inverting current

>100KHz

2.8

<4.5

<5.0

pA/

√

NCN

noise floor

>100KHz

-159

<-157

dBm/(1Hz)

SNF

integrated noise

1kHz to 200MHz

<45

INV

noise figure

>100KHz

<17

STATIC, DC PERFORMANCE

* input offset voltage

2.0

<14.0

<5.0

<15.0

VIO

average temperature coefficient

<100

–

<100

DVIO

* non-inverting bias current

5.0

<35

<20

IBN

average temperature coefficient

<175

–

<100

nA/

DIBN

* inverting bias current

10.0

<50

<30

<50

IBI

average temperature coefficient

100

<200

–

<200

nA/

DIBI

* power supply rejection ratio (DC)

>54

>52

PSRR

* supply current

no load

<60

<65

ICC

MISCELLANEOUS PERFORMANCE

open loop current gain

(

2% tolerance)

10.0

–

mA/mA

average temperature coefficient

+0.02

<+.03

–

<+.02

inverting input resistance

(

5% tolerance)

14.0

–

Ω

RIN

average temperature coefficient

+.02

<+.025

–

<+.025

Ω

DRIN

non-inverting input resistance

700

>200

>400

Ω

RNI

non-inverting input capacitance

to 100MHz

2.7

<3.5

CNI

output voltage range

150mA load current

10.5

–

10.0

–

output current limit

210

<250

OCL

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are

determined from tested parameters.

Absolute Maximum Ratings

Recommended Operating Conditions

(reversed supplies will destroy part)

20V

10V to

15V

differential input voltage

≤

200mA

common mode input voltage

(|V

| -6)V

junction temperature (see thermal model)

+175

output impedance

Ω

to 200

Ω

storage temperature

-65

C to +150

gain range (no-load voltage gain)

+5 to +80

lead temperature (soldering 10s)

+300

case temperature: AIJ

-25

C to +85

output current (internally limited)

250mA

AMJ

-55

C to +125

Notes

1) *

AIJ, AMJ 100% tested at +25

AMJ

100% tested at at +25

C and sample tested

at -55

C and +125

AIJ

sample tested at +25

2) Test Tones are set

100kHz of indicated frequency.

SPT561 Electrical Characteristics

= +10V, V

15V, R

= 50

Ω

, R

= 410

Ω

, R

= 40

Ω

, R

= 50

Ω

; unless specified)

10/9/98

SPT561

Small Signal Gain and Phase

Gain (dB)

Frequency (MHz)

100

150

200

250

Maximally Flat

Phase (degrees)

-90

-360

-180

-270

0% Overshoot

Gain

Phase

= 10dBm

Frequency Response vs. Gain

Normalized Magnitude (1dB/div)

Frequency (MHz)

100

150

200

250

= 10dBm

= 10

= 5

= 15

= 20

Re-compensated at

each gain (see text)

Frequency Response vs. Output Power

Gain (dB)

Frequency (MHz)

120

160

200

= 10dBm

= 2V

= 24dBm

= 10V

= 27.5dBm

= 15V

= 18dBm

= 5V

Frequency Response vs. R

Normalized Magnitude (1dB/div)

Frequency (MHz)

100

150

200

250

= -4dBm

= 50

Ω

= 25

Ω

= 75

Ω

= 100

Ω

Fixed gain and

compensated vs. load

Frequency Response vs. Power Supply

Frequency (MHz)

100

150

200

250

= 10dBm

= 18

= 12

= 15

= 10

Gain (dB)

Re-compensated at

each supply voltage

Frequency Response vs. R

Frequency (MHz)

100

150

200

250

= -4dBm

Normalized Magnitude (1dB/div)

= 50

Ω

= 25

Ω

= 75

Ω

= 100

Ω

Response measured with matched load

Re-compensated at each R

Frequency Response vs. Gain (R

= 75

Ω

)

Frequency (MHz)

100

150

200

250

= 2V

Normalized Magnitude (1dB/div)

= 5

= 10

= 15

= 20

Re-compensated

at each gain

Gain Flatness/Deviation from Linear Phase

Gain (0.1dB/div)

Frequency (MHz)

100

Phase (0.5

/div)

Gain

Phase

= 10dBm

Internal Current Gain and Phase

Gain (10dB/div)

Frequency (MHz)

-30

-20

100

200

300

400

500

Phase (90

/div)

180

-180

-90

Gain

Phase

-10

= 0

Phase consistant with current

polarity connection of Figure 3

Two Tone, 3rd-Order Intermodulation

Intercept (2.5dB/div)

Frequency (MHz)