41
STK12C68-IM
PIN NAMES
A
0
- A
12
Address Inputs
W
Write Enable
DQ
0
- DQ
7
Data In/Out
E
Chip Enable
G
Output Enable
V
CCX
Power (+5V)
V
SS
Ground
V
CAP
Capacitor
HSB
Hardware Store/Busy
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
A
A
A
A
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
V
W
HSB
A
A
A
G
A
E
SS
7
6
5
4
3
2
1
0
0
1
2
8
9
10
7
6
5
4
3
CAP
A
12
11
CCX
A
A
A
A
A
A
A
A
A
A
A
A
DQ
DQ
DQ
DQ
DQ
DQ
DQ
G
A
E
DQ
Vss
V
W
HSB
7
12
6
5
4
3
2
1
0
0
1
8
9
11
10
7
6
2
3
4
5
TOP VIEW
4
5
6
7
8
9
10
11
12
3
2
1
28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
V
CAP
CCX
28 - LCC
28 - 300 CDIP
PIN CONFIGURATIONS
A
A
A
A
A
A
4
5
6
7
8
EEPROM ARRAY
256 x 256
STORE
RECALL
STATIC RAM
ARRAY
256 x 256
ROW DECODER
STORE/
RECALL
CONTROL
A
A
A
A
A
0
1
2
10
12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
G
E
W
COLUMN I/O
COLUMN DECODER
INPUT BUFFERS
A
A
0
11
A
3
A
9
12
HSB
LOGIC BLOCK DIAGRAM
STK12C68-IM
CMOS nvSRAM
8K x 8
AutoStore™
Nonvolatile Static RAM
Industrial Temperature/Military Screen
FEATURES
• Industrial Temperature with Military Screening
• 25, 35 and 45ns Access Times
• 15 mA I
CC
at 200ns Access Speed
• Automatic
STORE
to
EEPROM
on Power Down
• Hardware or Software initiated
STORE
to
EEPROM
• Automatic
STORE
Timing
• 100,000
STORE
cycles to
EEPROM
• 10 year data retention in
EEPROM
• Automatic
RECALL
on Power Up
• Software initiated
RECALL
from
EEPROM
• Unlimited
RECALL
cycles from
EEPROM
• Single 5V
±
10% Operation
• Commercial and Industrial Temperatures
• Available in multiple standard packages
DESCRIPTION
The Simtek STK12C68-IM is a fast static
RAM
(25, 35
and 45ns), with a nonvolatile
EEPROM
element incor-
porated in each static memory cell. The
SRAM
can be
read and written an unlimited number of times, while
independent nonvolatile data resides in
EEPROM
. Data
transfers from the
SRAM
to the
EEPROM
(
the
STORE
operation
) take place automatically upon power down
using charge stored in an external 100
µ
F capacitor.
Transfers from the
EEPROM
to the
SRAM
(the
RECALL
operation) take place automatically on power up. Soft-
ware sequences may also be used to initiate both
STORE
and
RECALL
operations. A
STORE
can also be
initiated via a single pin.
The STK12C68-IM is available in the following
packages: a 28-pin 300 mil ceramic DIP and a 28-pad
LCC. MIL-STD-883 and Standard Military Drawing
(SMD 5962-94599) devices are also available.
42
STK12C68-IM
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: V
CC
reference levels throughout this datasheet refer to V
CCX
if that is where the power supply connection is made, or V
CAP
if V
CCX
is connected to ground.
DC CHARACTERISTICS
(V
CC
= 5.0V
±
10%)
d
I
CC
b
Average V
CC
Current
95
mA
t
AVAV
= 25ns
85
mA
t
AVAV
= 35ns
80
mA
t
AVAV
= 45ns
I
CC
Average V
CC
Current During
STORE
7
mA
All inputs
≤
0.2V or
≥
(V
CC
- 0.2V)
I
CC
b
Average V
CC
Current
15
mA
E
≤
0.2V, W
≥
(V
CC
– 0.2V)
at t
AVAV
= 200ns
others
≤
0.2V or
≥
(V
CC
– 0.2V)
I
CC
Average V
CC
current during AutoStore™ Cycle
4
mA
All inputs
≤
0.2V or
≥
(V
CC
- 0.2V)
I
SB
c
Average V
CC
Current
39
mA
t
AVAV
= 25ns
(Standby, Cycling TTL Input Levels)
35
mA
t
AVAV
= 35ns
32
mA
t
AVAV
= 45ns
E
≥
V
IH
; all others cycling
I
SB
c
Average V
CC
Current
3
mA
E
≥
(V
CC
– 0.2V)
(Standby, Stable CMOS Input Levels)
all others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
I
ILK
Input Leakage Current (Any Input)
±
1
µ
A
V
CC
= max
V
IN
= V
SS
to V
CC
I
OLK
Off State Output Leakage Current
±
5
µ
A
V
CC
= max
V
OUT
= V
SS
to V
CC
V
IH
Input Logic "1" Voltage
2.2
V
CC
+.5
V
All Inputs
V
IL
Input Logic "0" Voltage
V
SS
–.5
0.8
V
All Inputs
V
OH
Output Logic "1" Voltage
2.4
V
I
OUT
= –4mA except HSB
V
OL
Output Logic "0" Voltage
0.4
V
I
OUT
= 8mA except HSB
T
A
Operating Temperature
-40
85
°
C
1
2
3
4
1
2
3
ABSOLUTE MAXIMUM RATINGS
a
Voltage on typical input relative to V
SS
. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ
0-7
and G. . . . . . . . . . . . . . . . . . .–0.5V to (V
CC
+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55
°
C to 125
°
C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65
°
C to 150
°
C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(One output at a time, one second duration)
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
Note e: These parameters are guaranteed but not tested.
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
C
IN
Input Capacitance
8
pF
∆
V = 0 to 3V
C
OUT
Output Capacitance
7
pF
∆
V = 0 to 3V
CAPACITANCE
e
(T
A
=25
°
C, f=1.0MHz)
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .
≤
5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
AC TEST CONDITIONS
5.0V
Output
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
255 Ohms
Figure 1: AC Output Loading
1
3
43
STK12C68-IM
NO.
PARAMETER
UNITS
Note c: Bringing E
≥
V
IH
will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured
±
200mV from steady state output voltage.
READ CYCLE #1
f,g
DQ (Data Out)
ADDRESS
DATA VALID
2
t
AVAV
3
t
AVQV
5
t
AXQX
READ CYCLES #1 & #2
SRAM MEMORY OPERATION
ADDRESS
E
G
DQ (Data Out)
DATA VALID
2
t
AVAV
1
t
ELQV
6
t
ELQX
4
t
GLQV
8
t
GLQX
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
I
CC
ACTIVE
STANDBY
READ CYCLE #2
f
1
t
ELQV
t
ACS
Chip Enable Access Time
25
35
45
ns
2
t
AVAV
t
RC
Read Cycle Time
25
35
45
ns
3
t
AVQV
g
t
AA
Address Access Time
25
35
45
ns
4
t
GLQV
t
OE
Output Enable to Data Valid
10
20
25
ns
5
t
AXQX
t
OH
Output Hold After Address Change
5
5
5
ns
6
t
ELQX
t
LZ
Chip Enable to Output Active
5
5
5
ns
7
t
EHQZ
h
t
HZ
Chip Disable to Output Inactive
10
17
20
ns
8
t
GLQX
t
OLZ
Output Enable to Output Active
0
0
0
ns
9
t
GHQZ
h
t
OHZ
Output Disable to Output Inactive
10
17
20
ns
10
t
ELICCH
e
t
PA
Chip Enable to Power Active
0
0
0
ns
11
t
EHICCL
c,e
t
PS
Chip Disable to Power Standby
25
35
45
ns
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
SYMBOLS
STK12C68-25-IM
STK12C68-35-IM
STK12C68-45-IM
(V
CC
= 5.0V
±
10%)
d
44
STK12C68-IM
NO.
PARAMETER
UNITS
WRITE CYCLES #1 & #2
WRITE CYCLE #1: W CONTROLLED
i
WRITE CYCLE #2: E CONTROLLED
i
Note h: Measured
±
200mV from steady state output voltage.
Note i: E or W must be
≥
V
IH
during address transitions.
Note j: If W is low when E goes low, the outputs remain in the high impedance state.
12
t
AVAV
t
AVAV
t
WC
Write Cycle Time
25
35
45
ns
13
t
WLWH
t
WLEH
t
WP
Write Pulse Width
20
30
35
ns
14
t
ELWH
t
ELEH
t
CW
Chip Enable to End of Write
20
30
35
ns
15
t
DVWH
t
DVEH
t
DW
Data Set-up to End of Write
10
18
20
ns
16
t
WHDX
t
EHDX
t
DH
Data Hold After End of Write
0
0
0
ns
17
t
AVWH
t
AVEH
t
AW
Address Set-up to End of Write
20
30
35
ns
18
t
AVWL
t
AVEL
t
AS
Address Set-up to Start of Write
0
0
0
ns
19
t
WHAX
t
EHAX
t
WR
Address Hold After End of Write
0
0
0
ns
20
t
WLQZ
h,j
t
WZ
Write Enable to Output Disable
10
17
20
ns
21
t
WHQX
t
OW
Output Active After End of Write
5
5
5
ns
SYMBOLS
STK12C68-25-IM
STK12C68-35-IM
STK12C68-45-IM
PREVIOUS DATA
ADDRESS
E
W
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
12
t
AVAV
14
t
ELWH
19
t
WHAX
17
t
AVWH
18
t
AVWL
13
t
WLWH
15
t
DVWH
16
t
WHDX
20
t
WLQZ
21
t
WHQX
ADDRESS
E
W
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
12
t
AVAV
18
t
AVEL
14
t
ELEH
19
t
EHAX
17
t
AVEH
13
t
WLEH
15
t
DVEH
16
t
EHDX
(V
CC
= 5.0V
±
10%)
d
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
45
STK12C68-IM
Note e: These parameters guaranteed but not tested.
Note n: HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-IMs to be ganged together for
simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68 HSB pins.
Note o: A RECALL cycle is initiated automatically at power up when V
CC
exceeds V
SWITCH
. t
RESTORE
is measured from the point at which V
CC
exceeds 4.5V.
MODE SELECTION
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
l
L
L
H
X
Write SRAM
Input Data
Active
L
H
H
0000
Read SRAM
Output Data
Active
k,l
1555
Read SRAM
Output Data
k,l
0AAA
Read SRAM
Output Data
k,l
1FFF
Read SRAM
Output Data
k,l
10F0
Read SRAM
Output Data
k,l
0F0F
Nonvolatile
STORE
Output High Z
k
L
H
H
0000
Read SRAM
Output Data
Active
k,l
1555
Read SRAM
Output Data
k,l
0AAA
Read SRAM
Output Data
k,l
1FFF
Read SRAM
Output Data
k,l
10F0
Read SRAM
Output Data
k,l
0F0E
Nonvolatile
RECALL
Output High Z
k
X
X
L
X
STORE
/Inhibit
Output High Z
I
CC2
/Standby
m
NONVOLATILE MEMORY OPERATION
E
W
HSB
A
12
- A
0
(hex)
MODE
I/O
POWER
NOTES
Note k:
The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE
cycle or (0000, 1555, 0AAA, 1FFF, 10F0,
0F0E) for a
RECALL
cycle
.
W must be high during all six consecutive cycles. See
STORE
cycle
and
RECALL
cycle
tables and diagrams for further details.
Note l:
I/O state assumes that G
≤
V
IL
. Activation of nonvolatile cycles does not depend on the state of G.
Note m: HSB initiated
STORE
operation actually occurs only if a WRITE has been done since last
STORE
operation. After the
STORE
(if any) completes, the
part will go into standby mode inhibiting all operation until HSB rises.
HARDWARE
STORE /RECALL
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
NOTES
22