TSB12LV31
Data Manual
IEEE 1394-1995 General-Purpose
Link-Layer Controller
For Computer Peripherals and
Consumer Audio/Video Electronics
SLLS255A
SEPTEMBER 1998
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright
©
1998, Texas Instruments Incorporated
iii
Contents
Section
Title
Page
1
Overview
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Description
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features
1–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Related Documents
1–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Functional Block Diagram
1–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Terminal Assignments
1–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6
Terminal Functions
1–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Architecture
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Functional Block Diagram
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 FIFO
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Microcontroller Interface
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Link Core
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Data Mover (DM) Control
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Internal Registers
3–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Memory and Configuration Address Space Register Map
3–1
. . . . . . . . . . . . . . . . . . .
3.1.1 TSB12LV31 Configuration Registers
3–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Configuration Register Definitions
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Version Register @00h
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 MISC Register @04h
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Control Register @08h
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Interrupt/Interrupt Mask Register @0Ch/10h
3–5
. . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Cycle Timer Register @14h
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 IsoPort Number Register @18h
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.7 Diagnostics Register @20h
3–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 Phy Access Register @24h
3–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.9 ATF Status Register @30h
3–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.10 Bus Reset Register @34h
3–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.11 Self-ID Check Register @38h
3–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.12 GRF Status Register @3Ch
3–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.13 FIFO State Register @50h
3–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.14 Isochronous Control Register @54h
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.15 Isochronous Mode Register @58h
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.16 Isochronous Header Register @5Ch
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Contents (continued)
Section
Title
Page
4
FIFO Access
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
FIFO Access
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 ATF Access
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 General-Receive-FIFO (GRF)
4–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
TSB12LV31 Data Formats
5–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Asynchronous Transmit (Host Bus to TSB12LV31)
5–1
. . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Quadlet Transmit
5–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Block Transmit
5–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3 Quadlet Receive
5–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4 Block Receive
5–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Isochronous Transmit (Host Bus to TSB12LV31)
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Isochronous Receive (TSB12LV31 to Host Bus)
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
Snoop
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
CycleMark
5–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Phy Configuration
5–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Receive Self-ID Packet
5–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Electrical Characteristics
6–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Absolute Maximum Ratings Over Free-Air Temperature Range
6–1
. . . . . . . . . . . . . .
6.2
Recommended Operating Conditions
6–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature Range
6–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Microcontroller Write Switching Characteristics Over Operating Free-Air
Temperature Range
6–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Microcontroller Read Switching Characteristics Over Operating Free-Air
Temperature Range
6–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
IsoPort Phase 1, 2, and 3 Switching Characteristics Over Operating Free-Air
Temperature Range
6–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
IsoPort Receive Switching Characteristics Over Operating Free-Air
Temperature Range
6–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
Link Read/Write Switching Characteristics Over Operating Free-Air
Temperature Range
6–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
Output Signals Synchronous with ISOCK Switching Characteristics Over Operating
Free-Air
Temperature
Range
6–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Mechanical Information
7–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
List of Illustrations
Figure
Title
Page
1–1 TSB12LV31 Functional Block Diagram
1–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Terminal Assignments
1–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 TSB12LV31 Functional Block Diagram
2–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Typical Handshake Doublet-Mode Timing Waveforms
2–2
. . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Typical Handshake Byte-Mode Timing Waveforms
2–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Pulse Mode Timing Waveforms
2–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Timing Waveforms for 16-Bit Pulse Mode with Fixed Timing
2–5
. . . . . . . . . . . . . . . . . . . . .
2–6 Timing Waveforms for 8-Bit Pulse Mode with Fixed Timing
2–7
. . . . . . . . . . . . . . . . . . . . . .
2–7 Microcontroller Byte Stack Operation (Write)
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Microcontroller Byte UnStack Operation (Read)
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Link Core Components
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Isochronous DM Flow Control (TSB12LV31 Transmit)
2–12
. . . . . . . . . . . . . . . . . . . . . . . .
2–11 Isochronous Transmit Data Path
2–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Configuration Register (CFR) Map
3–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 TSB12LV31 Controller-FIFO-Access Address Map
4–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Quadlet-Transmit Format
5–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Block-Transmit Format
5–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Quadlet-Receive Format
5–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Block-Receive Format
5–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Isochronous-Transmit Format
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Isochronous-Receive Format
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Snoop Format
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 CycleMark Format
5–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Phy Configuration Format
5–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Receive Self-ID Format
5–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Phy Self-ID Packet #0 Format
5–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 Phy Self-ID Packet #1, Packet #2, and Packet #3 Format
5–10
. . . . . . . . . . . . . . . . . . . . .
6–1 Microcontroller Write-Operation Timing Waveforms
6–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Microcontroller Read-Operation Timing Waveforms
6–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 IsoPort Phase 1 (Four-Byte Preread) Timing Waveforms
6–5
. . . . . . . . . . . . . . . . . . . . . . . .
6–4 IsoPort Phase 2 (Data Transmit to End of Packet) Timing Waveforms
6–6
. . . . . . . . . . . . .
6–5 IsoPort Phase 3 (End of Block) Timing Waveforms
6–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 IsoPort Receive Timing Waveforms
6–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 Isochronous Receive of One Quadlet at 200 Mbits/s
6–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–8 Isochronous-Receive Four Quadlets with Data Error at 200 Mbits/s
6–9
. . . . . . . . . . . . . . .
6–9 Link Read Waveforms
6–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–10 Link Write Waveforms
6–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–11 Synchronous ISOCK Output Waveforms
6–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Tables
Table
Title
Page
1–1 Terminal Functions
1–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 STAT0 and STAT1 Programming
1–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Isochronous Transmit Packet Structure
2–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Memory and Configuration Address Space Map
3–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 MISC Register Field Descriptions @04h
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Control Register Field Descriptions @08h
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Interrupt/Interrupt Mask Register Field Descriptions @0Ch/10h
3–5
. . . . . . . . . . . . . . . . . .
3–5 Cycle-Timer Register Field Descriptions @14h
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 IsoPort Number Register Field Descriptions @18h
3–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Diagnostics Register Field Descriptions @20h
3–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Recommended Range for XtendClk
3–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 Phy Access Register @24h
3–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 ATF Status Register @30h
3–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Bus Reset Register @34h
3–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Self-ID Check Register@38h
3–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 GRF Status Register @3Ch
3–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 FIFO State Register @50h
3–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–15 Isochronous Control Register @54h
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Isochronous Mode Register @58h
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Isochronous Mode Register@5Ch
3–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Quadlet-Transmit Format Functions
5–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Block-Transmit Format Functions
5–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Quadlet-Receive Format Functions
5–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 Block-Receive Format Functions
5–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 Isochronous-Transmit Functions
5–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 Isochronous-Receive Functions
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 Snoop Functions
5–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 CycleMark Function
5–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 Phy Configuration Functions
5–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Receive Self-ID Function
5–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 GRF Contents With Three Nodes on a Bus
5–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 Phy Self-ID Functions
5–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Tables (continued)
Table
Title
Page
6–1 Microcontroller Write Timing
6–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Microcontroller Read Timing
6–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 IsoPort Timing Phases 1, 2, and 3
6–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 IsoPort Receive Timing
6–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Link Read/Write Timing
6–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Synchronous ISOCK Output Timing
6–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
1–1
1 Overview
1.1
Description
The TSB12LV31 performs bidirectional asynchronous/isochronous data transfers to and from an IEEE
1394-1995 serial bus physical layer (phy) device. The TSB12LV31 is tailored and optimized for use as a
peripheral link-layer controller (LLC). TSB12LV31 asynchronous and isochronous operations are
summarized as follows:
TSB12LV31 asynchronous transmit:
From asynchronous transmit FIFO (ATF)
TSB12LV31 asynchronous receive:
To general receive FIFO (GRF)
TSB12LV31 isochronous transmit:
From 8-bit IsoPort
TSB12LV31 isochronous receive:
To 8 bit IsoPort,
To GRF, or
To 8-bit IsoPort and To GRF
This document is not intended to serve as a tutorial on the 1394; users should refer to the IEEE 1394-1995
standard for more detailed information.
1.2
Features
The TSB12LV31 supports the following features:
•
Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus (1394)
†
•
Fully Interoperable with FireWire
™
Implementation of 1394
•
Compatible with Texas Instruments TSB11LV01 and TSB21LV03 Physical Layer Controllers
(Phys)
•
Single 3.3-V supply operation with 5-V Tolerant Capabilities using 5-V Bias Terminals
•
High-performance 100-Pin PZ (S–PQFP–G100) package.
•
Programmable Microcontroller Interface with 8-Bit or 16-Bit Data Bus, Three Modes of Operation,
and Clock Frequency to 50 Mhz
•
50-quadlet (200-Byte) FIFO Accessed Through Microcontroller Interface Supports
Asynchronous and Isochronous Operations
•
Programmable FIFO Size For Asynchronous Transmit FIFO and General-Receive FIFO
•
Single-Channel Support for Isochronous Transmit from Unbuffered 8-Bit Isochronous Port
(IsoPort)
•
Isochronous Receive to FIFO or to Unbuffered 8-Bit IsoPort
•
Isochronous Header Synchronous-Bit Detection on Receive
•
Automatically Reports IRM NODE_ID and Verifies Automatic 1394 Self-ID
•
Transfer Rates of 100 Mbits/s and 200 Mbits/s
•
Asynchronous Packet Reception to Internal FIFO (Accessed Through the Microcontroller
Interface)
•
Asynchronous Packet Transmission from Internal FIFO (Accessed Through the Microcontroller
Interface)
•
Generation of External Microcontroller Clock from SCLK (SCLK/4)
•
Generation of 32-Bit Cyclic Redundancy Check (CRC) for Transmission of 1394 Packets
•
32-Bit CRC Checking on Reception of 1394 Packets
† Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
1–2
1.3
Related Documents
The following document is applicable and should be referenced for additional information:
•
IEEE STD IEEE 1394-1995 High Performance Serial Bus
1.4
Functional Block Diagram
The functional block diagram of the TSB12LV31 is shown in Figure 2–1.
MA0 – MA7
MD0 – MD15
BCLK
Byte Stacker
8-/16-to-32 bits
8
/
16
/
8
/
32
/
8
/
32
/
Address
Data
FIFO
CFR
Control
ATF
ARF
IRF
Phy/LLC
Interface
Host Interface
Link Core
DM
ISOD0 – ISOD7
Isochronous
Control
8
/
Isochronous
Port (IsoPort)
32
/
ITF
÷
2
SCLK
÷
4
MCLK
Microcontroller
Interface
MCA
MCS
Status
Figure 1–1. TSB12LV31 Functional Block Diagram
1–3
1.5
Terminal Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD13
MD12
GND
MD9
MD8
MD7
MD6
MD5
MD4
GND
MD2
MD1
MCLK
BCLK
MA7
MA6
GND
GND
ISOD1
ISOD2
ISOD3
ISOD7
ISOD4
ISOD5
ISOD6
GND
ISORST
ISORW
CONTNDR
IDATARDY
IDMDONE
PKTFLAG
GND
CYCLEIN
CYCLEOUT
RESET
IDMRST
GND
CYDONE
CYST
AR
T
S
TAT
1
S
TAT
0
MARXD
MBUSY
MCMODE1
MCMODE0
MD15
MD14
GND
GND
D3
D2
D1
D0
CTL1
SCLK
LREQ
NTBIHIZ
NT
OUT
NTCLK
MA0
MA1
GND
MA4
MA5
MD11
V
CC
5V
RAMEZ
CC
V
PZ PACKAGE
(TOP VIEW)
ISOD0
ISOCK
MIRXD
MD10
MD3
MD0
CTL0
MA2
V
CC
V
CC
ISOERROR
V
CC
CC
V
GND
CC
V5
V
CC
V
MA3
V
CC
V
CC
V
CC
V
CC
5V
CC
V
CC
V
CC
V
CC
V5
V
GND
POWERON
TSB12LV31
INT
MCS
MCA
MWR
Figure 1–2. Terminal Assignments
1–4
1.6
Terminal Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD13
MD12
GND
MD9
MD8
MD7
MD6
MD5
MD4
GND
MD2
MD1
MCLK
BCLK
MA7
MA6
GND
GND
ISOD1
ISOD2
ISOD3
ISOD7
ISOD4
ISOD5
ISOD6
GND
ISORST
ISORW
CONTNDR
IDATARDY
IDMDONE
PKTFLAG
GND
CYCLEIN
CYCLEOUT
RESET
IDMRST
GND
CYDONE
CYST
AR
T
S
TAT
1
S
TAT
0
MARXD
MBUSY
MCMODE1
MCMODE0
MD15
MD14
GND
GND
D3
D2
D1
D0
CTL1
SCLK
LREQ
NTBIHIZ
NT
OUT
NTCLK
MA0
MA1
GND
MA4
MA5
MD11
V
CC
5V
RAMEZ
CC
V
WN PACKAGE
(TOP VIEW)
ISOD0
ISOCK
MIRXD
MD10
MD3
MD0
CTL0
MA2
V
CC
V
CC
ISOERROR
V
CC
CC
V
GND
CC
V5
V
CC
V
MA3
V
CC
V
CC