1
PS8379 04/16/99
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI7ALVCH16269 is used in applications in which two separate
ports must be multiplexed onto, or demultiplexed from, a single port.
It is particularly suitable as an interface between synchronous DRAM’s
and high-speed microprocessors.
Data is stored on the internal B-port registers on the low-to-high
transition of the clock (CLK) input when the appropriate clock-enable
(CLKENA) inputs are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit word on the B-port.
For data transfer in the B-to-A direction, a single storage register is
provided. The select (SEL) line selects 1B or 2B data for the A outputs.
The register on the A output permits the fastest possible data transfer,
thus extending the period during which the data is valid on the bus. The
control terminals are registered so that all transactions are synchronous
with CLK. Data flow is controlled by the active-low output enables
(OEA, OEB1, and OEB2).
To ensure the high-impedance state during power up or power
down, a clock pulse should be applied as soon as possible and OE
should be tied to V
CC
through a pullup resistor; the minimum value
of the resistor is determined by the current-sinking capability of the
driver. Because OE is being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the
first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Product Features
•
PI74ALVCH16269 is designed for low voltage operation
•
V
CC
= 2.3V to 3.6V
•
Hysteresis on all inputs
•
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
•
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
•
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
•
Industrial operation at 40°C to +85°C
•
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
2
PS8379 04/16/99
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
↑
= Transition, Low to High
2.
Output level before indicated steady
state input conditions established.
s
t
u
p
n
I
s
t
u
p
t
u
O
K
L
C
A
E
O
B
E
O
A
B
2
,
B
1
↑
H
H
Z
Z
↑
H
L
Z
e
v
it
c
A
↑
L
H
e
v
it
c
A
Z
↑
L
L
e
v
it
c
A
e
v
it
c
A
s
t
u
p
n
I
s
t
u
p
t
u
O
A
K
L
C
L
E
S
B
1
B
2
X
H
X
X
0
A
)
2
(
X
L
X
X
0
A
)
2
(
↑
H
L
X
L
↑
H
Η
X
H
↑
L
X
L
L
↑
L
X
H
H
S
T
U
P
N
I
S
T
U
P
T
U
O
1
A
N
E
K
L
C
2
A
N
E
K
L
C
K
L
C
A
B
1
B
2
H
H
X
X
B
1
0 )
2
(
B
2
0 )
2
(
L
X
↑
L
L
X
L
X
↑
H
H
X
X
L
↑
L
X
L
X
L
↑
H
X
H
Pin Name
Description
OE
Output Enable Input (Active LOW)
CLK
Clock
SEL
Select (Active Low)
CLKEN
Clock Enable (Active Low)
A,1B,2B
3-State Outputs
GND
Ground
VCC
Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
Product Pin Description
Product Pin Configuration
56-PIN
A56
V56
OEA
OEB1
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
NC
SEL
OEB2
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
Truth Tables
(1)
A to B STORAGE (OEB = L)
B to A STORAGE (OEA = L)
3
PS8379 04/16/99
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 3.3V ±10%)
s
r
e
t
e
m
a
r
a
P
n
o
it
p
i
r
c
s
e
D
s
n
o
it
i
d
n
o
C
t
s
e
T
.
n
i
M
.
p
y
T
.
x
a
M
s
ti
n
U
V
C
C
e
g
a
tl
o
V
y
l
p
p
u
S
3
.
2
6
.
3
V
V
H
I
)
1
(
e
g
a
tl
o
V
H
G
I
H
t
u
p
n
I
V
C
C
V
7
.
2
o
t
V
3
.
2
=
7
.
1
V
C
C
V
6
.
3
o
t
V
7
.
2
=
0
.
2
V
L
I
)
1
(
e
g
a
tl
o
V
W
O
L
t
u
p
n
I
V
C
C
V
7
.
2
o
t
V
3
.
2
=
7
.
0
V
C
C
V
6
.
3
o
t
V
7
.
2
=
8
.
0
V
N
I
)
1
(
e
g
a
tl
o
V
t
u
p
n
I
0
V
C
C
V
T
U
O
)
1
(
e
g
a
tl
o
V
t
u
p
t
u
O
0
V
C
C
I
H
O
)
1
(
l
e
v
el
-
H
G
I
H
t
n
e
rr
u
C
t
u
p
t
u
O
V
C
C
V
3
.
2
=
2
1
-
A
m
V
C
C
V
7
.
2
=
2
1
-
V
C
C
V
0
.
3
=
4
2
-
I
L
O
)
1
(
l
e
v
el
-
W
O
L
t
n
e
rr
u
C
t
u
p
t
u
O
V
C
C
V
3
.
2
=
2
1
V
C
C
V
7
.
2
=
2
1
V
C
C
V
0
.
3
=
4
2
T
A
e
r
u
t
a
r
e
p
m
e
T
ri
A
-
e
e
r
F
g
n
it
a
r
e
p
O
0
4
-
5
8
C
º
/t
A
∆
V
e
t
a
R
ll
a
F
r
o
e
si
R
n
o
it
i
s
n
a
r
T
t
u
p
n
I
0
1
V
/
s
n
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................ 65°C to +150°C
Supply Voltage Range, V
CC .................................................
0.5V to 4.6V
Input Voltage Range,V
I
: Except
I/O ports
(1) ................................................................................
0.5V to 4.6V
I/O ports
(1,2) ...............................................................
0.5V to V
CC
+ 0.5V
Output Voltage Range, V
O
(1,2) ..............................
0.5V to V
CC
+ 0.5V
Input Clamp current, I
IK
(V
I
< 0) ............................................ 50mA
Output Clamp current, I
OK
(V
O
< 0) ....................................... 50mA
Continous Output Current, I
O
.................................................. ±50mA
Continous Current through each V
CC
or GND ...................... ±100mA
Maximum Power Dissipation:
A package ........................................................................................1W
V package .....................................................................................1.4W
Notes:
1. The input and output negative-voltage ratings maybe exceeded if the input
and outputclamp-current ratings are observed.
2. This value is limited to 4.6V maximum.
PI74ALVCH16269
12-Bit to 24-Bit Registered Bus Exchanger
with 3-State Outputs
4
PS8379 04/16/99
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
s
r
e
t
e
m
a
r
a
P
s
n
o
it
i
d
n
o
C
t
s
e
T
V
C
C
)
1
(
.
n
i
M
.
p
y
T
)
2
(
.
x
a
M
s
ti
n
U
V
H
O
I
H
O
= 0
1
-
0 Α
µ
.
x
a
M
o
t
.
n
i
M
V
C
C
2
.
0
-
V
I
H
O
= 6
- m
Α
V
3
.
2
0
.
2
I
H
O
= 2
1
- m
Α
V
3
.
2
7
.
1
V
7
.
2
2
.
2
V
0
.
3
4
.
2
I
H
O
= 4
2
- m
Α
V
0
.
3
0
.
2
V
L
O
I
L
O
= 0
1
0 Α
µ
.
x
a
M
o
t
.
n
i
M
2
.
0
I
L
O
= 6m
Α
V
3
.
2
4
.
0
I
L
O
= 2
1 m
Α
V
3
.
2
7
.
0
V
7
.
2
4
.
0
I
L
O
= 4
2 m
Α
V
0
.
3
5
5
.
0
I
I
V
I
= V
CC
r
o
D
N
G
V
6
.
3
5
±
Α
µ
I
I
)
d
l
o
H
(
)
3
(
V
I
=
V
7
.
0
V
3
.
2
5
4
V
I
=
V
7
.
1
5
4
-
V
I
=
V
8
.
0
V
0
.
3
5
7
V
I
=
V
0
.
2
5
7
-
V
I
= 0
V
6
.
3
o
t
V
6
.
3
0
0
5
±
I
Z
O
)
4
(
V
O
= V
C
C
D
N
G
r
o
V
6
.
3
0
1
±
I
C
C
V
I
= V
C
C
I
,
D
N
G
r
o
O
0
=
V
6
.
3
0
4
Ι
∆
C
C
V
t
a
t
u
p
n
i
e