MAS3504D, G.729 Annex A Voice Codec

MAS 3504D

ADVANCE INFORMATION

Micronas

G.729 Annex A Voice Codec

1. Introduction

The MAS 3504D is a single-chip codec for use in

memory-based voice recording and playback applica-

tions. Due to embedded memories, the embedded DC/

DC up-converter, and the very low power consump-

tion, the MAS 3504D is ideally suited for portable elec-

tronics.

The MAS 3504D implements a voice encoder and

decoder that is compliant to the ITU Standard G.729

Annex A. This standard works on 8 kHz, 16 bit, mono

audio data that is compressed to 1 bit per audio sam-

ple. One second of compressed audio data uses

1000 bytes of memory.

1.1. Features

– Single-chip G.729 decoder

– G.729 Annex A encoder

– ITU compliance tests passed

– Parallel input and parallel output of coded bitstream

data

– Input audio data read from an I

S bus (in various

formats)

– Output audio data delivered via an I

S bus (in vari-

ous formats)

– Digital volume / mute

– Low power dissipation (150 mW for encoder, 80 mW

for decoder @ 3.3 V)

– Supply voltage range: 1.0 V to 3.6 V due to built-in

DC/DC converter (1-cell battery operation)

– Adjustable power supply supervision

– Power-off function

– Additional functionality achievable via download

software (ADPCM encoder/decoder)

Fig. 1–1: MAS 3504D block diagram

CLKI

decoded output

voice audio data

/3/

Serial In

RISC DSP Core

PIO

/3/

/8+5/

/2/

serial control

MAS 3504D

parallel I/O

DC/DC

Converter

Clock

Synthesizer

Serial Out

ADVANCE INFORMATION

MAS 3504D

Micronas

1.2. Application Overview

The MAS 3504D can be applied in two major environ-

ments: as standalone decoder or as encoder/decoder

combination. For decoding only mode, the DAC 3550A

fits perfectly to the requirements of the MAS 3504D. It

is a high-quality multi sample rate DAC (8 kHz ...

50 kHz) with internal crystal oscillator, which is only

needed for generating the decoder Clock, and inte-

grated stereo headphone amplifier plus 2 stereo

inputs.

1.2.1. Decoder Mode

In a memory-based voice playback environment, the

decoding is started with a command from a controller.

Then the MAS 3504D continuously requests frames of

G.729 data every 10 ms via the parallel (PIO) inter-

face.

A delayed response of the host to the request signal

(max. 20 milliseconds) will be tolerated by the

MAS 3504D as long as the input buffer does not run

empty. A PC might use its DMA capabilities to transfer

the data in the background to the MAS 3504D without

interfering with its foreground processes.

The source of the bit stream may be a memory (e.g.

ROM, Flash) or PC peripherals, such as CD-ROM

drive, a hard disk or a floppy disk drive.

1.2.2. Encoder Mode

For encoding a support routine must be downloaded to

the MAS 3504D via I

C. After the encoder is started, it

begins to encode the incomming audio data and writes

the coded datastream to the parallel (PIO) interface.

A delayed response of the host to the data available

signal (max. 20 milliseconds) will be tolerated by the

MAS 3504D as long as the output buffer does not

overrun.

Fig. 1–2: Block diagram of a MAS 3504D, decoding a stored bit stream in a decoding only application

Fig. 1–3: Block diagram of a MAS 3504D in an encoding/decoding application

ROM, CD-ROM,

RAM, Flash Mem. ..

Host

(PC, Controller)

line out

demand signal

demand clock

G.729 bit stream

CLKI

CLKOUT

18.432 MHz

MAS 3504D

DAC

3550A

ROM, CD-ROM,

RAM, Flash Mem. ..

Host

(PC, Controller)

clock

line in

CLKI

G.729 bit stream

Mic in

Handshake signals

line out

strobe

data out

data in

S lines

MAS 3504D

PLL

AD/DA

MAS 3504D

ADVANCE INFORMATION

Micronas

2. Functional Description of the MAS 3504D

2.1. DSP Core

The hardware of the MAS 3504D consists of a high

performance Digital Signal Processor and appropriate

interfaces. The processor works with a memory word

length of 20 bits and an extended range of 32 bits in its

accumulators. The instruction set of the DSP is highly

optimized for audio data compression and decompres-

sion. Thus, only very small areas of internal RAM and

ROM are required. All data input and output actions

are based on a ‘non cycle stealing’ background DMA

that does not cause any computational overhead.

2.2. Firmware (Internal Program ROM)

The firmware fully contains a G.729 voice decoder.

With an additional support routine the IC is extended to

a G.729 Annex A encoder.

The G.729 standard compresses 8 kHz/16 bit mono

voice data in frames of 80 samples to 10 bytes each,

what results in a compressed bitstream of 1 bit/sam-

ple. The encoding according to Annex A has reduced

complexity, but is fully compatible to the initial G.729

standard. Therefore the MAS 3504D can decode bit-

streams that were encoded by other G.729 encoders

and it can encode bitstreams that can be decoded with

other G.729 decoders.

2.2.1. G.729 Encoder

For encoding operation the MAS 3504D has to be pre-

pared by downloading an additional routine to support

the encoder. After starting the encoder, 80 audio sam-

ples are continously read via the serial input interface.

Each audio block of 80 samples is encoded to a G.729

data frame consisting of 10 bytes which is sent via the

parallel interface. It is possible to monitor the input

audio samples also directly via the serial output inter-

face.

2.2.2. G.729 Decoder

The MAS 3504D expects a sequence of valid G.729

frames (10 bytes each) as input. The compressed data

is sent via the parallel interface. Each frame is

decoded to 80 audio samples, modified by the volume/

mute control and sent out via the serial output inter-

face.

2.3. Program Download Feature

The overall function of the MAS 3504D can be altered

by downloading up to 1 kWord program code into the

internal RAM and by executing this code instead of the

ROM code. During this time, G.729 processing is not

possible.

The code must be downloaded by the ‘write to mem-

ory’ command (see Section 3.3.) into an area of inter-

nal RAM. A ‘run’ command starts the operation.

Micronas provides modules for encoding and decoding

audio data with ADPCM.

Detailed information about downloading is provided in

combination with the MAS 3504D software develop-

ment package from Micronas.

2.4. Clock Management

The MAS 3504D should be driven by a single clock at

a frequency of 18.432 MHz.

The CLKI signal acts as a reference for the embedded

clock synthesizer that generates the internal system

clock.

2.5. Power Supply Concept

The MAS 3504D offers an embedded controlled DC/

DC converter and voltage monitoring circuits for bat-

tery based power supply concepts. It works as an up-

converter. The application circuit for the DC/DC con-

verter is shown in Fig. 2–1.

2.5.1. Internal Voltage Monitor

An internal voltage monitor compares the input voltage

at the VSENS

pin with an internal reference value that

is adjustable via I

C bus. The PUP output pin becomes

inactive when the voltage at the VSENS pin drops

below the programmed value of the reference voltage.

It is important that the WSEN must not be activated

before the PUP is generated. The PUP signal thresh-

olds are listed in Table 3–8.

ADVANCE INFORMATION

MAS 3504D

Micronas

2.5.2. DC/DC Converter

The DC/DC converter of the MAS 3504D is used to

generate a fixed power supply voltage even if the chip

is powered by battery cells in portable applications.

The DC/DC converter is designed for the application of

1 or 2 batteries or NiCd cells. The DC/DC converter is

switched on by activating the DCEN pin. Its output

power is sufficient for other ICs as well.

A 22

H inductor is required for the application. The

important specification item is the inductor saturation

current rating, which should be greater than 2.5 times

the DC load current. The DC resistance of the inductor

is important for efficiency. The primary criterion for

selecting the output filter capacitor is low equivalent

series resistance (ESR), as the product of the inductor

current variation and the ESR determines the high-fre-

quency amplitude seen on the output voltage. The

Schottky diode should have a low voltage drop V

for a

high overall efficiency of the DC/DC converter. The

current rating of the diode should also be greater than

2.5 times the DC output current. The VSENS pin is

always connected to the output voltage at the low ESR

capacitor.

2.5.3. Stand-by Functions

The digital part of the MAS 3504D and the DC/DC

converter are turned on by setting WSEN. If only the

DC/DC converter should work, it can remain active

bysetting DCEN alone to supply other parts of the

application even if the audio decoding part of the

MAS 3504D is not being used. The WSEN power-up

pin of the digital part should be handled by the control-

ler.

Please pay attention to the fact, that the I

C interface is

working only if the processor is powered up

(WSEN = 1).

Fig. 2–1: DC/DC converter application circuit

voltage monitor

DC/DC

converter

Start-up

oscillator

Frequency

divider

optional

filter

+32

0...15

32...47

64...94

−

VSS

AVSS

AVDD

VDD

CLKI

DCSO

DCSG

DCEN

PUP

WSEN

VSENS

≥

0.9 V

out

330

Low ESR

330

DCCF

$8e

47 k

Ω

µController

47 k

Ω

Power-On

Push Button

MAS 3504D

ADVANCE INFORMATION

Micronas

2.5.4. Start-up Sequence

The DC/DC converter operates at a minimum input

voltage of 0.9 V. In case WSEN is active, the

MAS 3504D is in the DSP operation mode. The start-

up script should be as follows:

1. in the power-off state DCEN and WSEN are inactive

2. set DCEN to > 0.9 V

3. hold DCEN until controller operates, detects if

PUP

is high, and sets WSEN to high.

Please also refer to Figure 2–2.

Note: Connecting DCEN directly to VDD leads to unex-

pected states of the DCCF register.

The PUP signal should be read out by the system con-

troller and used to set WSEN.

2.6. Interfaces

The MAS 3504D uses an I

C control interface, a paral-

lel I/O interface (PIO) for G.729- or ADPCM-data, a

digital audio input interface (SDI) for audio data input

and a digital audio output interface (SDO) for the

decoded audio data (I

S or similar).

The G.729 bit stream generated by an encoder is

aligned in frames of 10 bytes. The parallel data

required from the G.729 decoder must be sent in byte-

swapped order related to the standard specification.

The G.729 encoder also sends the encoded bit stream

byte-swapped to the PIO interface.

2.6.1. Parallel Input Output Interface (PIO)

The parallel interface of the MAS 3504D consists of

the lines PI0...PI4, PI8, PI12...PI19, and several con-

trol lines.

Fig. 2–2: DC/DC startup

2.6.2. Parallel Data Output

In encoding mode, PIO lines PI12

...

PI19 are switched

to the MAS 3504D data output which hence will be an

8-bit parallel output port with MSB first (at position

PI19) for the G.729 bit stream data.

The data is transfered in bursts of 10 bytes (1 frame)

each 10 ms. If the transmission of headers is enabled,

there is an additional 10 byte burst before each

sequence of 50 frames.

Handshaking for PIO output mode is accomplished

through the RTW, PCS, and PI12

PI19 signal lines

(see Fig. 2–3). The PR line has to be set to high level.

RTW will go low as soon as a byte is available in the

output buffer and will stay low until a byte has been

read. Reading of a byte is performed with a PCS pulse.

Data is latched out from the MAS 3504D on the falling

edge of PCS and removed from the bus on the rising

edge of PCS.

Fig. 2–3: Parallel Data Output (PIO) Timing

> 0.9 V

WSEN > 2 V

DCEN

DSP

operation

µController

DC/DC

button

RTW

PIxx

PCS

ADVANCE INFORMATION

MAS 3504D

Micronas

2.6.3. Parallel Data Input

In decoding mode, PIO lines PI12

...

PI19 are switched

to the MAS 3504D data input which hence will be an 8-

bit parallel input port with MSB first (at position PI19)

for the G.729 bit stream data. In order to write data to

this parallel port, a special handshake protocol has to

be used by the controller (see Fig. 2–4).

2.6.3.1. DMA Handshake Protocol

The data transfer can be started after the EOD pin of

the MAS 3504D is set to high. After verifying this, the

controller indicates the transmission of data by activat-

ing the PR line. The MAS 3504D responds by setting

the RTR line to the low level. The MAS 3504D reads

the data PI[19:12] after the rising edge of the PR. The

next data word write operation will again be initialized

by setting the PR line via the controller. Please refer to

Figure 2–4 and Table 2–2 for the exact timing.

Fig. 2–4: Handshake protocol for writing G.729 data to the PIO-DMA

Table 2–1: PIO Output Mode Timing

Symbol

Pin

Min.

Max.

Unit

RTW, PCS

0.010

1800

PCS

0.330

PCS, RTW

0.010

RTW

0.330

10000

0.330

0.081

see Figure 2–3

EOD

RTR

PI[19:12]

high

low

high

low

high

low

high

low

rpr

rtrq

set

eodq

eod

Byte 15

Byte 1

MAS 3504D latches the PIO DATA

MAS 3504D

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Micronas

2.6.3.2. End of DMA Transfer

The above procedure will be repeated until the

MAS 3504D sets the EOD signal to “0”, which indi-

cates that the transfer of one data block has been exe-

cuted. Subsequently, the controller should set PR to

“0”, wait until EOD rises again, and then repeat the

procedure (see Section 2.6.3.1. ) to send the next

block of data. The DMA buffer is 10 bytes long (one

frame).

The recommended PIO DMA conditions and the char-

acteristics of the PIO timing are given in Table 2–2.

2.6.4. Audio Input Interface (SDI)

The A/D interface is a standard I

S interface (16/32 bit,

stereo). This input is used for G.729 recording mode

and must be slaved to the D/A output clock and word-

strobe signals.

The interface is configurable by software to work in dif-

ferent modes. It is possible to choose:

– inverted or noninverted word strobe (SOI),

– no delay or delay of data related to word strobe

– inverted or noninverted I

S-Clock (SOC).

For further details see Section 3.5.4.

2.6.5. Audio Output Interface (SDO)

The audio output interface of the MAS 3504D is a

standard I

S interface. As the G.729 standard is only

working on mono signals, the same signal is written to

both output channels (left and right).

The interface is configurable by software to work in dif-

ferent modes. It is possible to choose:

– 16 or 32 bit/sample modes,

– inverted or noninverted word strobe (

SOI

– no delay or delay of data related to word strobe

– inverted or noninverted I

S-clock (

SOC

For further details see Section 3.5.4.

Table 2–2: PIO DMA Timing

Symbol

PIO Pin

Min.

Max.

Unit

PR, EOD

0.010

2000

PR, RTR

160

PR,

PI[19:12]

120

480

set

PI[19:12]

160

no limit

PI[19:12]

160

no limit

rtrq

RTR

200

30000

120

no limit

rpr

PR, RTR

no limit

eod

PR, EOD

160

eodq

EOD

500

ADVANCE INFORMATION

MAS 3504D

Micronas

2.6.5.1. Example 1:16 Bits/Sample

S Compatible Data Format)

A schematic timing diagram of the SDO interface in 16

bit/sample mode with delayed data by 1 clock cycle is

shown in Fig. 2–5.

Fig. 2–5: Schematic timing of the SDO interface in 16bit/sample mode

2.6.5.2. Example 2:32 Bit/Sample (Inverted SOI)

If the serial output generates 32 bits per audio sample,

only the first 20 bits will carry valid audio data. The 12

trailing bits are set to zero by default (see Fig. 2–6).

Fig. 2–6: Schematic timing of the SDO interface in 32 bit/sample mode

SOC

SOD

SOI

left 16-bit audio sample

right 16-bit audio sample

15 14 13 12 11 10 9

13 12 11 10

9 8

15 14

30 29 28 27 26 25 ... 7

31 30 29 28 27 26 25

left 32-bit audio sample

right 32-bit audio sample

SOC

SOD

SOI

...