800BG-L_BGH-L(TSOP,CSP)

- 1 -

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,

etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

LH28F800BG-L/BGH-L

(FOR TSOP, CSP)

8 M-bit (512 kB x 16) SmartVoltage

Flash Memories

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

DESCRIPTION

The LH28F800BG-L/BGH-L flash memories with

SmartVoltage technology are high-density, low-cost,

nonvolatile, read/write storage solution for a wide

range of applications. The LH28F800BG-L/BGH-L

can operate at V

= 2.7 V and V

= 2.7 V. Their

low voltage operation capability realizes longer

battery life and suits for cellular phone application.

Their boot, parameter and main-blocked

architecture, flexible voltage and enhanced cycling

capability provide for highly flexible component

suitable for portable terminals and personal

computers. Their enhanced suspend capabilities

provide for an ideal solution for code + data storage

applications. For secure code storage applications,

such as networking, where code is either directly

executed out of flash or downloaded to DRAM, the

LH28F800BG-L/BGH-L offer two levels of protection

: absolute protection with V

at GND, selective

hardware boot block locking. These alternatives

give designers ultimate control of their code security

needs.

FEATURES

• SmartVoltage technology

– 2.7 V, 3.3 V or 5 V V

– 2.7 V, 3.3 V, 5 V or 12 V V

• High performance read access time

LH28F800BG-L85/BGH-L85

– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)/

100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)

LH28F800BG-L12/BGH-L12

– 120 ns (5.0±0.5 V)/130 ns (3.3±0.3 V)/

150 ns (2.7 to 3.6 V)

• Enhanced automated suspend options

– Word write suspend to read

– Block erase suspend to word write

– Block erase suspend to read

• Enhanced data protection features

– Absolute protection with V

= GND

– Block erase/word write lockout during power

transitions

– Boot blocks protection with WP# = V

• SRAM-compatible write interface

• Optimized array blocking architecture

– Two 4 k-word boot blocks

– Six 4 k-word parameter blocks

– Fifteen 32 k-word main blocks

– Top or bottom boot location

• Enhanced cycling capability

– 100 000 block erase cycles

• Low power management

– Deep power-down mode

– Automatic power saving mode decreases I

in static mode

• Automated word write and block erase

– Command user interface

– Status register

• ETOX

∗

V nonvolatile flash technology

• Packages

– 48-pin TSOP Type I (TSOP048-P-1220)

Normal bend/Reverse bend

– 48-ball CSP (FBGA048-P-0808)

∗

ETOX is a trademark of Intel Corporation.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 2 -

PIN CONNECTIONS

GND

CE#

OE#

WP#

WE#

RP#

GND

RY/BY#

(FBGA048-P-0808)

48-BALL CSP

48-PIN TSOP (Type I)

(TSOP048-P-1220)

WE#

RP#

WP#

RY/BY#

GND

OE#

GND

CE#

VERSIONS

OPERATING

PACKAGE

DC CHARACTERISTICS

WRITE PROTECT FUNCTION

TEMPERATURE

deep power-down current (MAX.)

FOR BOOT BLOCKS

LH28F800BG-L

0 to +70°C

48-pin TSOP (I)

10 µA

Controlled by

(FOR TSOP, CSP)

48-ball CSP

WP# and RP# pins

LH28F800BGH-L

–40 to +85°C

48-pin TSOP (I)

20 µA

Controlled by

(FOR TSOP, CSP)

48-ball CSP

WP# and RP# pins

LH28F800BG-L

∗

0 to +70°C

44-pin SOP

10 µA

Controlled by RP# pin

(FOR SOP)

COMPARISON TABLE

∗

1 Refer to the datasheet of LH28F800BG-L (FOR SOP).

NOTE :

Reverse bend available on request.

TOP VIEW

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

BLOCK ORGANIZATION

This product features an asymmetrically-blocked

architecture providing system memory integration.

Each erase block can be erased independently of

the others up to 100 000 times. For the address

locations of the blocks, see the memory map in

Fig. 1.

Boot Blocks : The two boot blocks are intended to

replace a dedicated boot PROM in a micro-

processor or microcontroller-based system. The

boot blocks of 4 k words (4 096 words) feature

hardware controllable write-protection to protect the

crucial microprocessor boot code from accidental

modification. The protection of the boot blocks is

controlled using a combination of the V

, RP# and

WP# pins.

Parameter Blocks : The boot block architecture

includes parameter blocks to facilitate storage of

frequently update small parameters that would

normally require an EEPROM. By using software

techniques, the byte-rewrite functionality of

EEPROMs can be emulated. Each boot block

component contains six parameter blocks of 4 k

words (4 096 words) each. The parameter blocks

are not write-protectable.

Main Blocks : The reminder is divided into main

blocks for data or code storage. Each 8 M-bit

device contains fifteen 32 k words (32 768 words)

blocks.

- 3 -

INPUT

BUFFER

OUTPUT

MULTIPLEXER

CE#

RP#

OE#

IDENTIFIER

COMMAND

USER

INTERFACE

WRITE

STATE

MACHINE

PROGRAM/ERASE

VOLTAGE SWITCH

I/O

LOGIC

STATUS

DATA

COMPARATOR

32 k-WORD

MAIN BLOCKS

DECODER

Y GATING

RY/BY#

GND

-A

INPUT

BUFFER

ADDRESS

LATCH

ADDRESS

COUNTER

BOOT BLOCK 0

BOOT BLOCK 1

PARAMETER BLOCK 0

PARAMETER BLOCK 1

PARAMETER BLOCK 2

PARAMETER BLOCK 3

PARAMETER BLOCK 4

PARAMETER BLOCK 5

MAIN BLOCK 0

MAIN BLOCK 1

MAIN BLOCK 13

MAIN BLOCK 14

WP#

WE#

OUTPUT

-DQ

BLOCK DIAGRAM

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 4 -

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

-A

INPUT

ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses

are internally latched during a write cycle.

DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs

data during memory array, status register and identifier code read cycles. Data pins float

to high-impedance when the chip is deselected or outputs are disabled. Data is

internally latched during a write cycle.

CE#

INPUT

CHIP ENABLE : Activates the device’s control logic, input buffers, decoders and sense

amplifiers. CE#-high deselects the device and reduces power consumption to standby

levels.

RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets

internal automation. RP#-high enables normal operation. When driven low, RP# inhibits

write operations which provide data protection during power transitions. Exit from deep

power-down sets the device to read array mode. With RP# = V

, block erase or word

write can operate to all blocks without WP# state. Block erase or word write with V

RP# < V

produce spurious results and should not be attempted.

OE#

INPUT

OUTPUT ENABLE : Gates the device’s outputs during a read cycle.

WE#

INPUT

WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of the WE# pulse.

WP#

INPUT

WRITE PROTECT : Master control for boot blocks locking. When V

, locked boot

blocks cannot be erased and programmed.

READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is

performing an internal operation (block erase or word write). RY/BY#-high indicates that

the WSM is ready for new commands, block erase is suspended, and word write is

inactive, word write is suspended, or the device is in deep power-down mode. RY/BY#

is always active and does not float when the chip is deselected or data outputs are

disabled.

SUPPLY

BLOCK ERASE AND WORD WRITE POWER SUPPLY : For erasing array blocks or

writing words. With V

≤

PPLK

, memory contents cannot be altered. Block erase and

word write with an invalid V

(see Section 6.2.3 "DC CHARACTERISTICS") produce

spurious results and should not be attempted.

DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or

5 V operation. To switch from one voltage to another, ramp V

down to GND and then

ramp V

to the new voltage. Do not float any power pins. With V

≤

LKO

, all write

attempts to the flash memory are inhibited. Device operations at invalid V

voltage

(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should

not be attempted.

GND

SUPPLY

GROUND : Do not float any ground pins.

NO CONNECT : Lead is not internal connected; recommend to be floated.

-DQ

INPUT/

OUTPUT

RP#

INPUT/

RY/BY#

OUTPUT

SUPPLY

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

1 INTRODUCTION

This datasheet contains LH28F800BG-L/BGH-L

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4 and 5 describe the

memory organization and functionality. Section 6

covers electrical specifications. LH28F800BG-L/

BGH-L flash memories documentation also includes

ordering information which is referenced in

Section 7.

1.1

New Features

Key enhancements of LH28F800BG-L/BGH-L

SmartVoltage flash memories are :

• SmartVoltage Technology

• Enhanced Suspend Capabilities

• Boot Block Architecture

Note following important differences :

• V

PPLK

has been lowered to 1.5 V to support

2.7 V, 3.3 V and 5 V block erase and word

write operations. Designs that switch V

off

during read operations should make sure that

the V

voltage transitions to GND.

• To take advantage of SmartVoltage technology,

allow V

connection to 2.7 V, 3.3 V or 5 V.

1.2

Product Overview

The LH28F800BG-L/BGH-L are high-performance

8 M-bit SmartVoltage flash memories organized as

512 k-word of 16 bits. The 512 k-word of data is

arranged in two 4 k-word boot blocks, six 4 k-word

parameter blocks and fifteen 32 k-word main blocks

which are individually erasable in-system. The

memory map is shown in Fig. 1.

SmartVoltage technology provides a choice of V

and V

combinations, as shown in Table 1, to

meet system performance and power expectations.

2.7 V V

consumes approximately one-fifth the

power of 5 V V

and 3.3 V V

consumes

approximately one-fourth the power of 5 V V

But, 5 V V

provides the highest read

performance. V

at 2.7 V, 3.3 V and 5 V

eliminates the need for a separate 12 V converter,

while V

PP =

12 V maximizes block erase and word

write performance. In addition to flexible erase and

program voltages, the dedicated V

pin gives

complete data protection when V

≤

PPLK

Table 1 V

and V

Voltage Combinations

Offered by SmartVoltage Technology

Internal V

and V

detection circuitry auto-

matically configures the device for optimized read

and write operations.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal operation of the device. A valid command

sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for block erase and word write

operations.

A block erase operation erases one of the device’s

32 k-word blocks typically within 0.39 second (5 V

, 12 V V

), 4 k-word blocks typically within

0.25 second (5 V V

, 12 V V

) independent of

other blocks. Each block can be independently

erased 100 000 times. Block erase suspend mode

allows system software to suspend block erase to

read data from, or write data to any other block.

Writing memory data is performed in word

increments of the device’s 32 k-word blocks

typically within 8.4 µs (5 V V

, 12 V V

), 4 k-

word blocks typically within 17 µs (5 V V

, 12 V

). Word write suspend mode enables the

VOLTAGE

2.7 V

2.7 V, 3.3 V, 5 V, 12 V

3.3 V

3.3 V, 5 V, 12 V

5 V

5 V, 12 V

- 5 -

- 6 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

system to read data from, or write to any other

flash memory array location.

The boot block is located at either the top or the

bottom of the address map in order to

accommodate different micro-processor protect for

boot code location. The hardware-lockable boot

block provides complete code security for the

kernel code required for system initialization.

Locking and unlocking of the boot block is

controlled by WP# and/or RP# (see Section 4.9 for

details). Block erase or word write for boot block

must not be carried out by WP# to low and RP# to

The status register indicates when the WSM’s block

erase or word write operation is finished.

The RY/BY# output gives an additional indicator of

WSM activity by providing both a hardware signal

of status (versus software polling) and status

masking (interrupt masking for background block

erase, for example). Status polling using RY/BY#

minimizes both CPU overhead and system power

consumption. When low, RY/BY# indicates that the

WSM is performing a block erase or word write.

RY/BY#-high indicates that the WSM is ready for a

new command, block erase is suspended (and

word write is inactive), word write is suspended, or

the device is in deep power-down mode.

The access time is 85 ns (t

AVQV

) at the V

supply

voltage range of 4.75 to 5.25 V over the

temperature range, 0 to +70°C (LH28F800BG-L)/

– 40 to +85°C (LH28F800BGH-L). At 4.5 to 5.5 V

, the access time is 90 ns or 120 ns. At lower

voltage, the access time is 100 ns or 130 ns

(3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).

The Automatic Power Saving (APS) feature

substantially reduces active current when the

device is in static mode (addresses not switching).

In APS mode, the typical I

CCR

current is 1 mA at

5 V V

and 3 mA at 2.7 V and 3.3 V V

When CE# and RP# pins are at V

, the I

CMOS standby mode is enabled. When the RP#

pin is at GND, deep power-down mode is enabled

which minimizes power consumption and provides

write protection during reset. A reset time (t

PHQV

) is

required from RP# switching high until outputs are

valid. Likewise, the device has a wake time (t

PHEL

)

from RP#-high until writes to the CUI are

recognized. With RP# at GND, the WSM is reset

and the status register is cleared.

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

- 7 -

32 k-Word Main Block

7FFFF

78000

77FFF

6FFFF

70000

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

07000

06FFF

06000

05FFF

05000

04FFF

04000

03FFF

03000

02FFF

02000

01FFF

01000

00FFF

00000

4 k-Word Parameter Block

4 k-Word Boot Block

Bottom Boot

4 k-Word Boot Block

4 k-Word Parameter Block

32 k-Word Main Block

7FFFF

7F000

7EFFF

7DFFF

7E000

7D000

7CFFF

7C000

7BFFF

7B000

7AFFF

7A000

79FFF

79000

78FFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

00000

32 k-Word Main Block

Top Boot

Fig. 1 Memory Map

BLOCK CONFIGURATION

VERSIONS

Top Boot

LH28F800BG-TL

LH28F800BGH-TL

Bottom Boot

LH28F800BG-BL

LH28F800BGH-BL

NOTES :

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

2 PRINCIPLES OF OPERATION

The LH28F800BG-L/BGH-L SmartVoltage flash

memories include an on-chip WSM to manage

block erase and word write functions. It allows for :

100% TTL-level control inputs, fixed power supplies

during block erasure and word write, and minimal

processor overhead with RAM-like interface timings.

After initial device power-up or return from deep

power-down mode (see Table 2 "Bus Operations"),

the device defaults to read array mode.

Manipulation of external memory control pins allow

array read, standby and output disable operations.

Status register and identifier codes can be

accessed through the CUI independent of the V

voltage. High voltage on V

enables successful

block erasure and word writing. All functions

associated with altering memory contents—block

erase, word write, status and identifier codes—are

accessed via the CUI and verified through the

status register.

Commands are written using standard micro-

processor write timings. The CUI contents serve as

input to the WSM, which controls the block erase

and word write. The internal algorithms are

regulated by the WSM, including pulse repetition,

internal verification and margining of data.

Addresses and data are internally latched during

write cycles. Writing the appropriate command

outputs array data, accesses the identifier codes or

outputs status register data.

Interface software that initiates and polls progress

of block erase and word write can be stored in any

block. This code is copied to and executed from

system RAM during flash memory updates. After

successful completion, reads are again possible via

the Read Array command. Block erase suspend

allows system software to suspend a block erase to

read/write data from/to blocks other than that which

is suspended. Word write suspend allows system

software to suspend a word write to read data from

any other flash memory array location.

2.1

Data Protection

Depending on the application, the system designer

may choose to make the V

power supply

switchable (available only when memory block

erases or word writes are required) or hardwired to

PPH1/2/3

. The device accommodates either design

practice and encourages optimization of the

processor-memory interface.

When V

≤

PPLK

, memory contents cannot be

altered. The CUI, with two-step block erase or word

write command sequences, provides protection

from unwanted operations even when high voltage

is applied to V

. All write functions are disabled

when V

is below the write lockout voltage V

LKO

or when RP# is at V

. The device’s boot blocks

locking capability for WP# provides additional

protection from inadvertent code or data alteration

by block erase and word write operations.

3 BUS OPERATION

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

3.1

Read

Information can be read from any block, identifier

codes or status register independent of the V

voltage. RP# can be at either V

or V

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes or

Read Status Register) to the CUI. Upon initial

device power-up or after exit from deep power-

down mode, the device automatically resets to read

array mode. Five control pins dictate the data flow

in and out of the component : CE#, OE#, WE#,

RP# and WP#. CE# and OE# must be driven

active to obtain data at the outputs. CE# is the

- 8 -

- 9 -

LH28F800BG-L/BGH-L (FOR TSOP, CSP)

device selection control, and when active enables

the selected memory device. OE# is the data

output (DQ

-DQ

) control and when active drives

the selected memory data onto the I/O bus. WE#

must be at V

and RP# must be at V

or V

Fig. 11 illustrates read cycle.

3.2

Output Disable

With OE# at a logic-high level (V

), the device

outputs are disabled. Output pins (DQ

-DQ

) are

placed in a high-impedance state.

3.3

Standby

CE# at a logic-high level (V

) places the device in

standby mode which substantially reduces device

power consumption. DQ

-DQ

outputs are placed

in a high-impedance state independent of OE#. If

deselected during block erase or word write, the

device continues functioning, and consuming active

power until the operation completes.

3.4

Deep Power-Down

RP# at V

initiates the deep power-down mode.

In read modes, RP#-low deselects the memory,

places output drivers in a high-impedance state and

turns off all internal circuits. RP# must be held low

for a minimum of 100 ns. Time t