LH5496/96H CMOS 512 x 9 FIFO

LH5496/96H

CMOS 512

9 FIFO

FEATURES

••

Fast Access Times:

15 */20/25/35/50/65/80 ns

••

Full CMOS Dual Port Memory Array

••

Fully Asynchronous Read and Write

••

Expandable-in Width and Depth

••

Full, Half-Full, and Empty Status Flags

••

Read Retransmit Capability

••

TTL Compatible I/O

••

Packages:

28-Pin, 300-mil PDIP

28-Pin, 600-mil PDIP

32-Pin PLCC

••

Pin and Functionally Compatible with IDT7201

FUNCTIONAL DESCRIPTION

The LH5496/96H are dual port memories with internal

addressing to implement a First-In, First-Out algorithm.

Through an advanced dual port architecture, they provide

fully asynchronous read/write operation. Empty, Full, and

Half-Full status flags are provided to prevent data over-

flow and underflow. In addition, internal logic provides for

unlimited expansion in both word size and depth.

Read and write operations automatically access se-

quential locations in memory in that data is read out in the

same order that it was written, that is on a First-In,

First-Out basis. Since the address sequence is internally

predefined, no external address information is required

for the operation of this device. A ninth data bit is provided

for parity or control information often needed in commu-

nication applications.

Empty, Full, and Half-Full status flags monitor the

extent to which data has been written into the FIFO, and

prevent improper operations (i.e., Read if the FIFO is

empty, or Write if the FIFO is full). A retransmit feature

resets the Read address pointer to its initial position,

thereby allowing repetitive readout of the same data.

Expansion In and Expansion Out pins implement an

expansion scheme that allows individual FIFOs to be

cascaded to greater depth without incurring additional

latency (bubblethrough) delays.

PIN CONNECTIONS

5496-1D

FL/RT

XO/HF

28-PIN PDIP

TOP VIEW

Figure 1. Pin Connections for PDIP Packages

32 31 30

14 15 16

FL/RT

XO/HF

5496-2D

32-PIN PLCC

TOP VIEW

Figure 2. Pin Connections for PLCC Package

* LH5496 only.

PIN DESCRIPTIONS

PIN

PIN TYPE *

DESCRIPTION

– D

Input Data Bus

– Q

O/Z

Output Data Bus

Write Request

Read Request

Empty Flag

Full Flag

* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

PIN

PIN TYPE *

DESCRIPTION

XO/HF

Expansion Out/Half-Full Flag

Expansion In

FL/RT

First Load/Retransmit

Reset

Positive Power Supply

Ground

DATA OUTPUTS

- Q

FLAG

LOGIC

WRITE

POINTER

READ

POINTER

DATA INPUTS

- D

DUAL-PORT

RAM

ARRAY

512 x 9

. . .

5496-3

INPUT

PORT

CONTROL

RESET

LOGIC

OUTPUT

PORT

CONTROL

EXPANSION

LOGIC

XO/HF

FL/RT

Figure 3. LH5496/96H Block Diagram

LH5496/96H

CMOS 512

9 FIFO

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

Supply Voltage to V

Potential

–0.5 V to 7 V

Signal Pin Voltage to V

Potential

–0.5 V to V

+ 0.5 V (not to exceed 7 V)

DC Output Current

50 mA

Storage Temperature Range

–65

C to 150

Power Dissipation (Package Limit)

1.0 W

DC Voltage Applied To Outputs In High-Z State

–0.5 V to Vcc + 0.5 V (not to exceed 7 V)

NOTES:

Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device.

This is a device stress rating for transient conditions only. Functional operation at these or any other conditions above

those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.

Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.

OPERATING RANGE

SYMBOL

PARAMETER

MIN

MAX

UNIT

Temperature, Ambient, LH5496

Temperature, Ambient, LH5496H

– 40

Supply Voltage

4.5

5.5

Supply Voltage

Logic ‘0’ Input Voltage

–0 .5

0.8

Logic ‘1’ Input Voltage

2.0

+ 0.5

NOTE:

Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Input Leakage Current

= 5.5 V, V

= 0 V to V

–10

Output Leakage Current

≥

, 0 V

≤

OUT

≤

–10

Output High Voltage

= –2.0 mA

2.4

Output Low Voltage

= 8.0 mA

0.4

Average Supply Current

Measured at f = 40 MHz

100

CC2

Average Standby Current

All Inputs = V

CC3

Power Down Current

All Inputs = V

– 0.2 V

NOTE:

, I

CC2

, and I

CC3

are dependent upon actual output loading and cycle rates. Specified values are with outputs open.

CMOS 512

9 FIFO

LH5496/96H

AC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

SYMBOL

PARAMETER

= 15 ns

= 20 ns t

= 25 ns t

= 35 ns t

= 50 ns t

= 65 ns

= 80 ns

UNIT

MIN

MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN

MAX

MIN MAX

READ CYCLE TIMING

Read

Cycle

Time

–

– 35

– 45

–

– 80

–

100

–

Access Time

–

Read

Recover

Time

–

– 10

–

– 15

–

RPW

Read Pulse Width

–

20 – 25

–

– 65

–

RLZ

Data Bus Active from Read LOW

–

WLZ

Data Bus Active from Write

HIGH

4,5

–

– 10

–

– 10

–

Data Valid from Read Pulse HIGH

–

RHZ

Data Bus High-Z from Read

HIGH

–

WRITE CYCLE TIMING

Write Cycle Time

–

100

–

WPW

Write Pulse Width

–

– 25

–

– 80

–

Write

Recovery

Time

–

– 10

–

– 15

–

Data Setup Time

–

Data

Hold

Time

–

– 0

–

– 5

–

RESET TIMING

RSC

Reset Cycle Time

–

100

–

Reset Pulse Width

–

– 25

–

RSR

Reset Recovery Time

–

RRSS

Read HIGH to RS HIGH

–

WRSS

Write HIGH to RS HIGH

–

RETRANSMIT TIMING

RTC

Retransmit Cycle Time

–

– 35

– 45

–

100

–

Retransmit Pulse Width

–

– 25

– 35

–

RTR

Retransmit

Recovery

Time

–

– 10

–

FLAG TIMING

EFL

Reset LOW to Empty Flag LOW

–

100

HFH,FFH

Reset LOW to Half-Full and Full

Flags HIGH

–

100

REF

Read LOW to Empty Flag LOW

–

RFF

Read HIGH to Full Flag HIGH

–

WEF

Write HIGH to Empty Flag HIGH

–

WFF

Write LOW to Full Flag LOW

–

WHF

Write LOW to Half-Full Flag LOW

–

100

RHF

Read HIGH to Half-Full Flag HIGH

–

100

EXPANSION TIMING

XOL

Expansion Out LOW

–

XOH

Expansion Out HIGH

–

Expansion In Pulse Width

–

XIR

Expansion In Recovery Time

–

XIS

Expansion in Setup Time

–

NOTES:

LH5496 only.

All timing measurements performed at ‘AC Test Condition’ levels.

CMOS 512

9 FIFO

LH5496/96H

OPERATIONAL DESCRIPTION

Reset

The device is reset whenever the Reset pin (RS) is

taken to a LOW state. The reset operation initializes both

the read and write address pointers to the first memory

location. The XI and FL pins are also sampled at this time

to determine whether the device is in Single mode or

Depth Expansion mode. A reset pulse is required when

the device is first powered up. The Read (R) and Write

(W) pins may be in any state when reset is initiated, but

must be brought to a HIGH state t

RPW

and t

WPW

before

the rising edge of RS. The reset operation forces the

Empty Flag EF to be asserted (EF = LOW), and the

Half-Full Flag HF and the Full FLag FF to be deasserted

(HF = FF = HIGH); the Data Out pins (D

– D

) are forced

into a high-impedance state.

Write

A write cycle is initiated on the falling edge of the Write

(W) pin. Data setup and hold times must be observed on

the data in (D

– D

) pins. A write operation is only possible

if the FIFO is not full, (i.e. the Full flag pin is HIGH). Writes

may occur independently of any ongoing read operta-

tions.

At the falling edge of the first write after the memory is

half filled, the Half-Full flag will be asserted (HF = LOW)

and will remain asserted until the difference between the

write pointer and read pointer indicates that the remaining

data in the device is less than or equal to one half the total

capacity of the FIFO. The Half-Full flag is deasserted

(HF = HIGH) by the appropriate rising edge of R.

The Full flag is asserted (FF = LOW) at the falling edge

of the write operation which fills the last available location

in the FIFO memory array. The Full flag will inhibit further

writes until cleared by a valid read. The Full flag is

deasserted (FF = HIGH) after the next rising edge of R

releases another memory location.