LH543611/21
FEATURES
••
Pin-Compatible and Functionally
Upwards-Compatible with Sharp LH5420 and
LH543601, but Deeper
••
Expanded Control Register that is Fully
Readable as well as Writeable
••
Fast Cycle Times: 18/20/25/30/35 ns
••
Improved Input Setup and Flag Out Timing
••
Two 512
×
36-bit FIFO Buffers (LH543611) or
Two 1024
×
36-bit FIFO Buffers (LH543621)
••
Full 36-bit Word Width
••
Selectable 36/18/9-bit Word Width on Port B;
Selection May be Changed Without Resetting
the BiFIFO
••
Programmable Byte-Order Reversal –
‘Big-Endian
↔
Little-Endian Conversion’
••
Independently-Synchronized (‘Fully-Asynchronous’)
Operation of Port A and Port B
••
‘Synchronous’ Enable-Plus-Clock Control at
Both Ports
••
R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
••
Synchronous Request/Acknowledge ‘Handshake’
Capability; Use is Optional
••
Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
••
Asynchronous Output Enables
••
Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
••
All Flags are Independently Programmable for
Either Synchronous or Asynchronous Operation
••
Almost-Full Flag and Almost-Empty Flag Have
Programmable Offsets
••
Mailbox Registers with Synchronized Flags
••
Data-Bypass Function
••
Data-Retransmit Function
••
Automatic Byte Parity Checking with
Programmable Parity Flag Latch
••
Programmable Byte Parity Generation
••
Programmable Byte, Half-Word, or Full-Word
Oriented Parity Operations
••
8 mA-I
OL
High-Drive Three-State Outputs with
Built-In Series Resistor
••
TTL/CMOS-Compatible I/O
••
Space-Saving PQFP and TQFP Packages
FUNCTIONAL DESCRIPTION
The LH543611 and LH543621 contain two FIFO buff-
ers, FIFO #1 and FIFO #2. These operate in parallel, but
in opposite directions, for bidirectional data buffering.
FIFO #1 and FIFO #2 each are organized as 512 or 1024
by 36 bits. The LH543611 and LH543621 are ideal either
for wide unidirectional applications or for bidirectional
data applications; component count and board area are
reduced.
The LH543611 and LH543621 have two 36-bit ports,
Port A and Port B. Each port has its own port-synchro-
nous clock, but the two ports may operate asynchro-
nously relative to each other. Data flow is initiated at a port
by the rising edge of the appropriate clock; it is gated by
the corresponding edge-sampled enable, request, and
read/write control signals. At the maximum operating
frequency, the clock duty cycle may vary from 40% to
60%. At lower frequencies, the clock waveform may be
quite asymmetric, as long as the minimum pulse-width
conditions for clock-HIGH and clock-LOW remain satis-
fied; the LH543611 and LH543621 are fully-static parts.
Conceptually, the port clocks CK
A
and CK
B
are free-
running, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ wave-
forms must be periodic. An ‘asynchronous’ mode of op-
e ration is p os sib le, in o ne o r bo th direc tio ns,
independently, if the appropriate enable and request in-
puts are continuously asserted, and enough aperiodic
‘clock’ pulses of suitable duration are generated by exter-
nal logic to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for
each
FIFO. Each of these flags may be independently pro-
grammed for either synchronous or asynchronous opera-
tion. Also, the Almost-Full and Almost-Empty flags are
programmable over the entire FIFO depth, but are auto-
matically initialized to eight locations from the respective
FIFO boundaries at reset. A data block of 512 (LH543611)
or 1024 (LH543621) or fewer words may be retransmitted
any desired number of times.
512
×
36
×
2 / 1024
×
36
×
2
Synchronous Bidirectional FIFO
BOLD = Additions over the 5420/3601 feature set
1
Two mailbox registers provide a separate path for
passing control words or status words between ports.
Each mailbox has a New-Mail-Alert Flag, which is syn-
chronized to the reading port’s clock. This mailbox func-
tion facilitates the synchronization of data transfers
between asynchronous systems.
Data-bypass mode allows Port A to directly transfer
data to or from Port B at reset. In this mode, the device
acts as a registered transceiver under the control of
Port A. For instance, a master processor on Port A can
use the data bypass feature to send or receive initializa-
tion or configuration information directly, to or from a
peripheral device on Port B, during system startup.
A word-width-select option is provided on Port B for
36-bit, 18-bit, or 9-bit data access. This feature allows
word-width matching between Port A and Port B, with no
additional logic needed. It also ensures maximum utiliza-
tion of bus band widths. Subject to meeting timing require-
ments, the word-width selection may be changed at any
time during the operation of an LH543611 or LH543621,
without the need either for a reset operation or for passing
dummy words through Port B immediately after the
change; except that if the change is not made at a
full-word boundary, at least one dummy word must be
passed through Port B before any actual data words
are transmitted.
A Byte Parity Check Flag at each port monitors data
integrity. Control-Register bit 00 (zero) selects the parity
mode, odd or even. This bit is initialized for odd data parity
at reset; but it may be reprogrammed for even parity, or
back again to odd parity, as desired. The parity flags may
be programmed to operate either in a latched mode or in
a flowthrough mode. The parity checking may be per-
formed over 36-bit full-words, over 18-bit half-words, or
over 9-bit single bytes.
Parity generation may be selected as well as parity
checking, and may likewise be performed over full-words
or half-words or single bytes. In any case, a parity bit of
the proper mode is generated over the least-significant
eight bits of a byte, and then is stored in the most-signifi-
cant bit position of the byte as it passes through the
LH543611/21, overwriting whatever bit was present in
that bit position previously.
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
2
