VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
Page 1
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
Applications
General Description
The VSC7969 is a 3.125Gb/s transimpedance amplifier IC with a built-in limiting amplifier, a signal detect
feature and a photocurrent monitor. The VSC7969 does not require any external electrical components in the
construction of a high performance optical receiver such as for SONET/SDH applications. The analog output is
a differential signal with a minimum amplitude of 200mVp-p (single-ended). The VSC7969 operates with a sin-
gle power supply with a maximum power dissipation of 300mW. A PIN photodiode or APD can be connected
and separately biased to provide optimal performance.
The VSC7969 provides filtered bias for MSM and PIN photodetectors; applications using an APD photode-
tector must supply bias separately. The VSC7969 also provides a photocurrent monitor whose output is linearly
proportional to the input photocurrent.
The VSC7969 can operate from a single +3.3V supply or a +5V or -5.2V supply. The VSC7969 is offered
in die form and in a 16-pin plastic thin-shrink small outline package (TSSOP-16). A fully tested TO-46 outline
packaged receiver with a photodetector is also available.
Block Diagram
• Integrated TIA and Limiting Amplifier
• Low Power Consumption for SFF Applications
• TO Package-Compatible Layout
• On-Chip Signal Detect
• On-Chip Linear Photocurrent Monitor
• Single 3.3V Supply
• 5V Supply Operation via Wirebond Option
• Compatible with PIN or Avalanche Detectors
• Packages: 16-Pin TSSOP, TO-46, Bare Die
50
Ω
Regulator
VSC7969
+3.3V
0.1µF
VOUTP
VCCD
Outputs need to
be AC-coupled
Dual power supply pins are
provided for +5V or +3.3V
operation. Only one power
supply pin should be connected.
VCCS
VOUTN
SD_OUT
SD_ADJ
IMON
0.1µF
+3.3V
+5V
50
Ω
Signal
Detect
Monitor
Filter
In
GND
• 2.488Gb/s, 3.125Gb/s SONET OC-48/
SDH STM-16
• 2.125Gb/s Fibre Channel
• 2.5Gb/s or 3.125Gb/s Ethernet Applications with
8B/10B Overhead
• SFF Transceivers
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 2
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Electrical Characteristics
Table 1: AC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Conditions
∆
I
PH
Input Photocurrent Swing
2.2
mA
Peak-to-peak AC current
amplitude
I
PHS-AVG
Average Photocurrent Sensitivity
4
µA
-23dBm average optical power
with a detector responsitivity of
0.8A/W.
I
PHS-PEAK
Peak Input Photocurrent Sensitivity
8
µA
-23dBm average optical power
with a detector responsitivity of
0.8A/W.
∆
V
OUT-SE
Single-Ended Output Voltage
Amplitude
200
250
300
mV
Single-ended peak-to-peak
measurement, I
IN
>20µA.
∆
V
OUT-DIFF
Differential Output Voltage Amplitude
400
500
600
mV
Differential peak-to-peak
measurement, I
IN
>20µA.
t
R
, t
F
Rise and Fall Time
60
100
ps
At 2.2mAp-p input photocurrent
swing. 20% to 80%.
Z
T
(1)
Transimpedance Gain
20k
27k
40k
Ω
Differential measurement
∆
Z
T
(1)
Ripple in Passband Transimpedance
1
dB
Modulation frequency between F
L
and BW
BW
Upper -3dB Bandwidth
2.2
2.5
3.0
GHz
Referenced to 10MHz,
CPD = 0.6pF
F
L
Lower -3dB Cutoff Frequency
100
kHz
Referenced to 10MHz, CPD =
0.6pF with no external
components
Z
O
Output Impedance
50
Ω
Single-ended
PSRR
Power Supply Rejection Ratio
TBD
I
NOISE
Input-Referred rms Noise Current
500
nA
30kHz to 2.5GHz
C
PD
Photodetector Capacitance
0.4
0.6
0.8
pF
Bias voltage on detector at 2.0V
SD
H
Signal Detect Hysterisis
1
2
4
dB
Electrical measurement on SD pin
SD
A-OPEN
Signal Detect Assertion Level
3
5
9
µA
Average photocurrent with SD
open.
SD
D-OPEN
Signal Detect Deasseration Level
1.0
2.2
3.0
µA
Average photocurrent with SD
open.
SD
A-SHORT
Signal Detect Asseration Level
6
10
18
µA
Average photocurrent with SD
shorted to ground.
SD
D-SHORT
Signal Detect Deasseration Level
2.0
4.4
6.0
µA
Average photocurrent with SD
shorted to ground.
SD
HIGH
Signal Detect HIGH Logic Level
V
CCS
- 0.3
V
SD
LOW
Signal Detect LOW Logic Level
0.5
0.8
V
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
Page 3
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
NOTES: (1) The transimpedance gain is defined as Z
T
= (
∆
V
OUT
- DIFF
)/
∆
I
PH
. (2) Using 1111100000 pattern at 2.5Gb/s to measure the
standard deviation of the edge of the pattern, multiply the standard deviation by 14 to achieve the total random jitter. (3) +K28.5
- K28.5 (00111110101100000101).
Table 2: DC Specifications
Absolute Maximum Ratings
(1)
(at T
A
= +25
°
C, unless otherwise specified)
Power Supply Voltage (V
CCS
)......................................................................................................................... 3.6V
Power Supply Voltage (V
CCD
) ........................................................................................................................ 5.5V
Junction Temperature Range ........................................................................................................ -40°C to +125°C
Storage Temperature Range ......................................................................................................... -40°C to +125°C
Relative Ambient Humidity ................................................................................................................. 85%/+85°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Supply (V
CCS
) ...................................................................................................................... 3.3V
Positive Voltage Supply (V
CCD
)...................................................................................................................... 5.0V
Negative Voltage Rail (GND) ............................................................................................................................ 0V
Ambient Temperature Range (T
A
)
(1)
.............................................................................................. -40°C to +85°C
MON
Slope of Linear Analog Photocurrent
Monitor vs Input Optical Power
0.8
µA/µW
0
Ω
to 2k
Ω
to V
CC
with a detector
responsitivity of 0.8A/W
DC
Duty Cycle
-5
+5
%
IMON
RANGE
Photocurrent Monitor Linearity Range
5
200
µA
IMON
OFFSET
Photocurrent Monitor Offset
0
10
µA
R
J
Random Jitter
(2)
TBD
ps
Peak-to-peak
D
J
Deterministic Jitter
(3)
TBD
ps
Peak-to-peak
Symbol
Parameter
Min
Typ
Max
Units
Conditions
GND
Negative Supply Rail
0
V
V
CCS
Positive Supply Rail for 3.3V Operation
3.0
3.3
3.6
V
V
CCD
Positive Supply Rail for 5V Operation
4.5
5.0
5.5
V
ICC
Power Supply Current
65
75
mA
3.3V
V
OUT-CM
Common-Mode Voltage on Output Pins
V
CCS
-
125mV
Applicable to VOUTP and
VOUTN pins at 50
Ω
load.
V
ANODE
Internal DC Bias Voltage on Detector
Anode Contact
0.8
0.9
1.0
V
V
CATHODE
Interal DC Bias Voltage on Detector
Cathode Contact
V
CCS
-
0.15V
V
CCS
V
V
CAT-EXT
External DC Bias Voltage Permissable
on Detector Cathode Contact
3.3
10
V
V
APD
External DC Bias Voltage for Use with
Avalanche Photodetector
60
V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 4
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Bare Die Descriptions
Figure 1: Pad Assignments
VSC7969
Die Size: 1143µm x 1453µm (45.0mil x 57.2mil)
Die Thickness: 279
µm (11.0mil)
Pad Size:
100µm x 100µm (3.9mil x 3.9mil)
Pad Passivation Opening:
86µm x 86µm (3.4mil x 3.4mil)
Scribe Size: 143µm (5.6mil)
Pad 7
SD_OUT
Pad 8
GND
Pad 9
VOUTN
Pad 10
GND
Pad 11
VOUTP
Pad 12
GND
Pad 13
IMON
Pad 14
VOUTP
Pad 15
GND
Pad 16
CSDN
Pad 17
CSDP
1143µm
(45.0mil)
1467µm (57.2mil)
143µm
(5.6mil)
Pad 18
GND
Pad 19
GND
Pad 5
SD_ADJ
Pad 4
SD_TP
Pad 3
GND
Pad 2
BG_VREF
Pad 1
GND
Pad 6
VOUTN
Pad 25
VCCS
Pad 24
GND
Pad 23
IN
Pad 22
FILTER
Pad 21
GND
Pad 20
GND
Pad 26
VCCD
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
Page 5
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Table 3: Pad Coordinates
Signal
Name
Pad
Number
Coordinates (µm)
Description
X
Y
GND
1
130
250
Negative power supply rail (typically 0V)
BG_VREF
2
130
375
Band Gap voltage reference 1.24V for testpoint, no connect
GND
3
130
500
Negative power supply rail (typically 0V)
SD_TP
4
130
625
Signal Detect test point, DO NOT CONNECT.
SD_ADJ
5
130
750
Signal Detect threshold adjustment (see Application amd Usage
section)
VOUTN
6
137
875
Complementary logic output (logic LOW when photocurrent is
HIGH)
SD_OUT
7
280
875
Signal detect output (logic HIGH when photocurrent exceeds
SD
A
)
GND
8
405
875
Negative power supply rail (typically 0V)
VOUTN
9
530
875
Complementary logic output (logic LOW when photocurrent is
HIGH)
GND
10
655
875
Negative power supply rail (typically 0V)
VOUTP
11
780
875
Positive logic output (logic HIGH when photocurrent is HIGH)
GND
12
905
875
Negative power supply rail (typically 0V)
IMON
13
1030
875
Photocurrent Monitor
VOUTP
14
1173
875
Positive logic output (logic HIGH when photocurrent is HIGH)
GMD
15
1180
750
Negative power supply rail (typically 0V)
CSDN
16
1180
625
Test point for Signal Detect capacitor. DO NOT CONNECT.
CSDP
17
1180
500
Test point for Signal Detect capacitor. DO NOT CONNECT.
GND
18
1180
375
Negative power supply rail (typically 0V)
GND
19
1180
250
Negative power supply rail (typically 0V)
GND
20
1030
125
Negative power supply rail (typically 0V)
GND
21
905
125
Negative power supply rail (typically 0V)
FILTER
22
780
125
Photodetector cathode connection (filtered V
CC
)
IN
23
530
125
Photodetector anode connection
GND
24
405
125
Negative power supply rail (typically 0V)
VCCS
25
280
125
Positive power supply rail for 3.3V operation
VCCD
26
137
125
Positive power supply rail for 5V operation
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 6
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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Package Pin Descriptions
Figure 2: Pin Diagram
Table 4: Pin Identifications
Pin Name
Pin No.
Description
VCC
1
Power Supply
GND
2
Ground
GND
3
Ground
IN
4
Photodetector Anode Connection
FILTER
5
Photodetector Cathode Connection (filtered V
CC
)
GND
6
Ground
GND
7
Ground
GND
8
Ground
IMON
9
Photocurrent Monitor
GND
10
Ground
GND
11
Ground
VOUTP
12
Positive Logic Output (logic HIGH when photocurrent is HIGH)
VOUTN
13
Complementary Logic Output (logic LOW when photocurrent is HIGH)
GND
14
Ground
SD_OUT
15
Signal Detect Output (logic HIGH when photocurrent exceeds SD
A
)
SD_ADJ
16
Signal Detect Threshold Adjustment (see Applications and Usage section)
1
2
3
4
5
6
7
8
VCC
GND
GND
IN
FILTER
GND
GND
GND
SD_ADJ
SD_OUT
GND
VOUTN
VOUTP
GND
GND
IMON
16
15
14
13
12
11
10
9
VSC7969
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Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
Page 7
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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Typical Operating Characteristics
Electrical Eye Diagram,
Input = 8µAp-p, 3.125Gb/s, PRBS 2
31
-1
T
A
= º+25C, V
CC
= 3.3V
Electrical Eye Diagram,
Input = 100µAp-p, 3.125Gb/s, PRBS 2
31
-1
T
A
= º+25C, V
CC
= 3.3V
Bit Error Rate vs Input Level
IMON Characteristic,
0µA to 200µA Input
1.00E-07
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
1.00E-13
6.0
6.5
7.0
7.5
IN (I
PD
) (
µ
Ap-p)
BIT ERROR RATE vs INPUT LEVEL
8.0
8.5
Bitt Eorr Rate (BER)
250
200
150
100
50
0
0
50
100
IN (DC Current) (
µ
A)
I
MON
CHARACTERISTIC
0
µ
A to 200
µ
A Input
150
200
I
MON
(
µ
A)
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 8
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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Circuit Description
The VSC7969 data path consists of several stages: transimpedance input stage, limiting amplifier, and out-
put driver. The transimpedance amplifier accepts current from a photodetector connected to the input pad ‘IN’
and converts the input current to a differential output voltage. The signal then travels to the second stage limit-
ing amplifier which provides DC restoration, eliminating the DC component of the input signal. The linear pho-
tocurrent monitor and signal detect function is also provided by this stage. The final stage consists of an output
driver with a differential pair connected to V
CC
via 50
Ω
internal pull-up resistors. The overall effective differ-
ential transimpedance of the VSC7969 is typically 27k
Ω
. The limited output single-ended voltage swing is typ-
ically 250mVp-p.
Design Guidelines
Power Supply
The VSC7969 is supplied by a single supply voltage; for +3.3V operation, the supply votlage should be
applied to only V
CCS
. For +5V operation, the supply voltage should be applied to only V
CCD
.
Data Outputs
The outputs of the VSC7969 need to be AC-coupled. This capacitor will determine the low frequency cut-
off for the system, which is directly related to the receiver’s deterministic jitter. For ATM/SONET or other
applications using PRBS NRZ data, select a capacitor of at least 0.1µF or greater, which provides less than
32kHz low frequency cutoff. For Fibre Channel, Gigabit Ethernet, or other applications requiring 8B/10B data
coding, select a capacitor of at least 0.01µF or greater, which provides less than 320kHz low frequency cutoff.
The outputs can be used single-ended or differential. For best performance, differential operation is recom-
mended. If single-ended operation is necessary, the unused output should be AC-coupled and terminated with
an impedance equal to the load on the pin in use.
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
Page 9
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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Signal Detect
The signal detect feature of the VSC7969 provides a CMOS level output corresponding to the input current
level to the transimpedance amplifier. The assert and deassert levels of the signal detect pin can be adjusted by
placing an optional resistor from SD_ADJ to ground. The following tables show the two extremes at which the
signal detect pin will operate; open circuit and short-ciruit to ground.
Table 5: Signal Detect Function, SD_ADJ Open
With SD_ADJ (pin 16) shorted to ground, thresholds are 3dB higher, as shown in Table 6.
Table 6: Signal Detect Function, SD_ADJ Shorted to Ground
Photodetector Current Monitor
The IMON pin provides a linear measurement of the average input current from the photodetector to the
transimpedance amplifier. For example, if 20µA is the average input current to the transimpedance amplifier,
the current through the IMON pin will be 20µA (see the typical operating curve “IMON Characteristic, 0µA to
200µA). To use this feature, connect the IMON pin to V
CC
using a resistor less than 2k
Ω
. If this feature is not
used, the IMON pin can be left unconnected.
Electrical
Min
Typ
Max
Units
Assert
3
5
9
µA
Deassert
1
2.2
3
µA
Hysteresis
1
2
4
dB
Electrical
Min
Typ
Max
Units
Assert
6
10
18
µA
Deassert
2
4.4
6
µA
Hysteresis
1
2
4
dB
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SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 10
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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Application Information
GND
VCC
VOUTP
IMON
NOTES:
No external components required.
Unused output is AC-coupled and terminated to 50
Ω
.
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SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
Page 11
02/09/01
© VITESSE
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Package Information
TSSOP-16
1. All dimensioning and tolerancing per ASME. Y14.5-1994
2. Controlling dimension: millimeter
3. This outline conforms to JEDEC Publication 95 Registration MS-026
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Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 12
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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TO-46 Ball Lens Package
1. Controlling dimenstion: millimeter
TOP VIEW
SIDE VIEW
Reference Isometric
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Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
G52355-0, Rev 2.0
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02/09/01
© VITESSE
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TO-46 Flat Window Package
1. Controlling dimension: millimeter
TOP VIEW
Reference Isometric
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Advance Product Information
VSC7969
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Page 14
G52355-0, Rev 2.0
02/09/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (8