VITESSE
SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
Page 1
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Features
General Description
The VSC7212 is an 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth
interconnection between busses, backplanes, or other subsystems. A Fibre Channel and Gigabit Ethernet
compliant transceiver provides up to 2.18Gb/s of duplex raw data transfer. The VSC7212 can operate at a
maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at 98MHz).
The VSC7212 contains an 8B/10B encoder, serializer, de-serializer, 8B/10B decoder and elastic buffer which
provide the user with a simple interface for transferring data serially and recovering it on the receive side. The
device can also be configured to operate as a non-encoded 10-bit transceiver with redundant I/O.
VSC7212 Block Diagram
• ANSI X3T11 Compliant Fibre Channel and IEEE
802.3z Compliant Gigabit Ethernet Transceiver
• Over 2Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• 8B/10B Encoder/Decoder, Optional Encoder/
Decoder Bypass Operation
• “ASIC-Friendly
TM
” Timing Options for Transmit-
ter Parallel Input Data
• Elastic Buffer for Chip-to-Chip Cable Deskewing
• Tx/Rx Rate Matching via IDLE Insertion/Deletion
• Compatible with VSC7211, VSC7214 and
VSC7216
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• PECL Rx Signal Detect and Cable Equalization
• Serial Tx-to-Rx and Parallel Rx-to-Tx Internal
Loopback Modes
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 1.0 W
• 100-pin, 14mm TQFP package
x20/x10
Clock Gen
Tx Clock
ENDEC
RESETN
WSI
DUAL
Channel
Align
WSO
TBC
KCHAR
10
Encode
8B/10B
D Q
T(7:0)
C/D
8
8
PTX-
PTX+
RTX-
RTX+
WSEN
RTXEN
PTXEN
PRX-
PRX+
RRX-
RRX+
RXP/R
LBEN(1:0)
Recovery
Clk/Data
Decode
8B/10B
10
Buffer
Elastic
3
8
IDLE
ERR
R(7:0)
KCH
8
RCLKN
RCLK
REFCLKP
REFCLKN
REFCLK
TBERR
TMODE(2:0)
FLOCK
TMS
TRSTN
TDI
TCK
TDO
Boundary
JTAG
Scan
RMODE(1:0)
CAP0 CAP1
TRANSMITTER
RECEIVER
BIST
LBTX
RSDET
PSDET
REFOUT
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VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 2
G52268-0, Rev 3.3
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Notation
Differential signals (i.e., PTX+ and PTX-) may be referred to as a single signal (i.e., PTX) by dropping
reference to the “+” and “- ”. REFCLK refers to the single-ended TTL or differential PECL input pair
REFCLKP/REFCLKN, whichever is used.
Clock Synthesizer
Depending on the state of the DUAL input, the VSC7212 clock synthesizer multiplies the reference
frequency provided on the REFCLK input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud
rate clock between 0.98GHz and 1.36GHz. The on-chip PLL uses a single external 0.1µF capacitor, connected
between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer ceramic dielectric,
or better, with at least a 5V working voltage rating and a good temperature coefficient; NPO is preferred but
X7R may be acceptable. These capacitors are used to minimize the impact of common-mode noise on the Clock
Multiplier Unit, especially power supply noise. Higher value capacitors provide better robustness in systems.
NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity will vary with
temperature. For best noise immunity, the designer may use a three capacitor circuit with one differential
capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to
ground, C3. Larger values are better but 0.1µF is adequate. However, if the designer cannot use a three capacitor
circuit, a single differential capacitor, C1, is adequate. These components should be isolated from noisy traces.
Figure 1: Loop Filter Capacitors (Best Circuit)
The REFCLK signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL
input to REFCLKP but leave REFCLKN open. If LVPECL, connect the inputs to REFCLKP and REFCLKN.
Internal biasing resistors sets the proper DC Level to V
DD
/2.
CAP0
CAP1
C1
C2
C3
VSC7216
C1=C2=C3= >0.1µF
MultiLayer Ceramic
Surface Mount
NPO (Preferred) or X7R
5V Working Voltage Rating
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SEMICONDUCTOR CORPORATION
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SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
Page 3
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Transmitter Functional Description
Transmitter Data Bus
The VSC7212 transmitter has an 8-bit input transmit data character, T(7:0), and two control inputs, C/D and
WSEN. The C/D input determines whether a normal data character or a special “K-character” is transmitted,
and the WSEN input initiates transmission of a 16-character “Word Sync Sequence” used to align the receiver.
These data and control inputs are clocked either on the rising edge of REFCLK, on the rising edge of TBC, or
within the data eye formed by TBC (“ASIC-Friendly” timing). The transmit interface mode is controlled by
TMODE(2:0) as shown in Table 1.
When used, TBC must be frequency locked to REFCLK. No phase relationship is assumed. A small skew
buffer is provided to tolerate phase drift between TBC and REFCLK. This buffer is recentered by the RESETN
input, and the total phase drift after recentering must be limited to +/- 180× (where 360× is one character time).
The VSC7212 has an error output, TBERR, that is asserted HIGH to indicate that the phase drift between TBC
and REFCLK has accumulated to the point that the elastic limit of the skew buffer has been exceeded and a
transmit data character has been either dropped or duplicated. This error can not occur when input timing is
referenced to REFCLK. The TBERR output timing is identical to the low-speed receiver outputs, as selected by
RMODE(1:0) in Table 5.
Table 1: Transmit Interface Input Timing Mode
The following figures show the possible relationships between data and control inputs and the selected
input timing source. Figure 2 shows how REFCLK is used as an input timing reference. This mode of operation
is also used in the VSC7211 and VSC7214. Figure 3 and Figure 4 show how TBC is used as an input timing
reference. When TBC is used to define a data eye as shown in Figure 4, it functions as an additional data input
that simply toggles every cycle.
Note that the REFCLK and TBC inputs are not used directly to clock the input data. Instead, an internal
PLL generates edges aligned with the appropriate clock. The arrows on the rising edges of these signals define
the reference edge for the internal phase detection logic. An internal clock is generated at 1/10 the serial
transmit data rate that is locked to the selected input timing source. This is an especially important issue when
DUAL is HIGH and input timing is referenced to REFCLK, since the falling edge is NOT used. The internal
clock active edges are placed coincident with the REFCLK rising edges and halfway between the REFCLK
rising edges in this mode.
TMODE(2:0)
Input Timing Reference
0 0 0
REFCLK Rising Edge
0 0 1
0 1 X
Reserved
1 0 X
TBC Rising Edge
1 1 X
TBC Data Eye
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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 4
G52268-0, Rev 3.3
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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A similar situation exists when TBC is used to define a data eye; only the rising edges of TBC are used to
define the external data timing. The internal clock active edges are placed at 90× and 270× points between
consecutive TBC rising edges (which are assumed to be 360× apart).
Figure 2: Transmit Timing, TMODE(2:0) = 000
Figure 3: Transmit Timing, TMODE(2:0) = 10X
Figure 4: Transmit Timing, TMODE(2:0) = 11X (“ASIC-Friendly” Timing)
REFCLK
(DUAL = 0)
Valid
C/D
Valid
Valid
T(7:0)
WSEN
REFCLK
(DUAL = 1)
Valid
C/D
Valid
Valid
T(7:0)
WSEN
TBC
Valid
C/D
Valid
Valid
T(7:0)
WSEN
TBC
0
o
90
o
180
o
270
o
360
o
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SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
Page 5
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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8B/10B Encoder
The VSC7212 contains an 8B/10B encoder which translates the 8-bit input data on T(7:0) into a 10-bit
encoded data character. A C/D input is also provided which, along with KCHAR, allow the transmission of
special Fibre Channel Kxx.x characters (see Table 2). Note that KCHAR is a static input, and does NOT have
the same input timing as T(7:0), C/D and WSEN. Normally C/D is LOW in order to transmit data. If C/D is
HIGH and KCHAR is LOW, then a Fibre Channel defined IDLE Character (K28.5 = ‘0011111010’ or
‘1100000101’ depending on disparity) is transmitted and T(7:0) is ignored. If C/D is HIGH and KCHAR is
HIGH, a Kxx.x character is transmitted as determined by the data on T(7:0) (see Table 3). Data patterns other
than those defined in Table 3 produce undefined 10B encodings.
Table 2: Transmit Data Controls
Table 3: Special Characters (Selected when C/D and KCHAR are HIGH)
Encoder Bypass Mode
When ENDEC is LOW the 8B/10B encoder is bypassed and a 10-bit input character T(7:0) is serialized
onto PTX/RTX with bit T0 is transmitted first. The C/D input becomes T8, and WSEN becomes T9. The
KCHAR input becomes ENCDET which is not used in the transmitter, but when HIGH, enables “Comma”
detection in the receiver. Refer to the “Decoder Bypass Mode” section for a description of this mode of
operation in the receiver. The latency through the transmitter is reduced by one character time when ENDEC is
LOW. This mode of operation is similar to a 10-bit interface commonly found in serializer/deserializers for the
Fibre Channel (e.g., VSC7125) and Gigabit Ethernet markets (e.g., VSC7135).
WSEN
C/D
KCHAR
Encoded 10-bit Output
0
0
X
Data Character
0
1
0
IDLE Character (K28.5)
0
1
1
Special Kxx.x Character
1
X
X
16-Character Word Sync Sequence
Code
T(7:0)
Comment
Code
T(7:0)
Comment
K28.0
000 11100
User Defined
K28.6
110 11100
User Defined
K28.1
001 11100
User Defined
K28.7
111 11100
Test Only
K28.2
010 11100
User Defined
K23.7
111 10111
User Defined
K28.3
011 11100
User Defined
K27.7
111 11011
User Defined
K28.4
100 11100
User Defined
K29.7
111 11101
User Defined
K28.5
101 11100
IDLE
K30.7
111 11110
User Defined
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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 6
G52268-0, Rev 3.3
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Word Sync Generation
The VSC7212 can perform chip-to-chip alignment (also referred to as “word alignment” or “word sync”),
meaning that the receive data output streams from multiple chips are aligned such that the same n-byte word
presented to the n transmit channels for serialization will be transferred on the receive channel parallel outputs.
The Word Sync Sequence provides a unique synchronization point in the serial data stream that is used to align
the receive channels. This sequence consists of 16 consecutive K28.5 IDLE characters with disparity reversals
on the second and fourth characters. The Word Sync Sequence is sent either as “I+ I+ I- I- I+ I- I+ I- I+ I- I+ I-
I+ I- I+ I-” or as “I- I- I+ I+ I- I+ I- I+ I- I+ I- I+ I- I+ I- I+”, depending on the transmitter’s running disparity at
the time the first IDLE character is serialized.
Transmission of the Word Sync Sequence is initiated when the WSEN input is asserted HIGH for one
character time (see Figure 5). When WSEN is HIGH, the C/D and T(7:0) inputs are ignored. The WSEN, C/D
and T(7:0) inputs are also ignored for the subsequent 15 character times. In Figure 5, the Word Sync Sequence
is initiated in cycle W1 and transmitted through cycle W16. Normal data transmission (or the transmission of
another Word Sync Sequence) resumes in cycle D3. This figure is drawn assuming that input timing is
referenced to REFCLK (e.g. TMODE(2:0)=000) with the DUAL input LOW. As long as WSEN remains
asserted, another Word Sync Sequence will be generated.
Figure 5: Word Sync Sequence Generation
Serializer
The 10-bit output from the encoder (or from the skew buffer if ENDEC is LOW) is fed into a multiplexer
which serializes the parallel data using the synthesized transmit clock. The least significant bit of the 10B data is
transmitted first. The VSC7212 has both primary and redundant serial output ports, PTX and RTX, respectively,
which consist of differential PECL output buffers operating at either 10 or 20 times the REFCLK rate. The
primary and redundant transmitter outputs are separately controllable. The primary PECL outputs PTX are
enabled when the PTXEN input is HIGH, and the redundant PECL outputs RTX are enabled when the RTXEN
input is HIGH. When a PECL output is disabled, the associated output buffers do not consume power and the
attached pins are un-driven.
REFCLK
WSEN
C/D
T(7:0)
0x02
0x01
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
0x04
0x03
D2
D1
W2
W1
W4
W3
W6
W5
W8
W7
W10
W9
W12
W11
W14
W13
W16
W15
D4
D3
TX+/-
D2.0+
D1.0+
K28.5+
K28.5+
K28.5-
K28.5-
K28.5-
K28.5+
K28.5-
K28.5+
K28.5-
K28.5+
K28.5-
K28.5+
K28.5-
K28.5+
K28.5-
K28.5+
D4.0-
D3.0+
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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
Page 7
04/10/01
© VITESSE
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Receiver Functional Description
Serial Data Source
The receiver has both primary and redundant serial input ports, PRX and RRX, respectively, which consist
of differential PECL input buffers. It also has a control input, RXP/R, used to select either the primary or
redundant serial input as the data source. When RXP/R is HIGH, the serial data source is PRX. When
LBEN(1:0)=10, the transmitter is looped back and becomes the serial data source regardless of the state of
RXP/R (see Table 4).
Table 4: Serial Data Source Selection
Signal Detection
The primary and redundant PECL input buffers have an associated signal detect output, PSDET and
RSDET. Both outputs are available for continuous monitoring of the selected and non-selected input. Each
signal detect output is asserted HIGH when transitions are detected on the associated PECL input and the signal
amplitude exceeds 200mV. A LOW indicates that either no transitions are detected or the signal amplitude is
below 100mV. The signal detect outputs are considered undefined when the signal amplitude is in the 100mV to
200mV range. The signal detect circuitry behaves like a re-triggerable one shot that is triggered by signal
transitions, and whose time-out interval ranges from 40 to 80 bit times. The transition density is not checked to
make sure that it corresponds to a valid Fibre Channel data stream. The PSDET and RSDET output timing is
identical to the low-speed receiver outputs, as selected by RMODE(1:0) in Table 5.
Receiver Equalization
Incoming data on the PRX/RRX input typically contains a substantial amount of Inter Symbol Interference
(ISI) or deterministic jitter which reduces the ability of the receiver to recover data without errors. An equalizer
has been added to each of the receiver’s input buffers in order to compensate for this deterministic jitter. This
circuit has been designed to effectively reduce the ISI commonly found in copper cables or backplane traces due
to low frequencies traveling faster than high frequencies as a result of the skin effect. The equalizer boosts high
frequency edge response in order to reduce the adverse effects of ISI.
LBEN(1:0)
RXP/R
Serial Data Source
≠
1 0
0
RRX
≠
1 0
1
PRX
= 1 0
X
LBTX (Loopback from PTX/RTX)
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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 8
G52268-0, Rev 3.3
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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Clock and Data Recovery
The receiver has a Clock Recovery Unit (CRU) which accepts the selected serial input source, extracts the
high-speed clock and retimes the data. The CRU is monolithic. The CRU automatically locks on data and if the
data is not present, will automatically lock to the REFCLK. This maintains a very well-behaved recovered
clock, RCLK/RCLKN which does not contain any slivers and will operate at a frequency of the REFCLK
reference +/- 200 ppm. The use of an external Lock-to-Reference pin is not needed.
The Clock Recovery Unit must perform bit synchronization which occurs when the CRU locks onto and
properly samples the incoming serial data as described in the previous paragraph. When the CRU is not locked
onto the serial data, the 10-bit data out of the decoder is invalid which results in numerous 8B/10B decoding
errors or disparity errors. When the link is disturbed (e.g., the cable is disconnected or the serial data source is
switched), the CRU will require a certain amount of time to lock onto data, which is specified in the AC Timing
Specification for “Data Acquisition Lock Time.”
Deserializer and Character Alignment
The retimed serial data stream is converted into 10-bit characters by the deserializer. A special 7-bit
“Comma” pattern (‘0011111xxx’ or ‘1100000xxx’) is recognized by the receiver and allows it to identify the
10-bit character boundary. Note that this pattern is found in three special characters, K28.1, K28.5 and K28.7.
However, K28.5 is chosen as the unique IDLE character. Only K28.1 and K28.5 should be used in normal
operation. The K28.7 character should be reserved for test and characterization use.
Character alignment occurs when the deserializer synchronizes the 10-bit character framing boundary to a
“Comma” pattern in the incoming serial data stream. If the receiver identifies a “Comma” pattern in the
incoming data stream which is misaligned to the current framing boundary the receiver will re-synchronize the
recovered data in order to align the data to the new “Comma” pattern. Re-synchronization ensures that the
“Comma” character is output on the internal 10-bit bus so that bits 0 through 9 equal ‘0011111xxx’ or
‘1100000xxx’. If the “Comma” pattern is aligned with the current framing boundary, then re-synchronization
will not change the current alignment. Re-synchronization is always enabled and cannot be turned off when
ENDEC is HIGH. After character re-synchronization the VSC7212 ensures that within a link, the 8-bit data sent
to the transmitting VSC7212 will be recovered by the receiving VSC7212 in the same bit locations as the
transmitter (i.e. T(7:0) = R(7:0)). When ENDEC is LOW, “Comma” detection and alignment are enabled only if
KCHAR is HIGH.
10B/8B Decoder
The 10-bit character from the deserializer is decoded in the 10B/8B decoder, which outputs the 8B data byte
and three bits of status information. If the 10-bit character does not match any valid value, an Out-of-Band Error
is generated which is output on the receiver status bus. Similarly, if the running disparity of the character does
not match the expected value, a Disparity Error is generated. The decoder also reports when a K-character is
received, and distinguishes the K28.5 (IDLE) character from other K-characters. This status information is
combined with LOS State Machine status and FIFO error status, to produce the prioritized per-character link
status output information (see Table 7).
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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
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Elastic Buffer and Channel De-Skewing
An elastic buffer is included in the receiver. Decoded data and status information is written into these
buffers with the recovered clock, and is read with the selected word clock (either the recovered clock or
REFCLK). In addition to allowing decoded data to easily cross from a receiver’s recovered clock domain to its
output clock domain, the elastic buffer facilitates chip-to-chip alignment (the reconstruction of a multi-byte
word as presented to the transmitting devices), and facilitates rate matching via IDLE character insertion/
deletion when the receiver’s recovered clock is not frequency-locked to its selected word clock.
There are three conditions under which a receiver’s elasticity buffer is recentered. The RESETN input,
when asserted LOW, recenters the read/write pointers in the elasticity buffer. Whenever a “Comma” character is
received which changes the receive character’s framing boundary, the elasticity buffer is recentered. Lastly, it is
also recentered whenever the receiver detects the synchronization point in the Word Sync Sequence. All three of
these events are associated with chip initialization or link initialization and would not occur during normal data
transfer. Note that recentering can result in the loss or duplication of decoded character data and status
information.
When a condition changes transmit timing (e.g., phase shifts in TBC) or shifts phase/alignment into the
receiver, the user should resend a Word Sync Event or assert RESETN in order to recenter the elasticity buffer.
Otherwise, data corruption could occur. It is unsafe to assume that after a change in transmit timing that
“Comma” characters will be misaligned and will cause recentering
The VSC7212 presents recovered data on R(7:0) and status on IDLE, KCH and ERR. These outputs are
timed either to the receiver’s recovered clock (RCLK/RCLKN) or to REFCLK. The output timing reference is
selected by RMODE(1:0) (see Table 5). TBERR, PSDET and RSDET are also synchronized to the selected
word clock. There are two choices for REFCLK-based timing, which differ in the positioning of the data valid
window associated with the output signals timed to REFCLK. When RMODE(1:0)=00 REFCLK is
approximately centered in the output data valid window as in the VSC7211 or VSC7214. When
RMODE(1:0)=01 REFCLK slightly leads the data valid window so that output data appears to have a more
typical “Clock-to-Q” timing relationship to REFCLK.
Table 5: Receive Interface Output Timing Mode
The term “word clock” will be used for whichever clock, REFCLK or RCLK/RCLKN, is selected as the
output timing reference. If RMODE(1) is HIGH, the receiver’s RCLK/RCLKN outputs are complementary
outputs at 1/10th or 1/20th the baud rate of the incoming data depending upon DUAL. If RMODE(1) is LOW,
then the RCLK/RCLKN outputs are held HIGH/LOW and the data bus and status outputs are timed to
REFCLK. If DUAL is HIGH, all data at the receiver’s output port is synchronously clocked out on both positive
and negative edges of the selected word clock at 1/20th the baud rate. If DUAL is LOW, the data is clocked out
RMODE(1:0)
Output Timing Reference
0 0
REFCLK (Centered)
0 1
REFCLK (Leading)
1 X
RCLK/RCLKN
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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 10
G52268-0, Rev 3.3
04/10/01
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of the VSC7212 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing waveforms
for the output data and status are shown in Figure 6, Figure 7 and Figure 8.
Figure 6: Receive Timing, RMODE(1:0) = 00
Figure 7: Receive Timing, RMODE(1:0) = 01
Figure 8: Receive Timing, RMODE(1:0) = 1X
REFCLK
(DUAL = 0)
Valid
IDLE
Valid
Valid
R(7:0)
KCH
REFCLK
(DUAL = 1)
ERR
REFCLK
(DUAL = 0)
IDLE
Valid
Valid
R(7:0)
KCH
REFCLK
(DUAL = 1)
ERR
Valid
RCLK
(DUAL = 0)
Valid
IDLE
Valid
Valid
R(7:0)
KCH
RCLK
(DUAL = 1)
ERR
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SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
Page 11
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
If RMODE1 is LOW and if the transmitting device’s REFCLK is not precisely frequency-locked to a
receiver’s REFCLK, then the channel’s elastic buffer will tend to gradually fill or empty as the recovered clock
(which is by definition frequency-locked to the transmitter’s REFCLK) steadily drifts in phase relative to the
word clock. In order to accommodate frequency differences between a transmitter’s REFCLK and the receiver’s
REFCLK, the VSC7212 can automatically perform “rate matching” by either deleting or duplicating IDLE
characters. FLOCK must be LOW and WSI must be connected to WSO to enable rate matching. It is the user’s
responsibility to ensure that the frequency at which IDLEs are transmitted accommodates the frequency
differences, if any, in their system architecture. Not meeting the IDLE density requirements described below
may result in Underrun/Overrun Errors.
The elastic buffer is designed to allow a maximum phase drift of +2 or -2 serial clock bit times between re-
synchronizations, which sets a limit on the maximum data “packet” length allowed between IDLEs. This
maximum packet length depends on the frequency difference between the transmitting and receiving devices
REFCLKs. Let
represent phase drift in bit times, and let
represent one full 10-bit character of phase
drift. Limiting phase drift to two bit times means the following inequality must be satisfied:
(1)
Let L be the number of 10-bit characters transmitted, and let Df be the frequency offset in ppm. The total
phase drift in bit times is given by:
(2)
A simple expression for maximum packet length as a function of frequency offset is derived by substituting
(2) in (1) and solving for L:
(3)
As an example, if the frequency offset is 200ppm, then the maximum packet length should not be more than
1K bytes. To increase the maximum packet length L, decrease the frequency offset Df. Note that if only one
K28.5 is transmitted between “packets” of data, it might be dropped during compensation for phase drift. If the
user must have at least one K28.5 between these two packets, then two K28.5s must be transmitted.
Using Multiple VSC7212s in Parallel
Multiple VSC7212s and VSC7216s can be used in parallel to form wider bus widths. In order for chip-to-
chip word alignment to function correctly across multiple devices, each transmit channel’s input data must be
transmitted synchronously to a common REFCLK or TBC, and each receiver’s output data must also be aligned
to a common REFCLK. This requires that all transmitting devices use either the same or identical REFCLKs,
and that TMODE(2:0)=000 (inputs timed to REFCLK) or TMODE(2:0)=1X0 (inputs timed to TBC). If inputs
are timed to TBC, then all transmitting devices must use either the same or identical TBCs. Since all receive
channels must use a common word clock, the receiving devices must also use the same or identical REFCLKs
and it must be selected as the word clock for all receive channels (RMODE(1:0)=0X).
∆φ
2
π
∆φ
0.2
2
π
×
(
)
≤
∆φ
∆
f 10
6
⁄
(
)
2
π
×
L
=
L
0.2
10
6
×
(
) ∆
f
⁄
≤
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SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 12
G52268-0, Rev 3.3
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Within the receiver there are elastic buffers used to deskew multiple VSC7212s and/or VSC7216s in order
to align them to a common word clock. The receiver’s elastic buffer allows the chips’ input to be skewed up to
+/-7 bit times in order to accommodate circuit imperfections, differences in transmission delay and jitter.
Multiple devices can be used in synchronous operation if the skew between all serial input pairs is maintained
less than +/-7 serial clock bit times. This allows easy implementation of robust systems.
Chip-to-Chip word alignment is enabled by connecting the WSI input of all devices to the WSO output of
an arbitrarily selected “Master” device. The FLOCK input state and WSI input source determine whether or not
rate matching (IDLE deletion or duplication) will be performed. Chip-to-chip alignment is disabled when WSI
is not connected to a WSO output. Rate matching is disabled when either FLOCK is HIGH or WSI is held LOW
(see Table 6).
In order to perform word alignment, a synchronization point must be seen across all receivers to be aligned
within the +/-7 bit time window. The VSC7212 receiver recognizes the first four characters of the Word Sync
Sequence (either K28.5+ K28.5+ K28.5- K28.5- or K28.5- K28.5- K28.5+ K28.5+) as the synchronization
point. As a model for understanding, consider the case where two VSC7212 transmitters send 16 bits of data to
two receivers via copper media which has small cable length differences causing chip-to-chip skew. Both
transmitters must be word aligned by simultaneously sending the Word Sync Sequence (within the +/-7 bit
window). On detection of the synchronization point, the receivers will reposition the recovered data within their
elastic buffers in order to align both devices and remove any chip-to-chip skew. All normal data characters
following the Word Sync Sequence will be properly chip-to-chip word aligned. In the process of alignment, one
or two of the final twelve K28.5 characters in the Word Sync Sequence may be deleted or duplicated.
The VSC7212 is capable of performing rate matching in multiple device applications by inserting or
deleting IDLEs in parallel across all receivers. This requires that the chip-to-chip aligned data streams contain
IDLEs inserted simultaneously on all transmitters according to the IDLE density requirement previously
described.
Table 6: Word Alignment and Rate Matching Control
FLOCK
WSI Source
Chip-to-Chip Alignment
Rate Matching
0
0
Off
Off
0
It’s own WSO
or 1
Off
Enabled within chip
0
Another chips’ WSO
Enabled
Enabled between chips
1
0
Off
Off
1
1
Off
Off
1
Another chips’
WSO
Enabled
Off
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SEMICONDUCTOR CORPORATION
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SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
Page 13
04/10/01
© VITESSE
SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
There are four distinct modes of operation defined in Table 6. The first row disables both word alignment
and rate matching. (The fourth and fifth row configurations function identically to the first row.) The second
row configures the VSC7212 to perform rate matching within its receiver without regard to other devices. Word
alignment is disabled and IDLEs will be dropped/duplicated independently of other devices. The third row
configures the part to perform word alignment and rate matching across multiple devices. All receivers will be
aligned per the device driving WSO, and IDLE words will be dropped/duplicated across the aligned channels as
required. The last row configures the part to perform word alignment and disables rate matching. This mode of
operation is appropriate for a frequency-locked application where it desired to align the receive channels
without altering the received data streams.
WSO uses a simple 3-bit serial protocol, synchronous to the Master device’s selected word clock, for
indicating the required synchronization action to other VSC7212s. A steady LOW level indicates no action is
required. ‘101’ indicates that Master device has seen a Word Sync Event. The relative timing relationship
between receiving a Word Sync Event (on all devices together) and seeing ‘101’ on the WSI input in the other
channels allows these channels to word-synchronize with to the Master. ‘110’ indicates that the next IDLE
encountered in the receive data stream should be deleted. ‘111’ indicates that an IDLE should be inserted after
the next IDLE encountered in the receive data stream. Note that the arbitrarily chosen Master device must have
valid input data.
Decoder Bypass Mode
If ENDEC is LOW, the 8B/10B decoder is bypassed and a 10-bit received character, R(9:0), is output from
the receiver. The KCH output becomes R8, and ERR becomes R9. Character alignment is handled differently in
this mode of operation. As mentioned in the “Encoder Bypass Mode” section, the KCHAR input becomes
ENCDET which enables “Comma” detection and re-synchronization when HIGH, and disables re-
synchronization when LOW. Only the ‘0011111xxx’ version of the Comma pattern is recognized when ENDEC
is LOW. The IDLE output becomes COMDET (Comma Detect) which signals detection of the ‘0011111xxx’
Comma pattern in the current 10-bit output character when high. This mode of operation is equivalent to a 10-
bit interface commonly found in serializer/deserializers for the Fibre Channel (e.g., VSC7125) and Gigabit
Ethernet markets (e.g., VSC7135).
The logic used to align multiple devices and perform rate matching is disabled when ENDEC is LOW. In
order for this mode of operation to function without errors, the word clock source as selected by RMODE(1:0)
must be frequency locked to the REFCLK of the remote transmitting device in each channel. This is guaranteed
when RMODE(1:0) = 11. For other choices of RMODE(1:0) the frequency locked condition must be
guaranteed by system design. When DUAL is HIGH and RMODE(1:0) = 10 or 11, the character containing the
‘0011111xxx’ “Comma” pattern is aligned to RCLK/RCLKN so that COMDET will be asserted on the falling
edge of RCLK (rising edge of RCLKN). This is done by adjusting the latency through the elastic buffer, the
recovered clock is never stretched or slivered. When the “Comma” pattern changes the framing boundary, data
characters prior to the assertion of COMDET on the falling edge of RCLK may be corrupted.
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SEMICONDUCTOR CORPORATION
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 14
G52268-0, Rev 3.3
04/10/01
© VITESSE