WM8143-10
10-bit/6MSPS CCD Signal Processor
Production Data June 1998 Rev 3f
Production Data datasheets
contain final specifications current
on publication date. Supply of
products conforms to Wolfson
Microelectronic's terms and
conditions.
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176
email: sales@wolfson.co.uk
www: http://www.wolfson.co.uk
©
1998 Wolfson Microelectronics Ltd.
Description
The WM8143-10 integrates the analogue signal
conditioning required by CCD sensors with a 10-bit ADC.
The WM8143-10 requires minimal external circuitry and
provides a cost-effective sensor to digital domain system
solution.
Each of the three analogue conditioning channels
includes reset level clamp, CDS, fine offset level shifting
and programmable gain amplification. The three channels
are multiplexed into the ADC. The output from the ADC is
fed to the output bus pins OP[9:0] via a 10/8 bit
multiplexer, enabled by the OEB signal.
The flexible output architecture allows ten-bit data to be
accessed either on a ten-bit bus or via a time-multiplexed
eight-bit bus. The WM8143-10 can be configured for
pixel-by-pixel or line-by-line multiplexing operation. Reset
level clamp and/or CDS features can be optionally
bypassed. The device configuration is programmed either
via a simple serial interface or via an eight-bit parallel
interface.
The serial/parallel interfaces of the WM8143-10 are
control compatible with those of the WM8144-10 and
WM8144-12.
Features
•
Reset level clamp
•
Correlated double sampling (CDS)
•
Fine offset level shifting
•
Programmable gain amplification
•
10-bit ADC with maximum 6 MSPS
•
Simple clocking scheme
•
Control by serial or parallel interface
•
Time multiplexed eight-bit data output mode
•
32 pin TQFP package
•
Interface compatible with WM8144-10 and
WM8144-12
Applications
•
Flatbed scanners
•
Sheet feed scanners
•
Film scanners
•
CCD sensor interfaces
•
Contact image sensor (CIS) interfaces
Block Diagram
+
+
OFFSET
+
+
+
+
M
U
X
RINP
GINP
BINP
TIMING CONTROL
VSMP
MCLK
RLC
DGND
DVDD
AVDD
10-bit
ADC
10/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
SDI / DNA
SCK / RNW
SEN / STB
NRESET
OEB
MUX
VMID
VRLC
VRU
VRT
VRB
VMID
CL
RS
VS
AGND
WM8143-10
VMID
OFFSET
OFFSET
OP[9:0]
PGA
PGA
5-BIT REG
CDS
5-BIT REG
5-BIT REG
PGA
VMID
VMID
CDS
CDS
S/H
S/H
S/H
S/H
S/H
S/H
8-BIT +
SIGN DAC
8-BIT +
SIGN DAC
8-BIT +
SIGN DAC
WM8143-10
Production Data
Wolfson Microelectronics
PD Rev 3f June 98
2
Pin Configuration
Ordering Information
DEVICE
TEMP. RANGE
PACKAGE
WM8143-10CFT/V
0 - 70
o
C
32 Pin TQFP
1
8
7
6
5
4
3
2
OP[0]
OP[6]
OP[5]
OP[4]
OP[3]
OP[2]
OP[1]
OP[7]
25
32
31
30
29
28
27
26
SCK/RNW
nc
nc
DGND
MCLK
VSMP
RLC
DVDD
24
17
18
19
20
21
22
23
SDI/DNA
VRLC
BINP
GINP
RINP
OEB
SEN/STB
VMID
16
9
10
11
12
13
14
15
VRT
OP[9]
NRESET
AVDD
AGND
VRU
VRB
OP[8]
WM8143-10
Absolute Maximum Ratings
Analogue Supply Voltage .......... AGND - 0.3V, AGND +7V
Digital Supply Voltage ...............DGND - 0.3V, DGND +7V
Digital Inputs .......................... DGND - 0.3V, DVDD +0.3V
Digital Outputs ....................... DGND - 0.3V, DVDD +0.3V
Reference Inputs ....................AGND - 0.3V, AVDD +0.3V
RINP, GINP, BINP..................AGND - 0.3 V, AVDD +0.3V
Operating Temperature Range, T
A
.......... 0
°
C to +70
°
C
Storage Temperature.......................... -50
°
C to +150
°
C
Lead Temperature (soldering 10 seconds) ....... +260
°
C
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are
given under Electrical Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during
handling and storage of this device.
As per JEDEC specifications A112-A and A113-A, this product requires specific storage conditions
prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2
and as such will be supplied in vacuum-sealed moisture barrier bags.
Recommended Operating Conditions
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage
AVDD, DVDD
4.75
5.25
V
Operating Temperature Range
T
A
0
70
o
C
Input Common Mode Range
V
CMR
0.5
4.5
V
Production Data
WM8143-10
Wolfson Microelectronics
PD.Rev 3f June 98
3
Electrical Characteristics
Test Characteristics
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … T
A
= 0
o
C to +70
o
C, MCLK = 12MHz, unless otherwise stated
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Supply Current - Active
100
140
mA
Supply Current - Standby
7
15
mA
Digital Inputs
High Level Input Voltage
V
IH
0.8*DVDD
V
Low Level Input Voltage
V
IL
0.2*DVDD
V
High Level Input Current
I
IH
1
µA
Low Level Input Current
I
IL
1
µA
Input Capacitance
5
pF
Digital Outputs
High Level Output Voltage
V
OH
I
OH
= 1mA
DVDD-0.75
V
Low Level Output Voltage
V
OL
I
OL
= 1mA
DGND+0.75
V
High Impedance Output
Current
I
OZ
1
µA
Input Multiplexer
CDS Mode Full Scale Input
Range (V
VS
-V
RS
)
x denotes the
channel selected
2
Gx
Vp-p
Channel to Channel Gain
Matching
1
%
Input Video Set-up Time
tVSU
10
ns
Input Video Hold Time
tVH
15
ns
Reset Video Set-up Time
tRSU
CDS Mode only
10
ns
Reset Video Hold Time
tRH
CDS Mode only
15
ns
Reference String
Reference Voltage – Top
VRT
VRU = 5V
3.47
3.5
3.53
V
Reference Voltage – Bottom
VRB
VRU = 5V
1.47
1.5
1.53
V
DAC Reference Voltage
VMID
VRU = 5V
2.47
2.5
2.53
V
R.L.C. Switching Impedance
500
Ω
1.46
1.5
1.54
V
2.46
2.5
2.54
V
Reset Level Clamp Options
VRLC
VRU=5V Voltage set
by register
configuration
3.46
3.5
3.54
V
Impedance VRT to VRB
250
500
750
Ω
Impedance VRU to AGND
1000
1500
2000
Ω
8-Bit DACs
Resolution
8
Bits
Zero Code Voltage
V
MID
-20
V
MID
+20
mV
Full Scale Voltage Error
0
20
mV
WM8143-10
Production Data
Wolfson Microelectronics
PD Rev 3f June 98
4
Test Characteristics
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … T
A
= 0
o
C to +70
o
C, MCLK = 12MHz, unless otherwise stated
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
Differential Non Linearity
DNL
0.1
0.5
LSB
Integral Non Linearity
INL
0.25
1
LSB
10-bit ADC performance including CDS, PGA and Offset Functions
NO MISSING CODES GUARANTEED
Resolution
AVDD = DVDD = 5V
10
Bits
Maximum Sampling Rate
AVDD = DVDD = 5V
6
MSPS
Zero Scale Transition Error
Voltage at VINP
DAC Code = 000H,
AVDD = DVDD = 5V,
measured relative to
VRB
± 25
±100
mV
Full Scale Transition Error
Voltage at VINP
DAC Code = 000H,
AVDD = DVDD = 5V,
measured relative to
VRT
± 25
±100
mV
Differential Non Linearity
DNL
AVDD = DVDD = 5V
+1
LSB
PGA Gain
Monotonicity Guaranteed
Red Channel Max Gain
Gr
7
7.5
Times
Green Channel Max Gain
Gg
7.5
8
Times
Blue Channel Max Gain
Gb
Mode 1
AVDD = DVDD = 5V
7.5
8
Times
Switching Characteristics
MCLK Period
tPER
83.3
ns
MCLK High
tCKH
37.5
ns
MCLK Low
tCKL
37.5
ns
Data Set-up Time
tDSU
10
ns
Data Hold Time
tDH
10
ns
Output Propagation Delay
tPD
I
OH
=1mA, I
OL
=1mA
75
ns
Output Enable Time
tPZE
50
ns
Output Disable Time
tPEZ
25
ns
Serial Interface
SCK Period
tSPER
83.3
ns
SCK High
tSCKH
37.5
ns
SCK Low
tSCKL
37.5
ns
SDI Set up Time
tSSU
10
ns
SDI Hold Time
tSH
10
ns
Set up Time - SCK to SEN
tSCE
20
ns
Set up Time - SEN to SCK
tSEC
20
ns
Production Data
WM8143-10
Wolfson Microelectronics
PD.Rev 3f June 98
5
Test Characteristics
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … T
A
= 0
o
C to +70
o
C, MCLK = 12MHz, unless otherwise stated
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
SEN Pulse Width
tSEW
50
ns
Parallel Interface
RNW Low to OP[9:2] Tri-state
tOPZ
20
ns
Address Setup Time to STB
Low
tASU
0
ns
DNA Low Setup Time to STB
Low
tADLS
10
ns
Strobe Low Time
tSTB
50
ns
Address Hold Time from STB
High
tAH
10
ns
DNA Low Hold Time from
STB High
tADLH
10
ns
Data Setup Time to STB Low
tDSU
0
ns
DNA High Setup Time to STB
Low
tADHS
10
ns
Data Hold Time from STB
High
tDH
10
ns
Data High Hold Time from
STB High
tADHH
10
ns
RNW High to OP[9:2] Output
tOPD
0
ns
WM8143-10
Production Data
Wolfson Microelectronics
PD Rev 3f June 98
6
Pin Description
PIN
NAME
TYPE
DESCRIPTION
1
OP[0]
Digital OP
Tri-state digital 10-bit bi-directional bus. There are four modes:
2
OP1]
Digital OP
Tri-state:
when OEB = 1
3
OP[2]
Digital IO
4
OP[3]
Digital IO
5
OP[4]
Digital IO
6
OP[5]
Digital IO
7
OP[6]
Digital IO
8
OP[7]
Digital IO
9
OP[8]
Digital IO
10
OP[9]
Digital IO
Output ten-bit:
ten bit data is output from bus
Output 8-bit multiplexed:
data output on OP[9:2] at 2 * ADC
conversion rate
Input 8-bit:
control data is input on bits OP[9:2] in
parallel mode when SCK/RNW = 0.
MSB of the output word is OP[9], LSB is OP[0]
11
NRESET
Digital IP
Reset input, active low. This signal forces a reset of all internal registers and
selects whether serial control bus or parallel control bus is used ( see
SEN/STB)
12
AVDD
Analogue supply
Positive analogue supply (5V)
13
AGND
Analogue supply
Analogue ground (0V)
14
VRU
Analogue IP
15
VRB
Analogue OP
16
VRT
Analogue OP
ADC reference voltages. The ADC reference range is applied between V
RT
(full
scale) and V
RB
(zero level). V
RU
can be used to derive optimal reference
voltages from an external 5V reference
17
VMID
Analogue OP
Buffered mid-point of ADC reference string.
18
VRLC
Analogue OP
Selectable analogue output voltage for RLC
19
BINP
Analogue IP
Blue channel input video
20
GINP
Analogue IP
Green channel input video
21
RINP
Analogue IP
Red channel input video
22
OEB
Digital IP
Output tri-state control:
all outputs enabled when OEB=0
23
SEN/STB
Digital IP
Serial interface:
enable, active high
Parallel interface:
strobe, active low
Latched on NRESET rising edge: If low then device control is by serial
interface, if high then device control is by parallel interface
24
SDI/DNA
Digital IP
Serial interface:
serial interface input data signal
Parallel interface:
high = data, low = address
25
SCK/RNW
Digital IP
Serial interface:
serial interface clock signal
Parallel interface:
high = OP[9:2] is output bus
low = OP[9:2] is input bus
26
RLC
Digital IP
Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is
required on each pixel then this pin can be tied high
27
VSMP
Digital IP
Video sample synchronisation pulse. This signal is applied synchronously with
MLCK to specify the point in time that the input is sampled. The timing of
internal multiplexing between the R, G and B channels is derived from this
signal
28
MCLK
Digital IP
Master clock. This clock is applied at eight, six, three or two times the input pixel
rate depending on the operational mode. MCLK is divided internally to define the
ADC sample rate and to provide the clock source for digital logic
Production Data
WM8143-10
Wolfson Microelectronics
PD.Rev 3f June 98
7
PIN
NAME
TYPE
DESCRIPTION
29
DGND
Digital supply
Digital ground (0V)
30
nc
Reserved, pin must be left unconnected
31
nc
Reserved, pin must be left unconnected
32
DVDD
Digital supply
Positive digital supply (5V)
Typical Performance
AVDD = DVDD = 5V, T
A
= 25
o
C
PGA Gain Code vs Actual Gain
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
8.25
0
1
2
3
4
5
6
7
8
9
Actual Gain
PGA Gain Code
RED
GREEN
BLUE
WM8143-10 DNL
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0
256
512
768
1024
ADC Code
LSB's
WM8143-10
Production Data
Wolfson Microelectronics
PD Rev 3f June 98
8
System Description
RED
GREEN
BLUE
COLOUR CCD
SENSOR
BUFFERING
FOR CCD
OP[9:0]
OEB
SDI/DNA
SCK/RNW
NRESET
SEN/STB
VSMP
MCLK
RLC
WM8143-10
RINP
GINP
BINP
PARALLEL
DATA I/O
CONTROL/SERIAL
DATA IN
ANALOGUE
INTERFACE TIMING
Figure 1 System Diagram
The WM8143-10 signal processing IC interfaces
typically via buffering and AC coupling to the output of
CCD image sensors. The WM8143-10 also interfaces
to CIS image sensors via DC coupling.
Analogue output signals from the image sensor are
sampled, amplified and offset-corrected by the IC
before being converted into digital form by an on-board
high-speed 10-bit resolution analogue to digital
converter. Figure 1 illustrates a typical system
implementation where the three colour outputs from the
CCD image sensor are buffered and AC coupled to the
analogue inputs of the WM8143-10.
The digital interface to the WM8143-10 can be divided
into three distinct sections: -
•
Parallel Data I/O
•
Digital Control/Serial Timing
•
Analogue Interface Timing
These sections are constructed for ease of use by the
system designer and are described in detail on the
following pages of this datasheet.
Production Data
WM8143-10
Wolfson Microelectronics
PD.Rev 3f June 98
9
Device Description
S/H, Offset DACs and PGA
Each analogue input (RINP, GINP, BINP) of the
WM8143-10 consists of a sample and hold, a
programmable gain amplifier, and a DC offset
correction block. The operation of the red input stage is
summarised in Figure 2.
S/H
S/H
GAIN=G
VS
VMID
V
ADC
VMID
V
OFFSET
RINP
RS
-
+
+
+
Figure 2 Operation of Red Input Stage
The sample/hold block can operate in two modes of
operation, CDS (Correlated Double Sampling) or Single
Ended.
In CDS operation the video signal processed is the
difference between the voltage applied at the RINP
input when RS occurs, and the voltage at the RINP
input when VS occurs. This is summarised in Figure 3.
Figure 3 Video Signal Processed in CDS mode
When using CDS the actual DC value of the input
signal is not important, as long as the signal extremes
are maintained within 0.5 volts of the chip power
supplies. This is because the signal processed is the
difference between the two sample voltages, with the
common DC voltage being rejected.
In Single Ended operation, the VS and RS control
signals occur simultaneously, and the voltage applied
to the reset switch is fixed at V
MID
. This means that the
voltage processed is the difference between the voltage
applied to RINP when VS/RS occurs, and V
MID
. When
using Single Ended operation the DC content of the
video signal is not rejected.
The Programmable Gain Amplifier block multiplies the
resulting input voltage by a value between 0.5 and 8.25
which can be programmed independently for each of
the three input channels via the serial (or parallel)
interface.
Table 1 illustrates the PGA Gains Register codes
required for typical gains. (See Typical Performance
Graphs). The typical gain may also be calculated using
the following equation:
Typical Gain = 0.5+(Code
∗0
.25).
CODE
TYPICAL
GAIN
CODE
TYPICAL
GAIN
00000
0.5
10000
4.5
00001
0.75
10001
4.75
00010
1
10010
5
00011
1.25
10011
5.25
00100
1.5
10100
5.5
00101
1.75
10101
5.75
00110
2
10110
6
00111
2.25
10111
6.25
01000
2.5
11000
6.5
01001
2.75
11001
6.75
01010
3
11010
7
01011
3.25
11011
7.25
01100
3.5
11100
7.5
01101
3.75
11101
7.75
01110
4
11110
8
01111
4.25
11111
8.25
Table 1 Typical Gain
The DC value of the gained signal can then be trimmed
by the 8 bit plus sign DAC. The voltage output by this
DAC is shown as V
OFFSET
in Figure 2. The range of the
DAC is (V
MID
/2) or 1.5*(V
MID
/2) if the DAC_RANGE bit
in Set-up Register 4 is set.
The output from the offset DAC stage is referenced to
the V
MID
voltage. This allows the input to the ADC to
maximise the dynamic range, and is shown
diagrammatically in Figure 2 by the final V
MID
addition.
RS
VS
V
RS
V
VS
WM8143-10
Production Data
Wolfson Microelectronics
PD Rev 3f June 98
10
For the input stage, the final analogue voltage applied
to the ADC can be expressed as:
Where V
ADC
is the voltage applied, to the ADC
G is the programmed gain
V
VS
is the voltage of the video sample.
V
RS
is the voltage of th