Z86C21 PS Mstr

Z86C21 MCU

WITH

8K ROM

RODUCT

PECIFICA

TION

8-Bit CMOS MCU with 8 Kbytes of ROM

256 Byte Register File

- 236 Bytes of General-Purpose RAM

- 16 Bytes Control/Status Registers

- 4 Bytes for Ports

40-Pin DIP, 44-Pin PLCC or 44-Pin QFP Package

4.5V to 5.5V Operating Range

Low Power Consumption: 220 mW (max) @ 16 MHz

Fast instruction pointer: 1.0

s @ 12 MHz

Two Standby Modes: STOP and HALT

32 Input/Output Lines

FEATURES

Z86C21

8K ROM Z8

CMOS

ICROCONTROLLER

Full-Duplex UART

All Digital Inputs are TTL Levels

Auto Latches

RAM and ROM Protect

Two Programmable 8-Bit Counter/Timers each with

6-Bit Programmable Prescaler.

Six Vectored, Priority Interrupts from Eight Different

Sources

Clock Speeds: 12 and 16 MHz

On-Chip Oscillator that Accepts a Crystal, Ceramic

Resonator, LC, or External Clock Drive.

GENERAL DESCRIPTION

The Z86C21 microcontroller is a member of the Z8 single-

chip microcontroller family with 8 Kbytes of ROM and

236 bytes of RAM. The device is packaged in a 40-pin DIP,

44-pin PLCC, or a 44-pin QFP with a ROMless pin option

available on the 44-pin versions only. With the ROM/

ROMless feature selectively, the Z86C21 offers both exter-

nal memory and preprogrammed ROM, making it well-

suited for high-volume applications or where code flexibil-

ity is required.

Zilog’s CMOS microcontroller offers fast execution, effi-

cient use of memory, sophisticated interrupts, input/output

bit manipulation capabilities, and easy hardware/software

system expansion along with low cost and low power

consumption.

The Z86C21 architecture is characterized by Zilog’s 8-bit

microcontroller core. The device offers a flexible I/O

scheme, an efficient register and address space structure,

multiplexed capabilities between address/data, I/O, and a

number of ancillary features that are useful in many indus-

trial and advanced scientific applications.

For applications demanding powerful I/O capabilities, the

Z86C21 provides 32 pins dedicated to input and output.

These lines are grouped into four ports. Each port consists

of eight lines, and is configurable under software control to

provide timing, status signals, serial or parallel

I/O with or without handshake, and an address/data bus

for interfacing external memory. There are three basic

address spaces available to support this configuration:

Program Memory, Data Memory, and 236 general-pur-

pose registers.

Z86C21 MCU

WITH

8K ROM

GENERAL DESCRIPTION

(Continued)

To unburden the program from coping with the real-time

tasks, such as counting/timing and serial data communi-

cation, the Z86C21 offers two on-chip counter/timers with

a large number of user selectable modes, and an on-board

UART.

Port 3

UART

Counter/

Timers

(2)

Interrupt

Control

Port 2

I/O

(Bit Programmable)

ALU

FLAGS

Pointer

256 x 8-Bit

Machine Timing and

Instruction Control

Prg. Memory

8192 x 8-Bit

Program

Counter

Vcc

GND

XTAL

Port 0

Output

Input

Address or I/O

(Nibble Programmable)

Port 1

Address/Data or I/O

(Byte Programmable)

/AS /DS R//W /RESET

Figure 1. Z86C21 Functional Block Diagram

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.,

B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

Ground

GND

Z86C21 MCU

WITH

8K ROM

PIN DESCRIPTION

Pin #

Symbol

Function

Direction

Power Supply

Input

XTAL2

Crystal, Oscillator Clock

Output

XTAL1

Crystal, Oscillator Clock

Input

P37

Port 3, Pin 7

Output

P30

Port 3, Pin 0

Input

/RESET

Reset

Input

R//W

Read/Write

Output

/DS

Data Strobe

Output

/AS

Address Strobe

Output

P35

Port 3, Pin 5

Output

Pin #

Symbol

Function

Direction

GND

Ground

Input

P32

Port 3, Pin 2

Input

13-20

P00-P07

Port 0, Pins 0,1,2,3,4,5,6,7 In/Output

21-28

P10-P17

Port 1, Pins 0,1,2,3,4,5,6,7 In/Output

P34

Port 3, Pin 4

Output

P33

Port 3, Pin 3

Input

31-38

P20-P27

Port 2, Pins 0,1,2,3,4,5,6,7 In/Output

P31

Port 3, Pin 1

Input

P36

Port 3, Pin 6

Output

Table 1. 40-Pin DIP Pin Identification

P36

P31

P21

P27

P26

P25

P24

P23

P22

VCC

XTAL2

P37

P30

/RESET

R//W

/DS

XTAL1

GND

P32

P00

P01

P20

P33

P34

P17

P16

Z86C21

DIP

/AS

P35

P02

P03

P06

P07

P05

P04

P13

P15

P14

P12

P11

P10

Figure 2. 40-Pin DIP Pin Assignments

Z86C21 MCU

WITH

8K ROM

PIN DESCRIPTION

(Continued)

N/C

P30

P37

XTAL1

XTAL2

VCC

P36

P31

P27

P26

P25

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

N/C

P24

P23

P22

P21

P20

P33

P34

P17

P16

P15

/RESET

R//W

/DS

/AS

P35

GND

P32

P00

P01

P02

R//RL

Z86C21

PLCC

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

Table 2. 44-Pin PLCC Pin Identification

Pin #

Symbol

Function

Direction

14-16

P00-P02

Port 0, Pins 0,1,2

In/Output

R//RL

ROM/ROMless control

Input

18-22

P03-P07

Port 0, Pins 3,4,5,6,7

In/Output

23-27

P10-P14

Port 1, Pins 0,1,2,3,4

In/Output

N/C

Not Connected

Input

29-31

P15-P17

Port 1, Pins 5,6,7

In/Output

P34

Port 3, Pin 4

Output

P33

Port 3, Pin 3

Input

34-38

P20-P24

Port 2, Pins 0,1,2,3,4

In/Output

N/C

Not Connected

Input

40-42

P25-P27

Port 2, Pins 5,6,7

In/Output

P31

Port 3, Pin 1

Input

P36

Port 3, Pin 6

Output

Pin #

Symbol

Function

Direction

Power Supply

Input

XTAL2

Crystal, Oscillator Clock

Output

XTAL1

Crystal, Oscillator Clock

Input

P37

Port 3, Pin 7

Output

P30

Port 3, Pin 0

Input

N/C

Not Connected

Input

/RESET

Reset

Input

R//W

Read/Write

Output

/DS

Data Strobe

Output

/AS

Address Strobe

Output

P35

Port 3, Pin 5

Output

GND

Ground

Input

P32

Port 3, Pin 2

Input

Figure 3. 44-Pin PLCC Pin Assignments

Z86C21 MCU

WITH

8K ROM

33 32 31 30 29 28 27 26 25 24 23

GND

P30

P37

XTAL1

XTAL2

VCC

P36

P31

P27

P26

P25

/RESET

R//W

/DS

/AS

P35

GND

P32

P00

P01

P02

R//RL

GND

P24

P23

P22

P21

P20

P33

P34

P17

P16

P15

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

GND

Z86C21

QFP

Table 3. 44-Pin QFP Pin Identification

Pin #

Symbol

Function

Direction

1-5

P03-P07

Port 0, Pins 3,4,5,6,7

In/Output

GND

Ground

Input

7-14

P10-P17

Port 1, Pins 0 through 7

In/Output

P34

Port 3, Pin 4

Output

P33

Port 3, Pin 3

Input

17-21

P20-P24

Port 2, Pins 0,1,2,3,4

In/Output

GND

Ground

Input

23-25

P25-P27

Port 2, Pins 5,6,7

In/Output

P31

Port 3, Pin 1

Input

P36

Port 3, Pin 6

Output

GND

Ground

Input

Power Supply

Input

XTAL2

Crystal, Oscillator Clock

Output

Pin #

Symbol

Function

Direction

XTAL1

Crystal, Oscillator Clock

Input

P37

Port 3, Pin 7

Output

P30

Port 3, Pin 0

Input

/RESET

Reset

Input

R//W

Read/Write

Output

/DS

Data Strobe

Output

/AS

Address Strobe

Output

P35

Port 3, Pin 5

Output

GND

Ground

Input

P32

Port 3, Pin 2

Input

41-43

P00-P02

Port 0, Pins 0,1,2

In/Output

R//RL

ROM/ROMless control

Input

Figure 4. 44-Pin QFP Pin Assignments

Z86C21 MCU

WITH

8K ROM

PIN FUNCTIONS

/ROMless

(input, active Low). This pin, when connected to

GND, disables the internal ROM and forces the device to

function as a Z86C91 ROMless Z8. For more details on the

ROMless version, refer to the Z86C91 product specifica-

tion. (

Note:

When left unconnected or pulled high to V

the part functions as a normal Z86C21 ROM version). This

pin is only available on the 44-pin versions of the Z86C21.

/DS

(output, active Low). Data Strobe is activated once for

each external memory transfer. For a READ operation,

data must be available prior to the trailing edge of /DS. For

WRITE operations, the falling edge of /DS indicates that

output data is valid.

/AS

(output, active Low). Address Strobe is pulsed once at

the beginning of each machine cycle. Address output is

through Port 1 for all external programs. Memory address

transfers are valid at the trailing edge of /AS. Under

program control, /AS is placed in the high-impedance

state along with Ports 0 and 1, Data Strobe, and Read/

Write.

XTAL1, XTAL2

Crystal 1, Crystal 2 (time-based input and

output, respectively). These pins connect a parallel-reso-

nant crystal, ceramic resonator, LC, or any external single-

phase clock to the on-chip oscillator and buffer.

R//W

(output, write Low). The Read/Write signal is Low

when the MCU is writing to the external program or data

memory.

/RESET

(input, active Low). To avoid asynchronous and

noisy reset problems, the Z86C21 is equipped with a reset

filter of four external clocks (4TpC). If the external /RESET

signal is less than 4TpC in duration, no reset occurs.

On the fifth clock after the /RESET is detected, an internal

RST signal is latched and held for an internal register count

of 18 external clocks, or for the duration of the external

/RESET, whichever is longer. During the reset cycle, /DS is

held active Low while /AS cycles at a rate of TpC2. When

/RESET is deactivated, program execution begins at loca-

tion 000C (HEX). Power-up reset time must be held Low for

50 ms, or until V

is stable, whichever is longer.

Port 0

(P07-P00). Port 0 is an 8-bit, nibble programmable,

bidirectional, TTL compatible port. These eight I/O lines

can be configured under software control as a nibble I/O

port, or as an address port for interfacing external memory.

When used as an I/O port, Port 0 may be placed under

handshake control. In this configuration, Port 3, lines P32

and P35 are used as the handshake control /DAV0 and

RDY0 (Data Available and Ready). Handshake signal

assignment is dictated by the I/O direction of the upper

nibble P07-P04. The lower nibble must have the same

direction as the upper nibble to be under handshake

control.

For external memory references, Port 0 can provide ad-

dress bits A11-A8 (lower nibble) or A15-A8 (lower and

upper nibble) depending on the required address space.

If the address range requires 12 bits or less, the upper

nibble of Port 0 is programmed independently as I/O while

the lower nibble is used for addressing. If one or both

nibbles are needed for I/O operation, they must be config-

ured by writing to the Port 0 Mode register.

In ROMless mode, after a hardware reset, Port 0 lines are

defined as address lines A15-A8, and extended timing is

set to accommodate slow memory access. The initializa-

tion routine includes reconfiguration to eliminate this ex-

tended timing mode (Figure 5).

Z86C21 MCU

WITH

8K ROM

PIN FUNCTIONS

(Continued)

Port 1

(P17-P10). Port 1 is an 8-bit, byte programmable,

bidirectional, TTL compatible port. It has multiplexed Ad-

dress (A7-A0) and Data (D7-D0) ports. For Z86C21, these

eight I/O lines can be programmed as Input or Output lines

or can be configured under software control as an ad-

dress/data port for interfacing external memory. When

used as an I/O port, Port 1 can be placed under handshake

control. In this configuration, Port 3 line P33 and P34 are

used as the handshake controls RDY1 and /DAV1.

Memory locations greater than 8192 are referenced through

Port 1. To interface external memory, Port 1 is programmed

for the multiplexed Address/Data mode. If more than 256

external locations are required, Port 0 must output the

additional lines.

Port 1 can be placed in a high-impedance state along with

Port 0, /AS, /DS and R//W, allowing the MCU to share

common resource in multiprocessor and DMA applica-

tions. Data transfers are controlled by assigning P33 as a

Bus Acknowledge input, and P34 as a Bus request output

(Figure 6).

OEN

Out

PAD

Port 1

(AD7-AD0)

Z86C21

MCU

TTL Level Shifter

Auto Latch

≈

500 K

Ω

Handshake Controls

/DAV1 and RDY1

(P33 and P34)

Figure 6. Port 1 Configuration

Z86C21 MCU

WITH

8K ROM

Port 2

(P27-P20). Port 2 is an 8-bit, bit programmable,

bidirectional, CMOS compatible port. Each of these eight

I/O lines can be independently programmed as an input or

output or globally as an open-drain output. Port 2 is always

available for I/O operation. When used as an I/O port,

Port 2 may be placed under handshake control. In this

configuration, Port 3 lines P31 and P36 are used as the

handshake control lines /DAV2 and RDY2. The handshake

signal assignment for Port 3 lines P31 and P36 is dictated

by the direction (input or output) assigned to P27

(Figure 7).

OEN

Out

PAD

Port 2 (I/O)

Handshake Controls

/DAV2 and RDY2

(P31 and P36)

Z86C21

MCU

TTL Level Shifter

Auto Latch

≈

500 K

Ω

Open-Drain

Figure 7. Port 2 Configuration

\10

Z86C21 MCU

WITH

8K ROM

PIN FUNCTIONS

(Continued)

Port 3

(P37-P30). Port 3 is an 8-bit, CMOS compatible four-

fixed-input and four-fixed-output port. These eight I/O lines

have four-fixed input (P33-P30) and four fixed output

(P37-P34) ports. Port 3, when used as serial I/O, is pro-

grammed as serial in and serial out, respectively (Figure 8

and Table 4) Port 3 pins have Auto Latches only.

Port 3 is configured under software control to provide the

following control functions: handshake for Ports 0 and 2

(/DAV and RDY); four external interrupt request signals

(IRQ3-IRQ0); timer input and output signals (T

and T

OUT

and Data Memory Select (/DM).

UART Operation.

Port 3 lines P30 and P37, are be pro-

grammed as serial I/O lines for full-duplex serial asynchro-

Out

PAD

Z86C21

MCU

Port 3

(I/O or Control)

Auto Latch

≈

500 K

Ω

PAD

Port 3 Output Configuration

Port 3 Input Configuration

Figure 8. Port 3 Configuration

nous receiver/transmitter operation. The bit rate is con-

trolled by the Counter/Timer0.

The Z86C21 automatically adds a start bit and two stop bits

to transmitted data (Figure 9). Odd parity is also available

as an option. Eight data bits are always transmitted,

regardless of parity selection. If parity is enabled, the

eighth bit is the odd parity bit. An interrupt request (IRQ4)

is generated on all transmitted characters.

Received data must have a start bit, eight data bits and at

least one stop bit. If parity is on, bit 7 of the received data

is replaced by a parity error flag. Received characters

generate the IRQ3 interrupt request.

Z86C21 MCU

WITH

8K ROM

Table 4. Port 3 Pin Assignments

Pin

I/O

CTC1

Int.

P0 HS

P1 HS

P2 HS

UART

Ext

P30

IRQ3

Serial In

P31

IRQ2

D/R

P32

IRQ0

D/R

P33

IRQ1

D/R

P34

OUT

R/D

P35

OUT

R/D

P36

OUT

R/D

P37

OUT

Serial Out

IRQ4

IRQ5

Notes:

HS = Handshake Signals; D = Data Available; R = Ready

Auto Latch.

The Auto Latch puts valid CMOS levels on all

CMOS inputs that are not externally driven. This reduces

excessive supply current flow in the input buffer when it is

not been driven by any source.

Low EMI Option.

The Z86C21 is available in a Low EMI

option. This option is mask-programmable, to be selected

by the customer at the time when the ROM code is

submitted. Use of this feature results in:

The pre-drivers slew rate reduced to 10 ns typical.

Low EMI output drivers have resistance of 200 Ohms

typical.

Oscillator divide-by-two circuitry is eliminated.

Internal SCLK/TCLK operation is limited to a maximum

of 4 MHz (250 ns cycle time)

Start Bit

Seven Data Bits

Received Data (With Parity)

Parity Error Flag

One Stop Bit

Start Bit

Seven Data Bits

Transmitted Data (With Parity)

Odd Parity

Two Stop Bits

SP SP

Start Bit

Eight Data Bits

Transmitted Data (No Parity)

Two Stop Bits

SP SP

Start Bit

Eight Data Bits

Received Data (No Parity)

One Stop Bit

Figure 9. Serial Data Formats

\12

Z86C21 MCU

WITH

8K ROM

FUNCTIONAL DESCRIPTION

Address Space

Program Memory.

The Z86C21 can address up to 56K

bytes of external program memory (Figure 10). The first 12

bytes of program memory are reserved for the interrupt

vectors. These locations contain six 16-bit vectors that

correspond to the six available interrupts. For ROM mode,

byte 13 to byte 8191 consists of on-chip ROM. At ad-

dresses 8192 and greater, the Z86C21 executes external

program memory fetches. In the ROMless mode, the

Z86C21 can address up to 64K bytes of external program

memory. Program execution begins at external location

000C (HEX) after a reset.

Data Memory

(/DM). The ROM version can address up to

56K bytes of external data memory space beginning at

location 8192. The ROMless version can address up to

64K bytes of external data memory. External data memory

can be included with, or separated from, the external

program memory space. /DM, an optional I/O function that

can be programmed to appear on P34, is used to distin-

guish between data and program memory space (Figure

11). The state of the /DM signal is controlled by the type

instruction being executed. An LDC opcode references

PROGRAM (/DM inactive) memory, and an LDE instruction

references DATA (/DM active Low) memory.

External

ROM and RAM

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

IRQ5

65535

On-Chip ROM

8192

8191

Figure 10. Program Memory Configuration

65535

8192

8191