2.7V to 5.5V,8-Bit,4-Channel,DAC with Power Down

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

Four 8-Bit D/A Converters

Programmable Settling Time

of 3

s or 9

s Typ

TMS320, (Q)SPI, and Microwire Compatible

Serial Interface

Low Power Consumption:

7 mW, Slow Mode – 5-V Supply

3 mW, Slow Mode – 3-V Supply

Reference Input Buffers

Monotonic Over Temperature

Dual 2.7-V to 5.5-V Supply (Separate Digital

and Analog Supplies)

Hardware Power Down

Software Power Down

Simultaneous Update

applications

Battery Powered Test Instruments

Digital Offset and Gain Adjustment

Industrial Process Controls

Machine and Motion Control Devices

Arbitrary Waveform Generation

description

The TLV5627 is a four channel, 8-bit voltage

output digital-to-analog converter (DAC) with a

flexible 4-wire serial interface. The 4-wire serial

interface allows glueless interface to TMS320,

SPI, QSPI, and Microwire serial ports. The

TLV5627 is programmed with a 16-bit serial word

comprised of a DAC address, individual DAC

control bits, and an 8-bit DAC value.

The device has provision for two supplies: one

digital supply for the serial interface (via pins

and DGND), and one for the DACs,

reference buffers and output buffers (via pins AV

and AGND). Each supply is independent of the other, and

can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be

controlled via a microprocessor operating on a 3-V supply (also used on pins DV

and DGND), with the DACs

operating on a 5-V supply. The digital and analog supplies can be tied together.

The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a

Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down

mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable

to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits

within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD

terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow

DACs A and B to have a different reference voltage than DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The

TLV5627C is characterized for operation from 0

C to 70

C. The TLV5627I is characterized for operation from

– 40

C to 85

1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LDAC

DIN

SCLK

DGND

REFINAB

OUTA

OUTB

OUTC

OUTD

REFINCD

AGND

(TOP VIEW)

D OR PW PACKAGE

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

SOIC

(D)

TSSOP

(PW)

C to 70

TLV5627CD

TLV5627CPW

– 40

C to 85

TLV5627ID

TLV5627IPW

functional block diagram

Power-On

Reset

10-Bit

Data

and

Control

Register

REFINAB

AGND

DIN

DAC A

Serial

Input

Register

8-Bit

DAC

Latch

2-Bit

Control

Data

Latch

Power Down/

Speed Control

OUTA

DAC

Select/

Control

Logic

DAC B

DAC C

DAC D

OUTB

OUTC

OUTD

LDAC

DGND

AVDD

DVDD

REFINCD

SCLK

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

Analog ground

AVDD

Analog supply

Chip select. This terminal is active low.

DGND

Digital ground

DIN

Serial data input

DVDD

Digital supply

Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out

to the TLV5627.

Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.

This terminal is active low.

LDAC

Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into

the serial interface. The DAC outputs are only updated when LDAC is low.

REFINAB

Voltage reference input for DACs A and B.

REFINCD

Voltage reference input for DACs C and D.

SCLK

Serial clock input

OUTA

DAC A output

OUTB

DAC B output

OUTC

DAC C output

OUTD

DAC D output

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, (DV

, AV

to GND)

7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage difference, (AV

to DV

)

–2.8 V to 2.8 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range

–0.3 V to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range

–0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TLV5627C 0

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5627I –40

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

– 65

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage AVDD DVDD

5-V supply

4.5

5.5

Supply voltage, AVDD, DVDD

3-V supply

2.7

3.3

High-level digital input, VIH

DVDD = 2.7 V to 5.5 V

Low-level digital input, VIL

DVDD = 2.7 V to 5.5 V

0.8

Reference voltage V f to REFINAB REFINCD terminal

5-V supply (see Note 1)

2.048

AVDD–1.5

Reference voltage, Vref to REFINAB, REFINCD terminal

3-V supply (see Note 1)

1.024

AVDD–1.5

Load resistance, RL

Ω

Load capacitance, CL

100

Serial clock rate, SCLK

MHz

Operating free air temperature

TLV5627C

Operating free-air temperature

TLV5627I

–40

NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted)

static DAC specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

bits

Integral nonlinearity (INL), end point adjusted

See Note 2

0.3

0.5

LSB

Differential nonlinearity (DNL)

See Note 3

0.03

0.5

LSB

EZS

Zero scale error (offset error at zero scale)

See Note 4

Zero scale error temperature coefficient

See Note 5

ppm/

Gain error

See Note 6

0.6

%of FS

voltage

Gain error temperature coefficient

See Note 7

ppm/

NOTES:

2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal

1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains

constant) as a change in the digital input code.

4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref

106/(Tmax – Tmin).

6. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k

Ω

excluding the effects of the zero-error.

7. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref

106/(Tmax – Tmin).

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued)

individual DAC output specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage output

RL = 10 k

Ω

AVDD–0.1

Output load regulation accuracy

RL = 2 k

Ω

vs 10 k

Ω

0.1

0.25

% of FS

voltage

reference input (REFINAB, REFINCD)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range

See Note 8

AVDD–1.5

Input resistance

Ω

Input capacitance

Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V dc

(see Note 9)

–75

Reference input bandwidth

REFIN = 0 2 V

+ 1 024 V dc

Slow

0.5

MHz

Reference input bandwidth

REFIN = 0.2 Vpp + 1.024 V dc

Fast

MHz

NOTES:

8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

9. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD)

input = 1.024 Vdc + 1 Vpp at 1 kHz.

digital inputs (D0–D11, CS, WEB, LDAC, PD)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI = DVDD

IIL

Low-level digital input current

VI = 0 V

Input capacitance

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

5 V supply No load Clock running

Slow

1.4

2.2

IDD

Power supply current

5-V supply, No load, Clock running

Fast

3.5

5.5

IDD

Power supply current

3 V supply No load Clock running

Slow

1.5

3-V supply, No load, Clock running

Fast

4.5

Power down supply current, See Figure 12

PSRR

Power supply rejection ratio

Zero scale gain

See Notes 10 and 11

– 68

PSRR

Power supply rejection ratio

Gain

See Notes 10 and 11

– 68

10. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5

0.5 V and 3

0.5 V dc, and measuring the

proportion of this signal imposed on the zero-code output voltage.

11. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5

0.5 V and 3

0.5 V dc and measuring the proportion

of this signal imposed on the full-scale output voltage after subtracting the zero scale change.

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued)

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output slew rate

CL = 100 pF, RL = 10 k

Ω

VO 10% to 90%

Fast

Output slew rate

VO = 10% to 90%,

Vref = 2.048 V, 1024 V

Slow

Output settling time

0.1 LSB, CL = 100 pF,

Fast

2.5

Output settling time

RL = 10 k

Ω

, See Notes 12 and 14

Slow

8.5

t ( )

Output settling time code to code

0.1 LSB, CL = 100 pF,

Fast

ts(c)

Output settling time, code to code

RL = 10 k

Ω

, See Notes 13 and 14

Slow

Glitch energy

Code transition from 7F0 to 800

nV-sec

SNR

Signal-to-noise ratio

Sinewave generated by DAC

S/(N+D)

Signal to noise + distortion

Sinewave generated by DAC,

Reference voltage = 1.024 at 3 V and 2.048 at 5 V,

THD

Total harmonic distortion

fs = 400 KSPS, fOUT = 1.1 kHz sinewave,

100 pF

10 k

Ω

20 kHz

–50

SFDR

Spurious free dynamic range

CL = 100 pF, RL = 10 k

Ω

, BW = 20 kHz

NOTES: 12. Settling time is the time for the output signal to remain within

0.1 LSB of the final measured value for a digital input code change

of 0x020 to 0xFF0 or 0xFF0 to 0x020.

13. Settling time is the time for the output signal to remain within

0.1 LSB of the final measured value for a digital input code change

of one count.

14. Limits are ensured by design and characterization, but are not production tested.

digital input timing requirements

MIN

NOM

MAX

UNIT

tsu(CS–FS)

Setup time, CS low before FS

↓

tsu(FS–CK)

Setup time, FS low before first negative SCLK edge

tsu(C16–FS)

Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising

edge of FS

tsu(C16–CS)

Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising

edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup

time is between the FS rising edge and CS rising edge.

twH

Pulse duration, SCLK high

twL

Pulse duration, SCLK low

tsu(D)

Setup time, data ready before SCLK falling edge

th(D)

Hold time, data held valid after SCLK falling edge

twH(FS)

Pulse duration, FS high

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

0.20

0.10

0.05

0.02 0.04 0.1

0.2

0.4

– Output V

oltage – V

0.25

0.30

Load Current – mA

LOAD REGULATION

0.35

0.15

VDD = 5 V,

VREF = 2 V,

VO = Full Scale

5 V Slow Mode, Sink

5 V Fast Mode, Sink

Figure 3

0.10

0.08

0.04

0.01 0.02 0.05

0.1

0.2

0.5

0.16

0.18

LOAD REGULATION

0.20

0.14

0.12

0.06

0.02

– Output V

oltage – V

Load Current – mA

VDD = 3 V,

VREF = 1 V,

VO = Full Scale

3 V Slow Mode, Sink

3 V Fast Mode, Sink

Figure 4

3.994

3.99

3.986

3.984

0.02 0.04 0.1

0.2

0.4

3.996

4.00

LOAD REGULATION

4.002

3.998

3.992

3.988

– Output V

oltage – V

Load Current – mA

VDD = 5 V,

VREF = 2 V,

VO = Full Scale

5 V Slow Mode, Source

5 V Fast Mode, Source

Figure 5

2.001

1.999

0.01 0.02 0.05

0.1

0.2

0.5

2.002

LOAD REGULATION

2.003

2.001

– Output V

oltage – V

Load Current – mA

VDD = 3 V,

VREF = 1 V,

VO = Full Scale

3 V Slow Mode, Source

3 V Fast Mode, Source

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS232 – JUNE1999

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

2.5

1.5

0.5

–55

–40

–25

– Supply Current – mA

3.5

SUPPLY CURRENT

TEMPERATURE

125

T – Temperature –

I DD

Fast Mode

Slow Mode

VDD = 3 V,

VREF = 1.024 V,

VO = Full Scale

Figure 7

2.5

1.5

0.5

–55

–40

–25

– Supply Current – mA

3.5

SUPPLY CURRENT

TEMPERATURE

125

T – Temperature –

I DD

Fast Mode

Slow Mode

VDD = 5 V,

VREF = 1.024 V,

VO = Full Scale

Figure 8

––40

–50

–70

–80

THD

–

otal Harmonic Distortion – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION

FREQUENCY

100

–20

–60

Vref = 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Fast Mode

Figure 9

––40

–50

–70

–80

THD

–

otal Harmonic Distortion – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION

FREQUENCY

100

–20

–60

Vref = 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Slow Mode