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DS97LVO0900

P R E L I M I N A R Y

6-1

RODUCT

PECIFICATION

Z86C72/C92/L72/L92

IR M

ICROCONTROLLER

FEATURES

Expanded Register File Control Registers

Low Power Consumption - 40 mW (typical)

Three Standby Modes:

–

STOP

–

HALT

–

Low Voltage

Automatic External ROM Access Beyond 16K

(Z86LX2/C72 Version)

Special Architecture to Automate Both Generation and

Reception of Complex Pulses or Signals:

–

One Programmable 8-Bit Counter/Timer with Two

Capture Register

–

One Programmable 16-Bit Counter/Timer with

One Capture Register

–

Programmable Input Glitch Filter for Pulse

Reception

Five Priority Interrupts

–

Three External

–

Two Assigned to Counter/Timers

Low Voltage Detection and Standby Mode

Programmable Watch-Dog/Power-On Reset Circuits

Two Independent Comparators with Programmable

Interrupt Polarity

On-Chip Oscillator that Accepts a Crystal, Ceramic

Resonator, LC, RC (mask option), or External Clock

Drive

Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3

–

All Eight Port 2 Bits at one time or Not

–

Pull-Ups Automatically Disabled Upon Selecting

Individual Pins as Outputs

Maskable Mouse/Trackball Interface on P00 Through

P03 is available on the L72 version.

32 kHz Oscillator Mask Option

GENERAL DESCRIPTION

The Z86LX2/CX2 family of IR (Infrared) are ROM/ROM-

less-based members of the Z8

MCU single-chip micro-

controller family with 768 bytes of internal RAM. The differ-

entiating factor between these devices is the availability of

RAM, ROM and package options. The use of external

memory enables these Z8 microcontrollers to be used

where code flexibility is required. Offering the 5V versions

(Z86CXX) and gives optimum performance in both the low

and high voltage ranges. Zilog's CMOS microcontrollers

offer fast execution, efficient use of memory, sophisticated

interrupts, input/output bit manipulation capabilities, auto-

mated pulse generation/reception, and internal key-scan

pull-up resistors. The Z86LX2/CX2 product line offers easy

hardware/software system expansion with cost-effective

and low power consumption.

The Z86LX2/CX2 architecture is based on Zilog's 8-bit mi-

crocontroller core with an Expanded Register File to allow

Part

ROM

(KB)

RAM*

(Bytes)

I/O

Voltage Range

Z86C72

748

4.5V to 5.5V

Z86C92

748

4.5V to 5.5V

Z86L72

748

2.0V to 3.9V

Z86L92

748

2.0V to 3.9V

Note:

*General-Purpose

Z86C72/C92/L72/L92

IR Microcontroller

Zilog

6-2

P R E L I M I N A R Y

DS97LVO0900

GENERAL DESCRIPTION

(Continued)

access to register mapped peripherals, I/O circuits, and

powerful counter/timer circuitry. The Z86C72/C92/L72/L92

offers a flexible I/O scheme, an efficient register and ad-

dress space structure, and a number of ancillary features

that are useful in many consumer, automotive, computer

peripheral, and battery operated hand-held applications.

Many applications demand powerful I/O capabilities. The

Z86LX2/CX2 family fulfills this with three package options

in which the L72 version provides 31 pins of dedicated in-

put and output. These lines are grouped into four ports.

Each port consists of eight lines (Port 3 has seven lines)

and is configurable under software control to provide tim-

ing, status signals, parallel I/O with or without handshake,

and an address/data bus for interfacing external memory.

There are five basic address spaces available to support a

wide range of configurations: Program Memory, Register

File, Expanded Register File, Extended Data RAM and Ex-

ternal Memory. The register file is composed of 256 bytes

of RAM. It includes four I/O port registers, 16 control and

status registers and the rest are General-Purpose regis-

ters. The Extended Data RAM adds 512 bytes of usable

general-purpose registers. The Expanded Register FIle

consists of two additional register groups (F and D).

To unburden the program from coping with such real-time

problems as generating complex waveforms or receiving

and demodulating complex waveform/pulses, the

Z86LX2/CX2 family offers a new intelligent counter/timer

architecture with 8-bit and 16-bit counter/timers (Figure 1).

Also included are a large number of user-selectable

modes, and two on-board comparators to process analog

signals with separate reference voltages (Figure 2).

Figure 1. Counter/Timer Block Diagram

HI16

LO16

16-Bit

T16

TC16H

TC16L

HI8

LO8

And/Or

Logic

Clock

Divider

Glitch

Filter

Edge

Detect

Circuit

8-Bit

TC8H

TC8L

Input

SCLK

2 4

Timer 16

Timer 8/16

Timer 8

Z86C72/C92/L72/L92

Zilog

IR Microcontroller

DS97LVO0900

P R E L I M I N A R Y

6-3

Note:

All Signals with a preceding front slash, "/", are ac-

tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is

active Low, only).

Power connections follow conventional descriptions be-

low:

Figure 2. Functional Block Diagram

Port 0

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P31

P32

P33

/AS

/DS

R/W

/RESET

Port 3

Port 1

Port 2

256 x 8-Bit

ROM

16K/0K x 8

Z8 Core

Internal

Address Bus

Internal Data Bus

Expanded

File

512 x 8-Bit

Expanded

Counter/Timer 8

8-Bit

Counter/Timer 16

16-Bit

Machine

Timing

Instruction

Control

Power

XTAL

VDD

VSS

P34

P35

P36

P37

Connection

Circuit

Device

Power

Ground

GND

Z86C72/C92/L72/L92

IR Microcontroller

Zilog

6-4

P R E L I M I N A R Y

DS97LVO0900

PIN DESCRIPTION

Figure 3. 40-Pin DIP Pin Assignments

R//W

P25

P26

P27

P04

P05

P06

P14

P15

P07

VDD

P16

P17

XTAL2

XTAL1

P31

P32

P33

P34

/AS

/DS

P24

P23

P22

P21

P20

P03

P13

P12

VSS

P02

P11

P10

P01

P00

Pref1

P36

P37

P35

/RESET

Z86C72/C92

Z86L72/L92

DIP

Figure 4. 44-Pin PLCC Pin Assignments

Z86C72/C92

Z86L72/L92

PLCC

P21

P22

P23

P24

/DS

R//RL

R//W

P25

P26

P27

P04

Pref1

P36

P37

P35

/RESET

VSS

/AS

P34

P33

P32

P31

P05

P06

P14

P15

P07

VDD

P16

P17

AL2

AL1

P20

P03

P13

P12

VSS

P02

P11

P10

P01

P00

Z86C72/C92/L72/L92

IR Microcontroller

Zilog

6-6

P R E L I M I N A R Y

DS97LVO0900

PIN DESCRIPTION

(Continued)

Table 1. Pin Identiﬁcation

40-Pin

DIP #

44-Pin

PLCC

44-Pin

QFP#

Symbol

Direction

Description

P00

P01

P02

P03

P04

P05

P06

P07

Input/Output

Port 0 is Nibble Programmable

Port 0 can be conﬁgured as A15-A8

external program ROM/DATA Address

Bus.

Port 0 can be conﬁgured as a

mouse/trackball input.

P10

P11

P12

P13

P14

P15

P16

P17

Input/Output

Port 1 is byte programmable

Port 1 can be conﬁgured as multiplexed

A7-A0/D7-D0 external program ROM

Address/Data Bus.

P20

P21

P22

P23

P24

P25

P26

P27

Input/Output

Port 2 pins are individually conﬁgurable

as input or output.

P31

P32

P33

P34

P35

P36

P37

Input

Output

IRQ2/Modulator Input

IRQ0

IRQ1

T8 output

T16 output

T8/T16 output

23,24

1,2,34

6,7

17,28,29

/AS

/DS

R//W

/RESET

XTAL1

XTAL2

Pref1

R//RL

Output

Input

Output

Input

Address Strobe

Data Strobe

Read/Write

Reset

Crystal, Oscillator Clock

Power Supply

Ground

Comparator 1 Reference

ROM/ROMless

Z86C72/C92/L72/L92

Zilog

IR Microcontroller

DS97LVO0900

P R E L I M I N A R Y

6-7

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; operation of the device at

any condition above those indicated in the operational sec-

tions of these specifications is not implied. Exposure to ab-

solute maximum rating conditions for an extended period

may affect device reliability.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test

conditions as noted. All voltages are referenced to GND.

Positive current flows into the referenced pin (Figure 6).

CAPACITANCE

= 25

C, V

= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

Symbol

Description

Min

Max

Units

Supply Voltage (*)

-0.3

+7.0

STG

Storage Temp.

-65

+150

Oper. Ambient

Temp.

†

Notes:

* Voltage on all pins with respect to GND

† See Ordering Information

Figure 6. Test Load Diagram

From Output

Under Test

150 pF

Parameter

Max

Input capacitance

12 pF

Output capacitance

12 pF

I/O capacitance

12 pF

Z86C72/C92/L72/L92

IR Microcontroller

Zilog

6-8

P R E L I M I N A R Y

DS97LVO0900

DC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)

Preliminary

= 0

C to +70

Typ @

Sym

Parameter

Min

Max

Units

Conditions

Notes

Max Input Voltage 2.0V

3.9V

<250

Clock Input

High Voltage

2.0V

3.9V

0.8 V

+ 0.3

Driven by External

Clock Generator

Driven by External

Clock Generator

Clock Input

Low Voltage

2.0V

3.9V

– 0.3

0.2 V

Driven by External

Clock Generator

Driven by External

Clock Generator

Input High Voltage 2.0V

3.9V

0.7 V

+ 0.3

0.5V

Input Low Voltage 2.0V

3.9V

– 0.3

0.2 V

0.5V

OH1

Output High

Voltage

2.0V

3.9V

– 0.4

1.7

3.7

= –0.5 mA

OH2

Output High

Voltage (P36,

P37,P00, P01)

2.0V

3.9V

- 0.8

= –7 mA

Z86C72/C92/L72/L92

Zilog

IR Microcontroller

DS97LVO0900

P R E L I M I N A R Y

6-9

OL1

Output Low

Voltage

2.0V

3.9V

0.4

0.1

0.2

= 1.0 mA

= 4.0 mA

OL2*

Output Low

Voltage

2.0V

3.9V

0.8

0.5

0.3

= 5.0 mA

= 7.0 mA

OL2

Output Low

Voltage(P36,

P37,P00,P01)

2.0V

3.9V

0.8

0.3

0.2

= 10 mA

Reset Input

High Voltage

2.0V

3.9V

0.8 V

1.5

2.0

Reset Input

Low Voltage

2.0V

3.9V

– 0.3

0.2 V

0.5

0.9</