1
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
P
RELIMINARY
P
RODUCT
S
PECIFICATION
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
FEATURES
s
Enhanced Z8S180 MPU
s
Four Z80
CTC Channels
s
One Channel ESCC
™
Controller
s
Two 8-Bit Parallel I/O Ports
s
Bidirectional Centronics Interface (IEEE 1284)
s
Low-EMI Option
ROM
UART
Speed
Part
(KB)
Baud Rate
(MHz)
Z80185
32 x 8
512 Kbps
20, 33
Z80195
0
512 Kbps
20, 33
s
100-Pin QFP Package
s
5.0-Volt Operating Range
s
Low-Power Consumption
s
0
°
C to +70
°
C Temperature Range
GENERAL DESCRIPTION
The Z80185 and Z80195 are smart peripheral controller
devices designed for general data communications appli-
cations, and architected specifically to accommodate all
input and output (I/O) requirements for serial and parallel
connectivity. Combining a high-performance CPU core
with a variety of system and I/O resources, the Z80185/195
are useful in a broad range of applications. The Z80195 is
the ROMless version of the device.
The Z80185 and Z80195 feature an enhanced Z8S180
microprocessor linked with one enhanced channel of the
Z85230 ESCC
™
serial communications controller, and 25
bits of parallel I/O, allowing software code compatibility
with existing software code.
Seventeen lines can be configured as bidirectional
Centronics (IEEE 1284) controllers. When configured as a
1284 controller, an I/O line can operate in either the host or
peripheral role in compatible, nibble, byte or ECP mode. In
addition, the Z80185 includes 32 Kbytes of on-chip ROM.
These devices are well-suited for external modems using
a parallel interface, protocol translators, and cost-effective
WAN adapters. The Z80185/195 is ideal for handling all
laser printer I/O, as well as the main processor in cost-
effective printer applications.
Notes:
All Signals with a preceding front slash, "/", are active Low.
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
2
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
Processor
Power Controller
Parallel Ports (2)
Including IEEE
Bidirectional
Centronics Controller
16-Bit Programmable
Reload Timers (2)
UARTs (2)
ROM
32K x 8
(Z80185 Only)
DMACs (2)
EMSCC
Decode
CTCs (4)
16-Bit Address Bus
8-Bit Data Bus
/ROMCS
/RAMCS
MMU
A19-0
TxD,
RxD
TOUT
CLK/TRG
ZC/TO
TXA1-0,
RXA1-0
TIMING DIAGRAMS
(Continued)
Figure 1. Z80185/195 Functional Block Diagram
3
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
/BUSREQ
/BUSACK
NSTROBE
NACK
NAUTOFD
TOUT//DREQ
BUSY
NINIT
RXA1
/INT0
/NMI
/RESET
/W
AIT
EXT
AL
VSS
A17
PHI
/RD
/WR
/M1
NF
AUL
T
/MREQ
/IORQ
XT
AL
/RFSH
VDD
/HAL
T
Z80185/Z80195
100-Pin QFP
/INT1
/INT2
ST
A0
A1
A2
A3
A15
A4
A5
A6
A7
A8
A9
A11
A12
VSS
A13
A14
A16
D0
D1
D2
D3
D4
D5
D7
/RAMCS
/IOCS
TXA1
CKA0/CKS
RXA0
TXA0
/DCD0/CKA1
/CTS0/RXS
/RTS0/TXS
A18
A19
VSS
IEI
/ROMCS
IEO
VSS
/DCD
/CTS
/RTS
/DTR
TXD
/TRXC
RXD
PERROR
100
1
95
5
10
15
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
D6
A10
PIA10/CLKTRG0
PIA1
1/CLKTRG1
PIA12/CLKTRG2
PIA13/CLKTRG3
PIA14/ZCT
O0
PIA15/ZCT
O1
PIA16/ZCT
O2
SELECT
VSS
PIA21
PIA22
PIA23
PIA24
PIA25
PIA26
PIA27
/R
TXC
NSELECTIN
PIA20
VDD
PIN DESCRIPTION
Figure 2. 100-Pin QFP Pin Assignments
4
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
1.4 V
I
OH
100 pF
OL
I
= 2 mA
= 250
µ
A
ABSOLUTE MAXIMUM RATINGS
Symbol Description
Min
Max
Units
V
CC
Supply Voltage
–0.3
+7.0
V
V
IN
Input Voltage
–0.3
V
CC
+0.3
V
T
OPR
Operating Temp.
0
70
°
C
T
STG
Storage Temp.
–55
+150
°
C
Notes:
Voltage on all pins with respect to GND. Permanent LSI damage may
occur if maximum ratings are exceeded. Normal operation should be
recommended operating conditions. If these conditions are exceeded, it
could affect reliability of LSI.
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
STANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND (0V).
Positive current flows into the referenced pin (Test Load).
Operating Temperature Range:
S = 0
°
C to 70
°
C
Voltage Supply Range:
+4.5V
≤
V
CC
≤
+5.5V
All AC parameters assume a load capacitance of 100 pF.
Add 10 ns delay for each 50 pF increase in load up to a
maximum of 150 pF for the data bus and 100 pF for
address and control lines. AC timing measurements are
referenced to 1.5 volts (except for clock, which is refer-
enced to the 10% and 90% points). Maximum capacitive
load for PHI is 125 pF.
Figure 3. Test Load Diagram
5
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
DC CHARACTERISTICS
V
DD
= 5.0V
±
10%, V
SS
= 0V over specified temperature range, unless otherwise noted.
Symbol
Item
Condition
Min.
Typ.
Max.
Unit
V
IH
Input “H” Voltage
†
V
V
IL
Input “L” Voltage
†
V
V
OH
Output “H” Voltage
†
V
V
OL1
Output “L” Voltage
†
V
I
IL
Input Leakage
V
IN
=0.5 to
Current All Inputs
V
DD
–0.5
1.0
Except XTAL,EXTAL
µ
A
I
TL
Tri-State Leakage
V
IN
=0.5 to
Current
V
DD
–0.5
1.0
µ
A
V
DD
Supply Current*
Normal Operation
For 5.0V:
f = 20 MHz
60
120
mA
For 5.0V:
f = 33 MHz
68
132
mA
I
CC
*
Power Dissipation*
System Stop Mode
For 5.0V:
f = 20 MHz
5
10
mA
For 5.0V:
f = 33 MHz
7
13
mA
Notes:
† See Class Reference Table
* V
IH
min = V
DD
–1.0V, V
IL
max = 0.8V (All output terminals are at no load.)
6
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
TIMING DIAGRAMS
Z8S180 MPU Timing
Figure 4. CPU Timing
(Opcode Fetch Cycle, Memory Read/Write Cycle
I/O Read/Write Cycle)
ø
Address
Opcode Fetch Cycle
T1
T2
TW
T3
T1
T2
TW
T3
T1
I/O Write Cycle †
I/O Read Cycle †
/WAIT
/MREQ
6
1
3
2
4
5
19
20
19
20
7
8
12
11
7
11
29
/IORQ
13
11
13
9
/RD
/WR
22
26 and 26a
25
11
10
14
18
/M1
17
ST
Data
IN
Data
OUT
/RESET
15
16
15
16
27
21
23
24
48
49
54
53
48
49
54
53
28a
28b
9a
9b
7
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
Ø
32
31
33
30
15
16
39
40
41
42
34
35
35
34
37
36
38
38
43
[3]
/INTI
/NMI
/M1 [1]
/IORQ [1]
/Data IN [1]
/MREQ [2]
/RFSH [2]
/BUSREQ
/BUSACK
Address
Data /MREQ,
/RD, /WR,
/IORQ
/HALT
44
Notes:
[1] During /INT0 acknowledge cycle
[2] During refresh cycle
[3] Output buffer is off at this point
[4] Refer to Table C, parameter 7
Figure 5. CPU Timing
(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE mode
HALT mode, SLEEP mode, SYSTEM STOP mode)
TIMING DIAGRAMS
(Continued)
8
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
0
Address
/IROQ
T1
T2
TW
T3
T1
13
25
9
/RD
/WR
T2
TW
T3
I/O Read Cycle
I/O Write Cycle
28
29
28
29
22
Ø
45
46
45
45
17
18
CPU or DMA Read/Write Cycle
T1
T2
Tw
T3
T1
[3]
[4]
[2]
[1]
TOUT//DREQ
(At level
sense)
TOUT//DREQ
(At edge
sence)
ST
DMA Control Signals
[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
Figure 6. CPU Timing
Figure 7. DMA Control Signals
9
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
Ø
47
TOUT/DREQ
Timer Data
Reg = 0000H
Ø
T3
T1
T2
TS
TS
T1
T2
32
31
33
43
44
/INTi
/NMI
A18-A0
/MREQ, /M1
/RD
/HALT
SLP Instruction Fetch
Next Opcode Fetch
TIMING DIAGRAMS
(Continued)
Figure 9. SLEEP Execution Cycle
Figure 8. Timer Output Timing
10
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
CSI/O Clock
58
58
60
59
60
59
62
61
61
62
11.5 tcyc
11 tcyc
11 tcyc
11.5 tcyc
16.5 tcyc
16.5 tcyc
57
57
Transmit Data
(Internal Clock)
Transmit Data
(External Clock)
Receive Data
(Internal Clock)
Receive Data
(External Clock)
Figure 10. CSI/O Receive/Transmit Timing
11
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
/MREQ
63
64
/RAMCS
/ROMCS
/IORQ
/IOCS
56
55
EXTAL
VIL1
51
52
VIH1
VIL1
VIH1
TIMING DIAGRAMS
(Continued)
Figure 11. /ROMCS and /RAMCS Timing
Figure 12. External Clock Rise Time
and Fall Time
Figure 13. Input Rise and Fall Time
(Except EXTAL, /RESET)
12
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLERS
DS971850301
Zilog
AC CHARACTERISTICS
V
DD
= 5V
±
10%, V
SS
= 0V, CL = 50 pF for outputs over
specified temperature range, unless otherwise noted.
Z80185 / Z80195
Z80185 / Z80195
(20 MHz)
(33 MHz)
No.
Symbol Parameter
Min
Max
Min
Max
Units
1
tcy
Clock Cycle Time
50
(DC)
33
(DC)
ns
2
tCHW
Clock “H” Pulse Width
15
10
ns
3
tCLW
Clock “L” Pulse Width
15
10
ns
4
tcf
Clock Fall Time
10
5
ns
5
tcr
Clock Rise Time
10
5
ns
6
tAD
PHI Rising to Address Valid
30
15
ns
7
tAS
Address Valid to (MREQ Falling or IORQ Falling)
5
5
ns
8
tMED1
PHI Falling to MREQ Falling Delay
25
15
ns
9a
tRDD1
PHI Falling to RD Falling Delay (IOC=1)
25
15
ns
9b
tRDD1
PHI Rising to RD Falling Delay (IOC=0)
25
15
ns
10
tM1D1
PHI Rising to M1 Falling Delay
35
15
ns
11
tAH
Address Hold Time from (MREQ, IOREQ, RD, WR)
5
5
ns
12
tMED2
PHI Falling to MREQ Rising Delay
25
15
ns
13
tRDD2
PHI Falling to RD Rising Delay
25
15
ns
14
tM1D2
PHI Rising to M1 Rising Delay
40
15
ns
15
tDRS
Data Read Setup Time
10
5
ns
16
tDRH
Data Read Hold Time
0
0
ns
17
tSTD1
PHI Falling to ST Falling Delay
30
15
ns
18
tSTD2
PHI Falling to ST Rising Delay
30
15
ns
19
tWS
WAIT Setup Time to PHI Falling
15
10
ns
20
tWH
WAIT Hold Time from PHI Falling
10
5
ns
21
tWDZ
PHI Rising to Data Float Display
35
20
ns
22
tWRD1
PHI Rising to WR Falling Delay
25
15
ns
23
tWDD
PHI Rising to Write Data Delay Time
25
15
ns
24
tWDS
Write Data Setup Time to WR Falling
10
10
ns
25
tWRD2
PHI Falling to WR Rising Delay
25
15
ns
26
tWRP
Write Pulse Width (Memory Write Cycle)
75
45
ns
26a
tWRP
Write Pulse Width (I/O Write Cycle)
130
70
ns
27
WDH
Write Data Hold Time From (WR Rising)
10
5
ns
Notes:
Specifications 1 through 5 refer to an external clock input on EXTAL, and
provisionally to PHI clock output. When a quartz crystal is used with the
on-chip oscillator, a lower maximum frequency than that implied by spec.
#1 may apply.
13
P R E L I M I N A R Y
Z80185/Z80195
S
MART
P
ERIPHERAL
C
ONTROLLES
DS971850301
Zilog
AC CHARACTERISTICS
(Continued)
Z80185 / Z80195
Z80185 / Z80195
(20 MHz)
(33 MHz)
No.
Symbol Parameter
Min
Max
Min
Max
Units
28a
tIOD
PHI Falling to IORQ Falling Delay IOC = 1)
25
15
ns
28b
tIOD
PHI Rising to IORQ Fallin g Delay (IOC =0)
25
15
ns
29
tIOD2
PHI Falling to IORQ Rising Delay
25
15
ns
30
tIOD3
M1 Falling to IORQ Falling Delay
100
80
ns
31
tINTS
INT Setup Time to PHI Falling
20
15
ns
32
tINTH
INT Hold Time from PHI Falling
10
10
ns
33
tNMIW
NMI Pulse Width
35
25
ns
34
tBRS
BUSREQ Setup Time to PHI Falling
10
10
ns
35
tBRH
BUSREQ Hold Time from PHI Falling
10
10
ns
36
tBAD1
PHI Rising to BUSACK Falling Delay
25
15
ns
37
tBAD2
PHI Falling to BUSACK Rising Delay
25
15
ns
38
tBZD
PHI Rising to Bus Floating Delay Time
40
30
ns
39
tMEWH
MREQ Pulse Width (High)
tcy –15
tcy –10
ns
40
tMEWL
MREQ Pulse Width (Low)
2tcy –15
2tcy–10
ns
41
tRFD1
PHI Rising to RFSH Falling Delay
20
15
ns
42
tRFD2
PHI Rising to RFSH Rising Delay
20
15
ns
43
tHAD1
PHI Rising to HALT Falling Delay
15
15
ns
44
tHAD2
PHI Rising to HALT Rising Delay
15
15
ns
45
tDRQS
DREQ Setup Time to PHI Rising
20
15
ns
46
tDRQH
DREQ Hold Time from PHI Rising
20
15
ns
47
tTOD
PHI Falling to Timer Output Delay
75
50
ns
48
tRES
RESET Setup Time to PHI Falling
40
25
ns
49
tREH
RESET Hold Time From PHI Falling
25
15
ns
50
tOSC
Oscillator Stabilization Time
20
20
ms
51
tEXr
External Clock Rise Time (EXTAL)
10
5
ns
52
tEXf