DS96TEL0200
1
1
P
RELIMINARY
P
RODUCT
S
PECIFICATION
FEATURES
s
Complete Stand-Alone Line 21 Decoder for Closed-
Captions and Extended Data Services (XDS).
s
Preprogrammed to Provide Full Compliance with EIA-
608 Specifications for Extended Data Services.
s
Automatic Extraction and Serial Output of Special
XDS Packets such as Time of Day, Local Time Zone,
and Program Rating (
V-Chip
).
s
Cost-Effective Solution for NTSC Violence Blocking
inside Picture-in-Picture (PiP) Windows.
s
Minimal Communications and Control Overhead
Provides Simple Implementation of Violence Block,
Closed Caption, and Auto Clock Set Features.
s
Programmable, Full Screen On-Screen Display (OSD)
for Creating OSD or Captions inside a Picture-in-
Picture (PiP) Window (Z86129 only).
s
I
2
C Serial Data and Control Communication
s
User-Programmable Horizontal Display Position for
easy OSD Centering and Adjustment (Z86129 only).
GENERAL DESCRIPTION
The Z86129/130/131 is a stand-alone integrated circuit,
capable of processing Vertical Blanking Interval (VBI) data
from both fields of the video frame in data conforming to
the transmission format defined in the Television Decoder
Circuits Act of 1990 and in accordance with the Electronics
Industry Association specification 608 (EIA-608).
The Line 21 data stream can consist of data from several
data channels multiplexed together. Field 1 has four data
channels, two Captions and two Text. Field 2 has five
additional data channels, two Captions, two Text and
Extended Data Services (XDS). XDS data structure is
defined in EIA-608. The Z86129 can recover and display
data transmitted on any of these nine data channels. The
Z86130 and Z86131 are derivatives of the Z86129 which
can recover XDS data and output the recovered data via
the serial port. The Z86130 and Z86131 do not have OSD
capability, but are ideally suited for Line 21 data slicer
applications.
The Z86129/130/131 can recover and output to a host
processor via the I
2
C serial bus any XDS data packet
defined in EIA-608. On-chip XDS filters are fully
programmable, enabling recovery of only those XDS data
packets selected by the user, making the Z86129/130 an
ideal choice for implementing NTSC Violence Block. The
Z86131 is designed especially for extracting XDS time
information for Automatic Clock-Set features in TVs,
VCRs, and Set-Top boxes.
In addition, the Z86129/130 is ideally suited to monitor Line
21 of video displayed in a PiP window for violence blocking
purposes. A block diagram of the Z86129/130/131 is
shown in Figure 1.
Z86129/130/131
1
NTSC L
INE
21 D
ECODER
Speed
Pin Count/
Standard
On-Screen Display
Automatic Data Extraction
Devices
(MHz)
Package Types
Temp. Range
& Closed Captioning
V-Chip
Time of Day
Z86129
12
18-Pin DIP, SOIC
0
°
to +70
°
C
Yes
Yes
Yes
Z86130
12
18-Pin DIP, SOIC
0
°
to +70
°
C
No
Yes
Yes
Z86131
12
18-Pin DIP, SOIC
0
°
to +70
°
C
No
No
Yes
Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
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DS96TEL0200
GENERAL DESCRIPTION
(Continued)
Figure 1. Z86129 Block Diagram
Video
7
Buffer
VW
Data
Slicer
Data CLK
Recovery
Sliced
Data
Data Line
Data Bus
Dual
Clamp
Lock
SIG
SYNC
Slicer
PG
CSYNC
Digital
II Lock
FEW
AW
VIN/
Intro
Serial
Control Port
Status Reg
Test Reg
Slice Level
CG
Logic
PH1
PH2
FR
I Drive
OSC
O/S
& MUX
Control
CG Lines
MSYNC
COMP SYNC
5
HIN
9
LPF
Loop
1
Filter
DOT CLK
DIV
Line &
CHAR
CIR
V Lock
Field
FLD
LS
SFLD
SLS
Control
CHAR CLK
CW
Line & Fld
Decodes
MSGR
DOT CLK
SMS
SEN
SCK
SDA
SDO
6
4
15
14
16
13
VDD
+5V
12
11
Vss
Vss(A)
RREF
POR
CKT
4
10
Command Processor
Row
Address
MUX
Display
RAM
Character Generator
Row Latch
Display
Latch
SS CTR
Output
Logic
10
6
8
13
4
FLD
V/I
Ref
RED
GREEN
BLUE
BOX
17
3
2
18
Addr Bus
ADDR
DEC
ADDR
Decoder
8
Z86129 only
Z86129/130/131
P R E L I M I N A R Y
NTSC Line 21 Decoder
DS96TEL0200
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PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Figure 2. Z86129/130/131, 18-Pin DIP/SOIC
Pin Configuration
1
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
18
V
SS
GREEN*
BLUE*
SEN
HIN
SMS
VIDEO
CSYNC
LPF
RED*
BOX*
SDO
SCK
SDA
VIN/INTRO
V
DD
V
SS
(A)
RREF
*Z86129 Only
Table 1. 18-Pin DIP and SOIC Pin Identification
No. Symbol
Function
Direction
1
V
SS
Power Supply GND
2*
GREEN
Video Output
Output
3*
BLUE
Video Output
Output
4
SEN
Serial Enable
Input
5
HIN
Horizontal In
Input
6
SMS
Serial Mode Select
Input
7
VIDEO
Composite Video
Input
8
CSYNC
Composite Sync
Output
9
LPF
Loop Filter
Output
10 RREF
Resistor Reference
Input
11 V
SS
(A)
Pwr. Supply (Analog) GND
12 V
DD
Power Supply
13 VIN/INTRO Vertical In/Interrupt Out
In/Output
14 SDA
Serial Data
In/Output
15 SCK
Serial Clock
Input
16 SDO
Serial Data Out
Output
17* BOX
OSD Timing Signal
Output
18* RED
Video Output
Output
Note:
DIP and SOIC pin configuration are identical. *However,
the Z86130/Z86131 do not have signals on pins 2, 3, 18 and 19.
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
–0.5 to 6.0
V
V
IN
DC Input Voltage
–0.5 to V
DD
+0.5
V
V
OUT
DC Output Voltage
–0.5 to V
DD
+0.5
V
I
IN
CAUTION:
DC Input Current per Pin
+10
mA
I
OUT
DC Output Current per Pin
+20
mA
I
DD
DC Supply Current
+30
mA
P
D
Power Dissipation per Device
300
mW
T
STG
Storage Temperature
–65 to +150
°
C
T
L
Lead Temperature, 1 mm from Case for 10 seconds
260
°
C
Notes:
Voltages referenced to V
SS
(A) and V
SS
.
Maximum ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits specified in the DC and AC Characteristics tables or Pin Description section.
Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
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DS96TEL0200
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Figure 3).
DC ELECTRICAL CHARACTERISTICS
Note:
T
A
= 0
°
C to +70
°
C; V
DD
= +4.75V to +5.25V
AC AND TIMING CHARACTERISTICS
Composite Video Input
Figure 3. Standard Test Load
From Output
Under Test
150 pF
250
µ
A
2.1 k
Ω
+5V
Symbol
Parameter
Conditions
Min.
Max.
Unit
V
IL
Input Voltage Low
0
0.2 V
DD
V
V
IH
Input Voltage High
0.7 V
DD
V
DD
V
V
OL
Output Voltage Low
I
OL
= 1.00 mA
–
0.4
V
V
OH
Output Voltage High
I
OH
= 0.75 mA
V
DD
–0.4V
–
V
I
IL
Input Leakage
0V, V
DD
–3.0
3.0
µ
A
I
DD
Supply Current
Estimated*
30
mA
K
φ
VCO Gain
–
TBD
MHz/V
I
LP
Loop Filter Current
–
TBD
mA
Note:
*Not guaranteed
Parameter
Conditions
Amplitude
1.0V p-p
±
3 dB
Polarity
Sync tips negative
Bandwidth
600 kHz
Signal Type
Interlaced
Max Input R
470 ohms
DC Offset
Signal to be AC coupled with a minimum series capacitance of 0.1
µ
F
Z86129/130/131
P R E L I M I N A R Y
NTSC Line 21 Decoder
DS96TEL0200
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ELECTRICAL CHARACTERISTICS
Non Standard Video Signals must have the following characteristics:
Horizontal Signal Input (preferably H Flyback)
Line 21 Input Parameters (at 1.0V p-p)
Note:
Line 21 must be in its proper position to the leading edge of the Vertical Sync signal.
Timing Signals
Parameter
Conditions
Sync Amplitude
200 mV minimum
Vertical Pulse Width
3H
±
0.5H
Vertical Pulse Tilt
20 mV maximum
H Timing
Phase Step (Head Switch)
±
10
µ
s maximum
Fh Deviation (long term)
±
0.5% maximum
Fh p-p Deviation (short term)
±
0.3% maximum
Vertical Sync Signal
The internal sync circuits will lock to all 525 or 625 line signals having a vertical
sync pulse that meets the following conditions:
1.
It is at least 2H wide.
2.
It starts at the proper 2H boundary for its field.
3.
If equalizing pulse serrations are present, they must be less than 0.125H in
width.
Minimum Signal-to-Noise
The Z86129/130/131 will function down to a 25 dB signal-to-noise ratio (CCIR
weighted) with one error per row or better at that level.
Ratio to Composite Video
Input
Parameter
Conditions
Amplitude
CMOS level signal where Low <= 0.2 V
CC
Video Lock Mode:
Polarity
Frequency
Any
15,734.263 Hz
±
3%
HIN Lock Mode:
Polarity
Frequency
Any
Same as Display Horizontal Flyback Pulse (HFB) pulse
Parameter
Conditions
Cod Amplitude
50 IRE
Code Zero Level
5 IRE, +15 IRE relative to Back Porch
Start of Code
10.5
±
0.5
µ
s, (Measured from the midpoint of the falling edge of the last clock run-in cycle
to the midpoint of the rising edge of the start bit.)
Start of Data
3.972
µ
s, –0.00
µ
sec, +0.30
µ
s (Measured from the midpoint of the falling edge of the last
clock run-in cycle to the midpoint of the rising edge of the start bit.
Parameter
Conditions
Dot
768 x FH = 12.0839 MHz
Dot Period
82.75 ns
Character Cell Width
1.324
µ
s (tH/48)
Width of Row (Box)
45.018
µ
s (34 chars = 17/24 x tH
Width of Row (Char)
42.370
µ
s (32 chars = 2/3 x tH
Horizontal Display Timing
The timing of the output signals Box and RGB have been set to make a centered display.
The positioning of these outputs can be adjusted in 330 ns increments by writing a new
value to the Z86129 H Position Register (Address = 02h).
Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
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DS96TEL0200
PIN DESCRIPTIONS
Inputs
VIDEO (Pin 7). Composite NTSC video input, 1.0V p-p
(nom), band limited to 600 kHz. Circuit will operate with
signal variation between 0.7-1.4V p-p. The polarity is sync
tips negative. This signal pin should be AC coupled
through a 0.1
µ
F capacitor and driven by a source
impedance of 470 ohms or less.
HIN (Pin 5). Horizontal sync input at CMOS levels. When
the device is used in the VIDEO LOCK mode, this signal
pulls the on-chip VCO within the proper range. The circuit
uses the frequency of this signal which must be within
±
3%
Fh but can be of either polarity. When used in the H LOCK
mode, the VCO phase locks to the rising edge of this
signal. The HPOL bit of the H Position register can be set
to operate with either polarity of input signal. This is usually
the H Flyback signal. The timing difference between HIN
rising edge and the leading edge of composite sync (of
VIDEO input) is one of the factors which will affect the
horizontal position of the display. Any shift resulting from
the timing of this signal can be compensated for with the
horizontal timing value in H Position Register.
SMS (Pin 6). Mode select pin for the Serial Control Port.
When this input is at a CMOS High state (1) the Serial
Control Port will operate in the SPI mode. When the input
is Low (0), the Serial Control Port will operate in the I
2
C
slave mode. In SPI mode, the SEN pin must be tied High.
(See Reset Operation section.)
SEN (Pin 4). Enable signal for the SPI mode operation of
the Serial Control Port. When this pin is Low (0), the SPI
port is disabled and the SDO pin is in the high-impedance
state. Transitions on the SCK and SDA pins are ignored.
SPI mode operation is enabled when SMS is High (1).
SCK (Pin 15). Input pin for serial clock signal from the
master control device. In I
2
C mode operation the clock rate
is expected to be within I
2
C limits. In SPI mode, the
maximum clock frequency is 10 MHz.
Reset Operation. When the SMS and SEN pins are both
in the Low (0) state, the part will be in the Reset state.
Therefore, in the I
2
C mode the SEN pin can be used as an
NReset input. When SPI mode is used, if three wire
operation is desired, both SMS and SEN can be tied
together and used as the NReset input. In either mode,
NReset must be held Low (0) for at least 100 ns.
Input/Output
VIN/INTRO (Pin 13). In external (EXT) vertical lock mode
of operation, the internal vertical sync circuits will lock to
the VIN input signal applied at this pin. The part will lock to
the rising or falling edge of the signal in accordance with
the setting of the V Polarity command. The default is rising
edge. The VIN pulse must be at least 2 lines wide.
In INTRO Mode, when configured for internal vertical
synchronization, this pin will be an output pin providing an
interrupt signal to the master control device in accordance
with the settings in the Interrupt Mask Register.
SDA (Pin 14). When the Serial Control Port has been set
to I
2
C mode operation, this pin serves as the bidirectional
data line for sending and receiving serial data. In SPI mode
operation it operates as serial data input. SPI mode output
data is available on the SDO pin.
Outputs
SDO (Pin 16). Provides the serial data output when SPI
mode communications have been selected. This pin is not
used in I
2
C mode operation.
Box (Pin 17*). Black box keying output is an active High,
CMOS level signal used to key in the black box in the
captions/text displays. This output will be in the high-
impedance state when the background attribute has been
set to semi-transparent (*Z86129 only).
RED, GREEN, BLUE (Pins 2*, 3*, 18*). Positive acting
CMOS levels signals (*Z86129 only).
Color Mode: Red, Green and Blue character video outputs
for use in a color receiver.
s
Mono Mode: All three outputs carry the character
luminance information.
Notes: The selection of Color/Mono Mode is user
controlled in bit D
1
of the Configuration Register
(Address=00h). (See Internal Registers section.).
Z86129/130/131
P R E L I M I N A R Y
NTSC Line 21 Decoder
DS96TEL0200
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Pins With External Components
CSync (Pin 8). Sync slice level. A 0.1
µ
F capacitor must
be tied between this pin and analog ground V
SS
(A). This
capacitor stores the sync slice level voltage.
LPF (Pin 9). Loop Filter. A series RC low-pass filter must
be tied between this pin and analog ground V
SS
(A). There
must also be second capacitor from the pin to V
SS
(A).
Values for the three parts to be specified at a later date.
RREF (Pin 10). Reference setting resistor. Resistor must
be 10 kohms,
±
2%.
Power Supply
V
DD
(Pin 12). The voltage on this pin is nominally 5.0 Volts
and may range between 4.75 to 5.25 Volts with respect to
the V
SS
pins.
V
SS
(Pins 1, 11). These pins are the lowest potential
power pins for the analog and digital circuits. They are
normally tied to system ground. Note: The recommended
printed circuit pattern for implementing the power
connection and critical components will be supplied at a
later date.
Z86129/130/131 BLOCK DIAGRAM DESCRIPTION
The Z86129 is designed to process both fields of Line 21
of the television VBI and provide the functional
performance of a Line 21 Closed-Caption decoder and
Extended Data Service decoder. It requires two input
signals, Composite Video and a horizontal timing signal
(HIN), and several passive components for proper
operation. A vertical input signal is also required if OSD
display mode is desired when no video signal is present.
The Decoder performs several functions, namely
extraction of the data from Line 21, separation of the
normal Line 21 data from the XDS data, on-screen display
(Z86129 only) of the selected data channel and outputting
of the XDS data through the serial communications
channel.
Input Signals
The Composite Video input should be a signal which is
nominally 1.0 Volt p-p with sync tips negative and band
limited to 600 kHz. The Z86129 will operate with an input
level variation of
±
3 dB.
The HIN input signal is required to bring the VCO close to
the desired operating frequency. It must be a CMOS level
signal. The HIN signal can have positive or negative
polarity and is only required to be within 3% of the standard
H frequency. When configured for EXT HLK operation, this
signal should correspond to the H Flyback signal.
The timing difference between HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one of
the factors that will affect the horizontal position of the
display. Any shift resulting from the timing of this signal can
be compensated for with the horizontal timing value in the
H Position register.
Video Input Signal Processing
The Comp Video input is AC coupled to the device where
the sync tip is internally clamped to a fixed reference
voltage by means of a dual clamp. Initially, the unlocked
signal is clamped using a simple clamp. Improved impulse
noise performance is then achieved after the internal sync
circuits lock to the incoming signal. Noise rejection is
obtained by making the clamp operative only during the
sync tip. The clamped composite video signal is fed to both
the Data Slicer and Sync Slicer blocks.
The Data Slicer generates a clean CMOS level data signal
by slicing the signal at its midpoint. The slice level is
established on an adaptive basis during Line 21. The
resultant value is stored until the next occurrence of that
Line 21. A high level of noise immunity is achieved by
using this process.
The Sync Slicer processes the clamped Comp Video
signal to extract Comp Sync. This signal is used to lock the
internally generated sync to the incoming video when the
video lock mode of operation has been enabled. Sync
slicing is performed in two steps. In the non-locked mode,
the sync is sliced at a fixed offset level from the sync tip.
When proper lock operation has been achieved, the slice
level voltage switches from a fixed reference level to an
adaptive level. The slice level is stored on the sync slice
capacitor, CSYNC.
The Data Clock Recovery circuit operates in conjunction
with the Digital H Lock circuit. They produce a 32H clock
signal (DCLK) that is locked in phase to the clock run-in
burst portion of the sliced data obtained from the Data
Slicer. When Line 21 code appears, DCLK phase lock is
achieved during the clock run-in burst and used to reclock
the sliced data. Once phase lock is established it is
maintained until a change in video signal occurs.
The Digital H Lock circuit produces the video timing gates,
PG, STG, and so on, which are locked in phase with
HSYNC, the video timing signal, no matter which H lock
mode is used in the display generation circuits. This
independent phase lock loop is able to respond quickly to
changes in video timing, without concern for display
stability requirements.
Z86129/130/131
NTSC Line 21 Decoder
P R E L I M I N A R Y
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DS96TEL0200
Z86129/130/131 BLOCK DIAGRAM DESCRIPTION (Continued)
VCO and One Shot
All internal timing and synchronizing signals are derived
from the on-board 12 MHz VCO. Its output is the Dot Clk
signal used to drive the Horizontal and Vertical counter
chains and for display timing. The One Shot circuit
produces a horizontal timing signal derived from the
incoming video and qualified by the Copy Guard logic
circuits.
The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display
timing signal is available, the VCO is locked to the HIN
input through the action of the Phase Detector (PH2).
When a proper HIN signal is not available, such as in a
VCR, the VCO can be locked to the incoming video
through the Phase Detector (PH1). In this case the
frequency detector (FR) circuit is activated as required to
bring the VCO within the pull-in range of PH1.
Timing and Counting Circuits
The Dot Clk is first divided down to produce the character
timing clock CHAR CLK. This signal is then further divided
to generate the horizontal timing signals, H, 2H and
HSQR. These timing signals are used in the data output
(display) circuits.
The H signal is further divided in the LINE and FLD CNTR
to produce the various decodes used to establish vertical
lock and to time the display and control functions required
for proper operation. The H signal is also used to generate
the Smooth Scroll timing signal for display.
The V Lock circuits produce a noise free vertical pulse
derived from the horizontal timing signal. When the user
selects Video as the vertical lock source, the internal
synchronizing signals are phased up with the incoming
video by comparing the internally generated vertical pulse
to an input vertical pulse derived from the Comp Sync
signal provided by the Sync Slicer. In the vertical lock set
to VIN mode the VIN signal is used in place of the signal
derived from Comp Sync. In either case, when proper
phasing has been established, this circuit outputs the
LOCK signal which is used to provide additional noise
immunity to the slicing circuits.
The LOCKed state is established only after several
successive fields have occurred in which these two vertical
pulses remain in sync. Once LOCKed, the internal timing
will flywheel until such time as the two vertical pulses lose
coincidence for a number of consecutive fields. Until
LOCK is established, the decoder operates on a pulse for
pulse basis.