E
PRODUCT PREVIEW
May 1998
Order Number: 290645-001
n
Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
2.7 V or 1.65 V I/O Option Reduces
Overall System Power
12 V for Fast Production
Programming
n
High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n
Optimized Architecture for Code Plus
Data Storage
Eight 8-Kbyte Blocks,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks
Fast Program Suspend Capability
Fast Erase Suspend Capability
n
Flexible Block Locking
Lock/Unlock Any Block
Full Protection on Power-Up
WP# Pin for Hardware Block
Protection
V
PP
= GND Option
V
CC
Lockout Voltage
n
Low Power Consumption
9 mA Typical Read Power
10 µA Typical Standby Power with
Automatic Power Savings Feature
n
Extended Temperature Operation
–40 °C to +85 °C
n
Easy-12 V
Faster Production Programming
No Additional System Logic
n
128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP
Cells
n
Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles
n
Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., voice)
n
Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
n
SRAM-Compatible Write Interface
n
Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
n
x 16 for High Performance
48-Ball
µ
BGA* Package
48-Lead TSOP Package
n
x 8 I/O for Space Savings
48-Ball
µ
BGA* Package
40-Lead TSOP Package
n
0.25
µ
ETOX™ VI Flash Technology
The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a
feature-rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage
capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking
allows any block to be independently locked or unlocked. Add to this the Intel-developed Flash Data
Integrator (FDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution on
the market today. 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 40-lead TSOP,
and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing
Intel’s WWW page: http://www.intel.com/design/flcomp.
3 VOLT ADVANCED+ BOOT BLOCK
8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F008C3, 28F016C3, 28F032C3
28F800C3, 28F160C3, 28F320C3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F008C3, 28F016C3, 28F032C3, 28F800C3, 28F160C3, 28F320C3 may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are available on
request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION 1998
CG-041493
*
Third-party brands and names are the property of their respective owners.
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3 VOLT ADVANCED+ BOOT BLOCK
3
PRODUCT PREVIEW
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................5
1.1 3 Volt Advanced+ Boot Block Flash Memory
Enhancements ............................................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts ..........................................6
2.2 Block Organization .....................................10
2.2.1 Parameter Blocks ................................10
2.2.2 Main Blocks .........................................10
3.0 PRINCIPLES OF OPERATION .....................11
3.1 Bus Operation ............................................11
3.1.1 Read....................................................11
3.1.2 Output Disable.....................................11
3.1.3 Standby ...............................................11
3.1.4 Reset...................................................12
3.1.5 Write....................................................12
3.2 Modes of Operation....................................12
3.2.1 Read Array ..........................................12
3.2.2 Read Configuration..............................13
3.2.3 Read Status Register ..........................13
3.2.3.1 Clearing the Status Register .........13
3.2.4 Read Query .........................................13
3.2.5 Program Mode.....................................14
3.2.5.1 Suspending and Resuming
Program.......................................14
3.2.6 Erase Mode .........................................14
3.2.6.1 Suspending and Resuming Erase.15
3.3 Flexible Block Locking................................19
3.3.1 Locking Operation ...............................19
3.3.2 Locked State .......................................19
3.3.3 Unlocked State ....................................19
3.3.4 Lock-Down State .................................19
3.3.5 Reading a Block’s Lock Status ............20
3.3.6 Locking Operations during Erase
Suspend .............................................20
3.3.7 Status Register Error Checking ...........20
3.4 128-Bit Protection Register.........................21
3.4.1 Reading the Protection Register ..........21
3.4.2 Programming the Protection Register ..21
3.4.3 Locking the Protection Register ...........22
3.5 V
PP
Program and Erase Voltages...............22
3.5.1 Easy-12 V Operation for Fast
Manufacturing Programming...............22
3.5.2 V
PP
≤
V
PPLK
for Complete Protection ...22
3.5.3 V
PP
Usage ...........................................22
3.6 Power Consumption ...................................23
3.6.1 Active Power (Program/Erase/Read) ...23
3.6.2 Automatic Power Savings (APS) .........23
3.6.3 Standby Power ....................................23
3.6.4 Deep Power-Down Mode.....................24
3.7 Power-Up/Down Operation.........................24
3.7.1 RP# Connected to System Reset ........24
3.7.2 V
CC
, V
PP
and RP# Transitions .............24
3.8 Power Supply Decoupling ..........................24
4.0 ABSOLUTE MAXIMUM RATINGS ................25
4.2 Operating Conditions..................................25
4.3 Capacitance ...............................................26
4.4 DC Characteristics .....................................26
4.5 AC Characteristics—Read Operations—
Extended Temperature..............................30
4.6 AC Characteristics—Write Operations—
Extended Temperature..............................32
4.7 Erase and Program Timings .......................33
4.8 Reset Operations .......................................35
5.0 ORDERING INFORMATION..........................36
6.0 ADDITIONAL INFORMATION .......................37
APPENDIX A: WSM Current/Next States ..........38
APPENDIX B: Program/Erase Flowcharts ........40
APPENDIX C: Common Flash Interface Query
Structure ......................................................46
3 VOLT ADVANCED+ BOOT BLOCK
E
4
PRODUCT PREVIEW
APPENDIX D: Architecture Block Diagram ......52
APPENDIX E: Word-Wide Memory Map
Diagrams .....................................................53
APPENDIX F: Byte-Wide Memory Map
Diagrams .....................................................55
APPENDIX G: Device ID Table ..........................57
APPENDIX H: Protection Register
Addressing ..................................................58
REVISION HISTORY
Date of
Revision
Version
Description
05/12/98
-001
Original version
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3 VOLT ADVANCED+ BOOT BLOCK
5
PRODUCT PREVIEW
1.0
INTRODUCTION
This document contains the specifications for the
3 Volt Advanced+ Boot Block flash memory family.
These flash memories add features which can be
used to enhance the security of systems: instant
block locking and a protection register.
Throughout this document, the term “2.7 V” refers
to the full voltage range 2.7 V–3.6 V (except where
noted otherwise) and “V
PP
= 12 V” refers to 12 V
±5%. Sections 1 and 2 provide an overview of the
flash memory family including applications, pinouts,
pin descriptions and memory organization. Section
3 describes the operation of these products. Finally,
Section 4 contains the operating specifications.
1.1
3 Volt Advanced+ Boot Block
Flash Memory Enhancements
The 3 Volt Advanced+ Boot Block flash memory
features:
•
Zero-latency, flexible block locking
•
128-bit Protection Register
•
Simple system implementation for 12
V
production programming with 2.7
V in-field
programming
•
Ultra-low power operation at 2.7 V
•
Minimum 100,000 block erase cycles
•
Common Flash Interface for software query of
device specs and features
Table 1. 3 Volt Advanced+ Boot Block Feature Summary
Feature
8 M
(2)
16 M
32 M
(1)
8 M
(2)
16 M
32 M
Reference
V
CC
Operating Voltage
2.7 V – 3.6 V
Table 8
V
PP
Voltage
Provides complete write protection with
optional 12V Fast Programming
Table 8
V
CCQ
I/O Voltage
2.7 V– 3.6 V
Note 3
Bus Width
8-bit
16-bit
Table 2
Speed (ns)
90, 110 @ 2.7 V and 80, 100 @ 3.0 V
Table 11
Blocking (top or bottom)
8 x 8-Kbyte parameter
4-Mb: 7 x 64-Kbyte main
8-Mb: 15 x 64-Kbyte main
16-Mb: 31 x 64-Kbyte main
32-Mb: 63 x 64-Kbyte main
8 x 4-Kword parameter
4-Mb: 7 x 32-Kword main 8-
Mb: 15 x 32-Kword main
16-Mb: 31 x 32-Kword main
32-Mb: 63 x 32-Kword main
Section 2.2
Appendix E and F
Operating Temperature
Extended: –40 °C to +85 °C
Table 8
Program/Erase Cycling
100,000 cycles
Table 8
Packages
40-Lead TSOP
(1)
48-Ball
µ
BGA* CSP
(2)
48-Lead TSOP
48-Ball
µ
BGA* CSP
(2)
Figures 1, 2, 3,
and 4
Block Locking
Flexible locking of any block with zero latency
Section 3.3
Protection Register
64-bit unique device number, 64-bit user programmable
Section 3.4
NOTES:
1.
32-Mbit density not available in 40-lead TSOP.
2. 8-Mbit density not available in µBGA* CSP.
3.
V
CCQ
operation at 1.65 V — 2.5 V available upon request.
3 VOLT ADVANCED+ BOOT BLOCK
E
6
PRODUCT PREVIEW
1.2
Product Overview
Intel provides secure low voltage memory solutions
with the Advanced Boot Block family of products. A
new block locking feature allows instant
locking/unlocking of any block with zero-latency. A
128-bit protection register allows unique flash
device identification.
Discrete supply pins provide single voltage read,
program, and erase capability at 2.7 V while also
allowing 12
V V
PP
for faster production
programming. Easy-12 V, a new feature designed
to reduce external logic, simplifies board designs
when combining 12 V production programming with
2.7 V in-field programming.
The 3 Volt Advanced+ Boot Block flash memory
products are available in either x8 or x16 packages
in the following densities: (see Section 6,
Ordering
Information)
•
8-Mbit (8,388,608 bit) flash memories organized
as either 512 Kwords of 16 bits each or 1024
Kbytes or 8 bits each.
•
16-Mbit (16,777,216 bit) flash memories
organized as either 1024 Kwords of 16 bits
each or 2048 Kbytes of 8 bits each.
•
32-Mbit (33,554,432 bit) flash memories
organized as either 2048 Kwords of 16 bits
each or 4096 Kbytes of 8 bits each.
Eight 8-KB parameter blocks are located at either
the top (denoted by -T suffix) or the bottom (-B
suffix) of the address map in order to accommodate
different microprocessor protocols for kernel code
location. The remaining memory is grouped into 64-
Kbyte main blocks.
All blocks can be locked or unlocked instantly to
provide complete protection for code or data. (see
Section 3.3 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby
unburdening the microprocessor or microcontroller.
The status register indicates the status of the WSM
by signifying block erase or word program
completion and status.
Program and erase automation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Program operations are performed in word or byte
increments. Erase operations erase all locations
within a block simultaneously. Both program and
erase operations can be suspended by the system
software in order to read from any other block. In
addition, data can be programmed to another block
during an erase suspend.
The 3 Volt Advanced+ Boot Block flash memories
offer two low power savings features: Automatic
Power Savings (APS) and standby mode. The
device automatically enters APS mode following the
completion of a read cycle. Standby mode is
initiated when the system deselects the device by
driving CE# inactive. Combined, these two power
savings features significantly reduce power
consumption.
The device can be reset by lowering RP# to GND.
This provides CPU-memory reset synchronization
and additional protection against bus noise that
may occur during system reset and power-up/down
sequences (see Section 3.5 and 3.6).
Refer to the
DC Characteristics Section 4.4 for
complete current and voltage specifications. Refer
to the
AC Characteristics Sections 4.5 and 4.6, for
read and write performance specifications. Program
and erase times and shown in Section 4.7.
2.0
PRODUCT DESCRIPTION
This section provides device pin descriptions and
package pinouts for the 3 Volt Advanced+ Boot
Block flash memory family, which is available in 40-
Lead TSOP (x8, Figure 1), 48-lead TSOP (x16,
Figure 2) and 48-ball
µ
BGA packages (Figures 3
and 4).
2.1
Package Pinouts
In each diagram, upgrade pins from one density to
the next are circled.
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3 VOLT ADVANCED+ BOOT BLOCK
7
PRODUCT PREVIEW
Advanced Boot
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
21
22
23
24
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
WP#
A
7
A
6
A
5
A
4
A
3
A
2
A
1
V
PP
A
18
A
17
GND
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
OE#
GND
CE#
A
0
A
19
A
20
DQ
0
16M
8M
NOTES:
1.
40-Lead TSOP available for 8- and 16-Mbit densities only.
2.
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.
Figure 1. 40-Lead TSOP Package for x8 Configurations
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
25
26
27
28
29
30
31
32
16
15
7
14
6
13
5
12
4
A
V
CCQ
GND
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
CC
11
3
10
2
9
1
8
0
0
A
A
A
A
A
A
A
A
NC
WE#
RP#
WP#
A
A
A
A
A
A
A
A
17
7
6
5
4
3
2
1
15
14
13
12
11
10
9
8
V
PP
A
19
A
20
A
18
32M
16M
8M
NOTE:
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.
Figure 2. 48-Lead TSOP Package for x16 Configurations
3 VOLT ADVANCED+ BOOT BLOCK
E
8
PRODUCT PREVIEW
A
13
A
11
A
8
V
PP
WP#
A
7
A
4
A
B
C
D
E
F
1
2
3
4
5
6
7
8
A
14
A
10
WE#
RP#
A
18
A
17
A
5
A
2
A
15
A
12
A
9
A
6
A
3
A
1
A
16
D
14
D
5
D
11
D
2
D
8
CE#
A
0
V
CCQ
D
15
D
6
D
12
D
3
D
9
D
0
GND
GND
D
7
D
13
D
4
V
CC
D
10
D
1
OE#
A
19
16M
A
20
32M
NOTES:
1.
Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A
19
is the upgrade address for the 16-Mbit device. A
20
is the
upgrade address for the 32-Mbit device.
2.
8-Mbit not available on
µ
BGA* CSP.
Figure 3. x16 48-Ball
µ
BGA* Chip Size Package (Top View, Ball Down)
A
14
A
12
A
8
V
PP
WP#
A
7
A
4
A
B
C
D
E
F
1
2
3
4
5
6
7
8
A
15
A
10
WE#
RP#
A
19
A
18
A
5
A
2
A
16
A
13
A
9
A
6
A
3
A
1
A
17
NC
D
5
NC
D
2
NC
CE#
A
0
V
CCQ
A
11
D
6
NC
D
3
NC
D
0
GND
GND
D
7
NC
D
4
V
CC
NC
D
1
OE#
A
20
A
21
32M
16M
NOTES:
1.
Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A
20
is the upgrade address for the 16-Mbit device. A
21
is the
upgrade address for the 32-Mbit device.
2.
8-Mbit not available on
µ
BGA* CSP.
Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
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3 VOLT ADVANCED+ BOOT BLOCK
9
PRODUCT PREVIEW
Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
8-Mbit x 8 A[0-19], 16-Mbit x 8 A[0-20], 32-Mbit x 8 A[0-21]
8-Mbit x 16 A[0-18], 16-Mbit x 16 A[0-19], 32-Mbit x 16 A[0-20]
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, configuration and status register data.
The data pins float to tri-state when the chip is de-selected or the outputs
are disabled.
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and configuration data. The data pins float to tri-state when
the chip is de-selected. Not included on x8 products.
CE#
INPUT
CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and
memory array. WE# is active low. Addresses and data are latched on
the rising edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN: Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT: Controls the lock-down function of the flexible
Locking feature
When WP# is a logic low, the lock-down mechanism is enabled and
blocks marked lock-down cannot be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled and
blocks previously locked-down are now locked and can be unlocked and
locked through software. After WP# goes low, any blocks previously
marked lock-down revert to that state.
See Section 3.3 for details on block locking.
V
CC
SUPPLY
DEVICE POWER SUPPLY: [2.7 V–3.6 V] Supplies power for device
operations.
3 VOLT ADVANCED+ BOOT BLOCK
E
10
PRODUCT PREVIEW
Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions (Continued)
Symbol
Type
Name and Function
V
CCQ
INPUT
I/O POWER SUPPLY: Supplies power for input/output buffers.
[2.7 V–3.6 V] This input should be tied directly to V
CC
.
[1.65 V– 2.5 V] Lower I/O power supply voltage available upon request.
Contact your Intel representative for more information.
V
PP
INPUT/
SUPPLY
PROGRAM/ERASE POWER SUPPLY: [1.65 V–3.6 V or 11.4 V–12.6 V]
Operates as a input at logic levels to control complete device protection.
Supplies power for accelerated program and erase operations in 12 V
±
5% range. This pin cannot be left floating.
Lower V
PP
≤
V
PPLK
, to protect all contents against Program and
Erase commands.
Set V
PP
= V
CC
for in-system read, program and erase operations. In
this configuration, V
PP