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PRELIMINARY

May 1997

Order Number: 290605-001

Flexible SmartVoltage Technology



2.7V–3.6V Program/Erase



2.7V–3.6V Read Operation



12V V

Fast Production

Programming

2.7V or 1.8V I/O Option



Reduces Overall System Power

Optimized Block Sizes



Eight 8-Kbyte Blocks for Data,

Top or Bottom Locations



Up to Thirty-One 64-Kbyte Blocks

for Code

High Performance



2.7V–3.6V: 120 ns Max Access Time

Block Locking



-Level Control through WP#

Low Power Consumption



20 mA Maximum Read Current

Absolute Hardware-Protection



= GND Option



Lockout Voltage

Extended Temperature Operation



–40°C to +85°C

Supports Code plus Data Storage



Optimized for FDI, Flash Data

Integrator Software



Fast Program Suspend Capability



Fast Erase Suspend Capability

Extended Cycling Capability



10,000 Block Erase Cycles

Automated Byte Program and Block

Erase



Command User Interface



Status Registers

SRAM-Compatible Write Interface

Automatic Power Savings Feature

Reset/Deep Power-Down



1 µA I

Typical



Spurious Write Lockout

Standard Surface Mount Packaging



48-Ball

BGA* Package



40-Lead TSOP Package

Footprint Upgradeable



Upgradeable from 2-, 4- and 8-Mbit

Boot Block

ETOX™ V (0.4

µ)

Flash Technology

x8-Only Input/Output Architecture



For Space-Constrained 8-bit

Applications

The new Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.4µ technology, represents a feature-

rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability

(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been

added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and

interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device.

Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective,

monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Byte-Wide

products will be available in 40-lead TSOP and 48-ball µBGA* packages. Additional information on this

product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp

SMART 3 ADVANCED BOOT BLOCK

BYTE-WIDE

8-MBIT (1024K x 8), 16-MBIT (2056K x 8)

FLASH MEMORY FAMILY

28F008B3, 28F016B3

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F008B3 and 28F016B3 may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

*Third-party brands and names are the property of their respective owners.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

CG-041493

Third-party brands and names are the property of their respective owners.

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

CONTENTS

PAGE

1.0 INTRODUCTION .............................................5

1.1 Smart 3 Advanced Boot Block Flash

Memory Enhancements ..............................5

1.2 Product Overview.........................................6

2.0 PRODUCT DESCRIPTION..............................6

2.1 Package Pinouts ..........................................7

2.2 Block Organization .....................................11

2.2.1 Parameter Blocks ................................11

2.2.2 Main Blocks .........................................11

3.0 PRINCIPLES OF OPERATION .....................14

3.1 Bus Operation ............................................14

3.1.1 Read....................................................15

3.1.2 Output Disable.....................................15

3.1.3 Standby ...............................................15

3.1.4 Deep Power-Down/Reset ....................15

3.1.5 Write....................................................15

3.2 Modes of Operation....................................15

3.2.1 Read Array ..........................................16

3.2.2 Read Intelligent Identifier .....................17

3.2.3 Read Status Register ..........................17

3.2.4 Program Mode.....................................18

3.2.5 Erase Mode .........................................19

3.3 Block Locking.............................................26

3.3.1 V

= V

for Complete Protection .......26

3.3.2 WP# = V

for Block Locking................26

3.3.3 WP# = V

for Block Unlocking ............26

3.4 V

Program and Erase Voltages ..............26

3.5 Power Consumption ...................................26

3.5.1 Active Power .......................................26

3.5.2 Automatic Power Savings (APS) .........27

3.5.3 Standby Power ....................................27

3.5.4 Deep Power-Down Mode.....................27

3.6 Power-Up/Down Operation.........................27

3.6.1 RP# Connected to System Reset ........27

3.6.2 V

, V

and RP# Transitions .............27

3.7 Power Supply Decoupling ..........................28

3.7.1 V

Trace on Printed Circuit Boards ....28

4.0 ABSOLUTE MAXIMUM RATINGS ................29

5.0 OPERATING CONDITIONS

CCQ

= 2.7V–3.6V).......................................29

5.1 DC Characteristics: V

CCQ

= 2.7V–3.6V.......30

6.0 OPERATING CONDITIONS

CCQ

= 1.8V–2.2V).......................................34

6.1 DC Characteristics: V

CCQ

= 1.8V–2.2V.......34

7.0 AC CHARACTERISTICS...............................39

7.1 Reset Operations .......................................43

APPENDIX A: Ordering Information .................45

APPENDIX B: Write State Machine Current/

Next States ..................................................46

APPENDIX C: Access Time vs.

Capacitive Load...........................................47

APPENDIX D: Architecture Block Diagram ......48

APPENDIX E: Additional Information ...............49

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

1.0

INTRODUCTION

This preliminary datasheet contains the

specifications for the Advanced Boot Block flash

memory family, which is optimized for low power,

portable systems. This family of products features

1.8V–2.2V or 2.V–3.6V I/Os and a low V

operating range of 2.7V–3.6V for read and

program/erase operations. In addition this family is

capable of fast programming at 12V. Throughout

this document, the term “2.7V” refers to the full

voltage range 2.7V–3.6V (except where noted

otherwise) and “V

= 12V” refers to 12V ±5%.

Section 1 and 2 provides an overview of the flash

memory family including applications, pinouts and

pin descriptions. Section 3 describes the memory

organization and operation for these products.

Finally, Sections 4, 5, 6 and 7 contain the

operating specifications.

1.1

Smart 3 Advanced Boot Block

Flash Memory Enhancements

The new 8-Mbit and 16-Mbit Smart 3 Advanced

Boot Block flash memory provides a convenient

upgrade from and/or compatibility to previous 4-

Mbit and 8-Mbit Boot Block products. The Smart 3

product functions are similar to lower density

products in both command sets and operation,

providing similar pinouts to ease density upgrades.

The Smart 3 Advanced Boot Block flash memory

features

•

Enhanced blocking for easy segmentation of

code and data or additional design flexibility

•

Program Suspend command which permits

program suspend to read

•

WP# pin to lock and unlock the upper two (or

lower two, depending on location) 8-Kbyte

blocks

•

CCQ

input for 1.8V–2.2V on all I/Os. See

Figures 1–3 for pinout diagrams and V

CCQ

location

•

Maximum program time specification for

improved data storage.

Table 1. Smart 3 Advanced Boot Block Feature Summary

Feature

28F016B3/28F008B3/28F004B3

Reference

Read Voltage

2.7V– 3.6V

Table 9, Table 12

CCQ

I/O Voltage

1.8V–2.2V or 2.7V– 3.6V

Table 9, Table 12

Program/Erase Voltage

2.7V– 3.6V or 11.4V– 12.6V

Table 9, Table 12

Bus Width

8 bits

Table 2

Speed

120 ns

Table 15

Memory Arrangement

1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)

Blocking (top or bottom)

Eight 8-Kbyte parameter blocks (8/16 Mbit) &

Fifteen 64-Kbyte blocks (8 Mbit)

Thirty-one 64-Kbyte main blocks (16 Mbit)

Section 2.2

Figures 4 and 5

Locking

WP# locks/unlocks parameter blocks

All other blocks protected using V

switch

Section 3.3

Table 8

Operating Temperature

Extended: –40

C to +85

Table 9, Table 12

Program/Erase Cycling

10,000 cycles

Table 9, Table 12

Packages

40-Lead TSOP, 48-Ball

BGA* CSP

Figures 1, 2, and 3

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

1.2

Product Overview

Intel provides the most flexible voltage solution in

the flash industry, providing three discrete voltage

supply pins: V

for read operation, V

CCQ

for output

swing, and V

for program and erase operation.

Discrete supply pins allow system designers to use

the optimal voltage levels for their design. All Smart

3 Advanced Boot Block flash memory products

provide program/erase capability at 2.7V or 12V

and read with V

at 2.7V. Since many designs

read from the flash memory a large percentage of

the time, 2.7V V

operation can provide

substantial power savings. The 12V V

option

maximizes program and erase performance during

production programming.

The Smart 3 Advanced Boot Block flash memory

products are high-performance devices with low

power operation. The available densities for the

byte-wide devices (x8) are

8-Mbit (8,388,608-bit) flash memory

organized as 1 Mbyte of 8 bits each

16-Mbit (16,777,216-bit) flash memory

organized as 2 Mbytes of 8 bits each.

For word-wide devices (x16) see the

Smart 3

Advanced Boot Block Word-Wide Flash Memory

Family datasheet.

The parameter blocks are located at either the top

(denoted by -T suffix) or the bottom (-B suffix) of the

address map in order to accommodate different

microprocessor protocols for kernel code location.

The upper two (or lower two) parameter blocks can

be locked to provide complete code security for

system initialization code. Locking and unlocking is

controlled by WP# (see Section 3.3 for details).

The Command User Interface (CUI) serves as the

interface between the microprocessor or

microcontroller and the internal operation of the

flash memory. The internal Write State Machine

(WSM) automatically executes the algorithms and

timings necessary for program and erase

operations, including verification, thereby un-

burdening the microprocessor or microcontroller.

The status register indicates the status of the WSM

by signifying block erase or byte program

completion and status.

Program and erase automation allows program and

erase operations to be executed using an industry-

standard two-write command sequence to the CUI.

Data writes are performed in byte increments. Each

byte in the flash memory can be programmed

independently of other memory locations; every

erase operation erases all locations within a block

simultaneously. Program suspend allows system

software to suspend the program command in order

to read from any other block. Erase suspend allows

system software to suspend the block erase

command in order to read from or program data to

any other block.

The Smart 3 Advanced Boot Block flash memory is

also designed with an Automatic Power Savings

(APS) feature which minimizes system current

drain, allowing for very low power designs. This

mode is entered immediately following the

completion of a read cycle.

When the CE# and RP# pins are at V

, the I

CMOS standby mode is enabled. A deep power-

down mode is enabled when the RP# pin is at

GND, minimizing power consumption and providing

write protection. I

current in deep power-down is

1 µA typical (2.7V V

). A minimum reset time of

PHQV

is required from RP# switching high until

outputs are valid to read attempts. With RP# at

GND, the WSM is reset and Status Register is

cleared. Section 3.5 contains additional information

on using the deep power-down feature, along with

other power consumption issues.

The RP# pin provides additional protection against

unwanted command writes that may occur during

system reset and power-up/down sequences due to

invalid system bus conditions (see Section 3.6).

Refer to the DC Characteristics Table, Sections 5.1

and 6.1, for complete current and voltage

specifications. Refer to the AC Characteristics

Table, Section 7.0, for read, program and erase

performance specifications.

2.0

PRODUCT DESCRIPTION

This section explains device pin description and

package pinouts.

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

2.1

Package Pinouts

The Smart 3 Advanced Boot Block flash memory is

available in 40-lead TSOP (see Figure 1) and 48-

ball

BGA packages (see Figures 2 and 3). In

Figure 1, pin changes from one density to the next

are circled. Both packages, 40-lead TSOP and 48-

ball

BGA

package, are 8-bits wide and fully

upgradeable across product densities (from 8 Mb to

16 Mb).

Advanced Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

28F008

28F016

WE#

RP#

WP#

WE#

RP#

WP#

28F008

28F016

GND

CCQ

OE#

GND

CE#

GND

CCQ

OE#

GND

CE#

0605-01

Figure 1. 40-Lead TSOP Package

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

The pin descriptions table details the usage of each device pin.

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions

Symbol

Type

Name and Function

–A

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a program or erase cycle.

28F008B3: A[0-19], 28F016B3: A[0-20]

–DQ

INPUT/OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

WE# cycle during a Program command. Inputs commands to the

Command User Interface when CE# and WE# are active. Data is

internally latched. Outputs array, Intelligent Identifier and Status Register

data. The data pins float to tri-state when the chip is de-selected or the

outputs are disabled.

CE#

INPUT

CHIP ENABLE: Activates the internal control logic, input buffers,

decoders and sense amplifiers. CE# is active low. CE# high de-selects

the memory device and reduces power consumption to standby levels. If

CE# and RP# are high, but not at a CMOS high level, the standby

current will increase due to current flow through the CE# and RP# inputs.

OE#

INPUT

OUTPUT ENABLE: Enables the device’s outputs through the data

buffers during an array or status register read. OE# is active low.

WE#

INPUT

WRITE ENABLE: Controls writes to the Command Register and memory

array. WE# is active low. Addresses and data are latched on the rising

edge of the second WE# pulse.

RP#

INPUT

RESET/DEEP POWER-DOWN: Uses two voltage levels (V

, V

) to

control reset/deep power-down mode.

When RP# is at logic low, the device is in reset/deep power-down

mode, which drives the outputs to High-Z, resets the Write State

Machine, and draws minimum current.

When RP# is at logic high, the device is in standard operation.

When RP# transitions from logic-low to logic-high, the device defaults to

the read array mode.

WP#

INPUT

WRITE PROTECT: Provides a method for locking and unlocking the two

lockable parameter blocks.

When WP# is at logic low, the lockable blocks are locked,

preventing program and erase operations to those blocks. If a program

or erase operation is attempted on a locked block, SR.1 and either SR.4

[program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and

can be programmed or erased.

See Section 3.3 for details on write protection.

SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)

Symbol

Type

Name and Function

CCQ

INPUT

OUTPUT V

: Enables all outputs to be driven to 2.0V ±10% while the

is at 2.7V. When this mode is used, the V

should be regulated to

2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC

Characteristics: V

CCQ

= 1.8V–2.2V).

This input may be tied directly to V

(2.7V–3.6V).

See the DC Characteristics for further details.

DEVICE POWER SUPPLY: 2.7V–3.6V

PROGRAM/ERASE POWER SUPPLY: For erasing memory array

blocks or programming data in each block, a voltage of either 2.7V–3.6V

or 12V

5% must be applied to this pin. When V

< V

PPLK

all blocks

are locked and protected against Program and Erase commands.

Applying 11.4V–12.6V to V

can only be done for a maximum of 1000

cycles on the main blocks and 2500 cycles on the parameter blocks.

may be connected to 12V for a total of 80 hours maximum (see

Section 3.4 for details).

GND

GROUND: For all internal circuitry. All ground inputs must be

connected.

NO CONNECT: Pin may be driven or left floating.

2.2

Block Organization

The Smart 3 Advanced Boot Block is an

asymmetrically-blocked architecture that enables

system integration of code and data within a single

flash device. Each block can be erased

independently of the others up to 10,000 times. For

the address locations of each block, see the

memory maps in Figure 4 (top boot blocking) and

Figure 5 (bottom boot blocking).

2.2.1

PARAMETER BLOCKS

The Smart 3 Advanced Boot Block flash memory

architecture includes parameter blocks to facilitate

storage of frequently updated small parameters

(e.g., data that would normally be stored in an

EEPROM. By using software techniques, the byte-

rewrite functionality of EEPROMs can be emulated.

Each 8-/16-Mbit device contains eight parameter

blocks of 8 Kbytes (8,192-bytes) each.

2.2.2

MAIN BLOCKS

After the parameter blocks, the remainder of the

array is divided into equal size main blocks for data

or code storage. Each 16-Mbit device contains

thirty-one 64-Kbyte (65,536-byte) blocks. Each

8-Mbit device contains fifteen 64-Kbyte blocks.