E
PRODUCT PREVIEW
December 1996
Order Number: 290600-002
n
SmartVoltage Technology
2.7V (Read-Only), 3.3V or 5V V
CC
and 3.3V, 5V, or 12V V
PP
n
High-Performance
4, 8 Mbit: 85 ns Read Access Time
16 Mbit: 95 ns Read Access Time
n
Enhanced Data Protection Features
Absolute Protection with V
PP
= GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n
Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n
Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
n
High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n
Extended Cycling Capability
100,000 Block Erase Cycles
n
Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases I
CC
in Static Mode
n
Automated Program and Block Erase
Command User Interface
Status Register
n
SRAM-Compatible Write Interface
n
ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide SmartVoltage FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with V
PP
at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4
µ
m ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide SmartVoltage FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
BYTE-WIDE
SmartVoltage FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004SC, 28F008SC, 28F016SC
Includes Commercial and Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F004SC, 28F008SC, 28F016SC may contain design defects or errors known as errata. Current characterized errata are
available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
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PRODUCT PREVIEW
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION ............................................. 5
1.1 New Features .............................................. 5
1.2 Product Overview ........................................ 5
1.3 Pinout and Pin Description........................... 6
2.0 PRINCIPLES OF OPERATION ....................... 9
2.1 Data Protection .......................................... 10
3.0 BUS OPERATION......................................... 10
3.1 Read .......................................................... 10
3.2 Output Disable ........................................... 10
3.3 Standby ..................................................... 10
3.4 Deep Power-Down..................................... 10
3.5 Read Identifier Codes Operation................ 11
3.6 Write .......................................................... 11
4.0 COMMAND DEFINITIONS ............................ 11
4.1 Read Array Command ............................... 14
4.2 Read Identifier Codes Command ............... 14
4.3 Read Status Register Command................ 14
4.4 Clear Status Register Command................ 14
4.5 Block Erase Command .............................. 14
4.6 Program Command.................................... 15
4.7 Block Erase Suspend Command ............... 15
4.8 Program Suspend Command..................... 16
4.9 Set Block and Master Lock-Bit Commands 16
4.10 Clear Block Lock-Bits Command.............. 17
5.0 DESIGN CONSIDERATIONS........................ 25
5.1 Three-Line Output Control ......................... 25
5.2 RY/BY# Hardware Detection...................... 25
5.3 Power Supply Decoupling .......................... 25
5.4 V
PP
Trace on Printed Circuit Boards .......... 25
5.5 V
CC
, V
PP
, RP# Transitions ......................... 25
5.6 Power-Up/Down Protection ........................ 25
6.0 ELECTRICAL SPECIFICATIONS ................. 26
6.1 Absolute Maximum Ratings........................ 26
6.2 Commercial Temperature Operating
Conditions ................................................. 26
6.2.1 Capacitance ........................................ 26
6.2.2 AC Input/Output Test Conditions ......... 27
6.2.3 Commercial Temperature
DC Characteristics ............................. 28
6.2.4 Commercial Temperature
AC Characteristics - Read-Only
Operations.......................................... 30
6.2.5 Commercial Temperature Reset
Operations.......................................... 31
6.2.6 Commercial Temperature
AC Characteristics - Write Operations 32
6.2.7 Commercial Temperature Block Erase,
Program, and Lock-Bit Configuration
Performance....................................... 34
6.3 Extended Temperature Operating
Conditions ................................................. 35
6.3.1 Extended Temperature
DC Characteristics ............................. 35
6.3.2 Extended Temperature
AC Characteristics - Read-Only
Operations.......................................... 35
APPENDIX A. Ordering Information ................. 36
APPENDIX B. Additional Information ............... 37
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
4
PRODUCT PREVIEW
REVISION HISTORY
Number
Description
-001
Original version
-002
Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program.
Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead
PSOP to TB = Ext. Temp. 44-Lead PSOP.
Corrected nomenclature table (Appendix A) to reflect actual Operating Temperature/
Package information
Updated Ordering Information and table
Correction to table, Section 6.2.3. Under I
LO
Test Conditions, previously read V
IN
= V
CC
or GND, corrected to V
OUT
= V
CC
or GND
Section 6.2.7, modified Program and Block Erase Suspend Latency Times
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
5
PRODUCT PREVIEW
1.0
INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit
SmartVoltage FlashFile memory specifications.
Section 1 provides a flash memory overview.
Sections 2, 3, 4, and 5 describe the memory
organization and functionality. Section 6 covers
electrical specifications for commercial and
extended temperature product offerings. The byte-
wide SmartVoltage FlashFile memory family
documentation also includes application notes and
design tools which are referenced in Appendix B.
1.1
New Features
The byte-wide SmartVoltage FlashFile memory
family maintains backwards-compatibility with
Intel’s 28F008SA and 28F008SA-L. Key
enhancements include:
•
SmartVoltage Technology
•
Enhanced Suspend Capabilities
•
In-System Block Locking
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA and
28F008SA-L to byte-wide SmartVoltage FlashFile
products. When upgrading, it is important to note
the following differences:
•
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
•
V
PPLK
has been lowered from 6.5V to 1.5V to
support low V
PP
voltages during block erase,
program, and lock-bit configuration operations.
Designs that switch V
PP
off during read
operations should transition V
PP
to GND.
•
To take advantage of SmartVoltage tech-
nology, allow V
PP
connection to 3.3V or 5V.
For more details see application note
AP-625,
28F008SC Compatibility with 28F008SA (order
number 292180)
.
1.2
Product Overview
The byte-wide SmartVoltage FlashFile memory
family provides density upgrades with pinout
compatibility for the 4-, 8-, and 16-Mbit densities.
The 28F004SC, 28F008SC, and 28F016SC are
high-performance memories arranged as
512 Kbyte, 1 Mbyte, and 2 Mbyte of 8 bits. This
data is grouped in eight, sixteen, and thirty-two
64-Kbyte blocks which are individually erasable,
lockable, and unlockable in-system. Figure 4
illustrates the memory organization.
SmartVoltage technology enables fast factory
programming and low-power designs. These
components support read operations at 2.7V (read-
only), 3.3V, and 5V V
CC
and block erase and
program operations at 3.3V, 5V, and 12V V
PP
. The
12V V
PP
option renders the fastest program and
erase performance which will increase your factory
throughput. With the 3.3V and 5V V
PP
option, V
CC
and V
PP
can be tied together for a simple and
voltage flexible design. This voltage flexibility is key
for removable media that need to operate in a 3V to
5V system. In addition, the dedicated V
PP
pin gives
complete data protection when V
PP
≤
V
PPLK
.
Table 1. SmartVoltage Flash
V
CC
and V
PP
Voltage Combinations
V
CC
Voltage
V
PP
Voltage
2.7V
(1)
3.3V
3.3V, 5V, 12V
5V
5V, 12V
NOTE:
1.
Block erase, program, and lock-bit configuration
operation with V
CC
, 3.0V are not supported.
Internal V
CC
and V
PP
detection circuitry
automatically configures the device for optimum
performance.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
6
PRODUCT PREVIEW
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 1 second
(5V V
CC
, 12V V
PP
), independent of other blocks.
Each block can be independently erased 100,000
times (1.6 million block erases per device). A block
erase suspend operation allows system software to
suspend block erase to read data from or write data
to any other block.
Data is programmed in byte increments typically
within 6
µ
s (5V V
CC
, 12V V
PP
). A program suspend
operation permits system software to read data or
execute code from any other flash memory array
location.
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration operation. RY/BY#-high
indicates that the WSM is ready for a new
command, block erase is suspended (and program
is inactive), program is suspended, or the device is
in deep power-down mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
CCR
current is 1 mA at 5V
V
CC
.
When CE# and RP# pins are at V
CC
, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
PHQV
) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
PHEL
)
from RP#-high until writes to the CUI are
recognized.
1.3
Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package).
Pinouts are shown in Figures 2 and 3.
4-Mbit: A - A ,
8-Mbit: A - A ,
16-Mbit: A - A
0
18
0
19
0
20
Input
Buffer
Output
Buffer
Identifier
Register
Status
Register
Command
Register
I/O Logic
Data
Comparator
Input
Buffer
Address
Latch
Address
Counter
Y
Decoder
X
Decoder
Y Gating
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
Write State
Machine
Program/Erase
Voltage Switch
CE#
WE#
OE#
RP#
RY/BY#
V
V
GND
DQ - DQ
PP
CC
V
CC
0
7
Figure 1. Block Diagram
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BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
7
PRODUCT PREVIEW
Table 2. Pin Descriptions
Sym
Type
Name and Function
A
0
–A
20
INPUT
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during a write cycle.
4 Mbit
→
A
0
–A
18
8 Mbit
→
A
0
–A
19
16 Mbit
→
A
0
–A
20
DQ
0
–DQ
7
INPUT/
OUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, status register, and identifier code read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are
disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE#-high deselects the device and reduces power consumption to
standby levels.
RP#
INPUT
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during power transitions, puts the device in deep
power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
RP# at V
HH
enables setting of the master lock-bit and enables configuration of block
lock-bits when the master lock-bit is set. RP# = V
HH
overrides block lock-bits,
thereby enabling block erase and program operations to locked memory blocks.
Block erase, program, or lock-bit configuration with V
IH
< RP# < V
HH
produce
spurious results and should not be attempted.
OE#
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE#
INPUT
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
RY/BY#
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, program, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase or
program is suspended, or the device is in deep power-down mode. RY/BY# is
always active.
V
PP
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, programming data, or configuring lock-bits.
SmartVoltage Flash
→
3.3V, 5V, and 12V V
PP
With V
PP
≤
V
PPLK
, memory contents cannot be altered. Block erase, program, and
lock-bit configuration with an invalid V
PP
(see DC Characteristics) produce spurious
results and should not be attempted.
V
CC
SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
for optimized read performance. Do not float any power pins.
SmartVoltage Flash
→
2.7V (Read-Only), 3.3V, and 5V V
CC
With V
CC
≤
V
LKO
, all write attempts to the flash memory are inhibited. Device
operations at invalid V
CC
voltages (see DC Characteristics) produce spurious
results and should not be attempted. Block erase, program, and lock-bit
configuration operations with V
CC
< 3.0V are not supported.
GND
SUPPLY GROUND: Do not float any ground pins.
NC
NO CONNECT: Lead is not internally connected; it may be driven or floated.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
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PRODUCT PREVIEW
28F004SC
28F008SC
28F016SC
NC
CE#
RP#
A
18
A
13
A
17
A
14
A
16
A
15
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
V
CC
V
PP
NC
WE#
OE#
RY/BY#
GND
GND
DQ
6
DQ
7
DQ
5
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
NC
V
CC
A
19
A
19
DQ
4
A
20
40-LEAD TSOP
STANDARD PINOUT
10 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
CE#
RP#
A
18
A
13
A
17
A
14
A
16
A
15
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
V
CC
V
PP
CE#
RP#
A
18
A
13
A
17
A
14
A
16
A
15
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
V
CC
V
PP
NC
WE#
OE#
RY/BY#
GND
GND
DQ
6
DQ
7
DQ
5
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
NC
V
CC
DQ
4
NC
WE#
OE#
RY/BY#
GND
GND
DQ
6
DQ
7
DQ
5
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
V
CC
DQ
4
Figure 2. TSOP 40-Lead Pinout
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
RP#
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
NC
NC
GND
GND
V
PP
28F004SC
28F008SC
28F016SC
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
RP#
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
NC
NC
GND
GND
V
PP
WE#
CE#
RY/BY#
DQ
6
DQ
7
DQ
5
NC
V
CC
A
18
A
13
A
17
A
14
A
16
A
15
A
12
NC
NC
NC
NC
OE#
V
CC
DQ
4
A
19
A
19
A
20
44-LEAD PSOP
13.3 mm x 28.2 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
41
42
43
44
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
0
A
1
A
2
A
3
DQ
3
DQ
2
DQ
1
DQ
0
RP#
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
NC
NC
GND
GND
V
PP
WE#
CE#
RY/BY#
DQ
6
DQ
7
DQ
5
V
CC
A
18
A
13
A
17
A
14
A
16
A
15
A
12
NC
NC
NC
OE#
V
CC
DQ
4
WE#
CE#
RY/BY#
DQ
6
DQ
7
DQ
5
V
CC
A
18
A
13
A
17
A
14
A
16
A
15
A
12
NC
NC
NC
NC
OE#
V
CC
DQ
4