E
PRELIMINARY
July 1998
Order Number: 290580-005
n
Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
12 V V
PP
Fast Production
Programming
n
2.7 V or 1.65 V I/O Option
Reduces Overall System Power
n
High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n
Optimized Block Sizes
Eight 8-KB Blocks for Data,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks for
Code
n
Block Locking
V
CC
-Level Control through WP#
n
Low Power Consumption
10 mA Typical Read Current
n
Absolute Hardware-Protection
V
PP
= GND Option
V
CC
Lockout Voltage
n
Extended Temperature Operation
–40 °C to +85 °C
n
Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., Voice)
n
Automated Program and Block Erase
Status Registers
n
Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles Guaranteed
n
Automatic Power Savings Feature
Typical I
CCS
after Bus Inactivity
n
Standard Surface Mount Packaging
48-Ball
µ
BGA* Package
48-Lead TSOP Package
40-Lead TSOP Package
n
Footprint Upgradeable
Upgrade Path for 4-, 8-, 16-, and 32-
Mbit Densities
n
ETOX™ VI (0.25
µ)
Flash Technology
The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40-
lead and 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F400B3, 28F800/008B3, 28F160/016B3, 38F320/032B3 may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s Website at http://www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997,1998
CG-041493
*
Third-party brands and names are the property of their respective owners
E
SMART 3 ADVANCED BOOT BLOCK
3
PRELIMINARY
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts ..........................................6
2.2 Block Organization .....................................11
2.2.1 Parameter Blocks ................................11
2.2.2 Main Blocks .........................................11
3.0 PRINCIPLES OF OPERATION .....................11
3.1 Bus Operation ............................................12
3.1.1 Read....................................................13
3.1.2 Output Disable.....................................13
3.1.3 Standby ...............................................13
3.1.4 Deep Power-Down / Reset ..................13
3.1.5 Write....................................................13
3.2 Modes of Operation....................................14
3.2.1 Read Array ..........................................14
3.2.2 Read Identifier .....................................15
3.2.3 Read Status Register ..........................16
3.2.4 Program Mode.....................................16
3.2.5 Erase Mode .........................................17
3.3 Block Locking.............................................20
3.3.1 WP# = V
IL
for Block Locking................20
3.3.2 WP# = V
IH
for Block Unlocking ............20
3.4 V
PP
Program and Erase Voltages ..............20
3.4.1 V
PP
= V
IL
for Complete Protection .......20
3.5 Power Consumption ...................................20
3.5.1 Active Power .......................................21
3.5.2 Automatic Power Savings (APS) .........21
3.5.3 Standby Power ....................................21
3.5.4 Deep Power-Down Mode.....................21
3.6 Power-Up/Down Operation.........................21
3.6.1 RP# Connected to System Reset ........21
3.6.2 V
CC
, V
PP
and RP# Transitions .............21
3.7 Power Supply Decoupling ..........................22
4.0 ELECTRICAL SPECIFICATIONS..................23
4.1 Absolute Maximum Ratings ........................23
4.2 Operating Conditions..................................24
4.3 Capacitance ...............................................24
4.4 DC Characteristics .....................................25
4.5 AC Characteristics—Read Operations .......28
4.6 AC Characteristics—Write Operations........30
4.7 Program and Erase Timings .......................31
5.0 RESET OPERATIONS ..................................33
6.0 ORDERING INFORMATION..........................34
7.0 ADDITIONAL INFORMATION .......................36
APPENDIX A: Write State Machine
Current/Next States.....................................37
APPENDIX B: Access Time vs.
Capacitive Load...........................................38
APPENDIX C: Architecture Block Diagram ......39
APPENDIX D: Word-Wide Memory Map
Diagrams......................................................40
APPENDIX E: Byte Wide Memory Map
Diagrams......................................................43
APPENDIX F: Program and Erase Flowcharts .45
SMART 3 ADVANCED BOOT BLOCK
E
4
PRELIMINARY
REVISION HISTORY
Number
Description
-001
Original version
-002
Section 3.4,
V
PP
Program and Erase Voltages, added
Updated Figure 9:
Automated Block Erase Flowchart
Updated Figure 10:
Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16:
AC Waveform: Program and Erase Operations (updated notes)
I
PPR
maximum specification change from ±25
µ
A to ±50
µ
A
Program and Erase Suspend Latency specification change
Updated Appendix A:
Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D:
Architecture Block Diagram (Block info. in words not
bytes)
Minor wording changes
-003
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V
PP
read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved
Ordering Information from Appendix to Section 6.0; updated information
Moved
Additional Information from Appendix to Section 7.0
Updated figure Appendix B,
Access Time vs. Capacitive Load
Updated figure Appendix C,
Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated
Program Flowchart
Updated
Program Suspend/Resume Flowchart
Minor text edits throughout.
-004
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A
1
–A
20
= 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
V
CC
and V
CCQ
absolute maximum specification = 3.7 V (Section 4.1)
Combined I
PPW
and I
CCW
into one specification (Section 4.4)
Combined I
PPE
and I
CCE
into one specification (Section 4.4)
Max Parameter Block Erase Time (t
WHQV2
/t
EHQV2
) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (t
WHQV3
/t
EHQV3
) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (t
WHRH2
/t
EHRH2
) changed to 5 µs typical and 20 µs
maximum (Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
-005
µ
BGA package diagrams corrected (Figures 3 and 4)
I
PPD
test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µ
BGA package top side mark information added (Section 6)
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SMART 3 ADVANCED BOOT BLOCK
5
PRELIMINARY
1.0
INTRODUCTION
This datasheet contains the specifications for the
Advanced Boot Block flash memory family, which is
optimized for low power, portable systems. This
family of products features 1.65 V–2.5 V or 2.7 V–
3.6 V I/Os and a low V
CC
/V
PP
operating range of
2.7
V–3.6
V for read, program, and erase
operations. In addition this family is capable of fast
programming at 12 V. Throughout this document,
the term “2.7 V” refers to the full voltage range
2.7 V–3.6 V (except where noted otherwise) and
“V
PP
= 12 V” refers to 12 V ±5%. Section 1.0 and
2.0 provide an overview of the flash memory family
including applications, pinouts and pin descriptions.
Section 3.0 describes the memory organization and
operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally,
Sections 6.0 and 7.0 provide ordering and other
reference information.
1.1
Smart 3 Advanced Boot Block
Flash Memory Enhancements
The Smart 3 Advanced Boot Block flash memory
features
•
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
•
Program Suspend to Read command
•
V
CCQ
input of 1.65 V–2.5 V on all I/Os. See
Figures 1 through 4 for pinout diagrams and
V
CCQ
location
•
Maximum program and erase time specification
for improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature
28F008B3, 28F016B3,
28F032B3
(1)
28F400B3
(2),
28F800B3,
28F160B3, 28F320B3
Reference
V
CC
Read Voltage
2.7 V– 3.6 V
Section 4.2, 4.4
V
CCQ
I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
Section 4.2, 4.4
V
PP
Program/Erase Voltage
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
Bus Width
8-bit
16 bit
Table 3
Speed
80 ns, 90 ns, 100 ns, 110 ns
Section 4.5
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit),
4096 Kbit x 8 (32 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit)
2048 Kbit x 16 (32 Mbit)
Section 2.2
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4-Mbit) or
Fifteen 64-Kbyte blocks (8-Mbit) or
Thirty-one 64-Kbyte main blocks (16-Mbit)
Sixty-three 64-Kbyte main blocks (32-Mbit)
Section 2.2
Appendix D
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
Section 3.3
Table 8
Operating Temperature
Extended: –40
°
C to +85
°
C
Section 4.2, 4.4
Program/Erase Cycling
100,000 cycles
Section 4.2, 4.4
Packages
40-lead TSOP
(1)
, 48-Ball
µ
BGA* CSP
(2)
48-Lead TSOP, 48-Ball
µ
BGA CSP
(2)
Figure 3, Figure 4
NOTES:
1.
4-Mbit and 32-Mbit density not available in 40-lead TSOP.
2.
4-Mbit density not available in
µ
BGA* CSP.
SMART 3 ADVANCED BOOT BLOCK
E
6
PRELIMINARY
1.2
Product Overview
Intel provides the most flexible voltage solution in
the flash industry, providing three discrete voltage
supply pins: V
CC
for read operation, V
CCQ
for output
swing, and V
PP
for program and erase operation. All
Smart 3 Advanced Boot Block flash memory
products provide program/erase capability at 2.7 V
or 12 V [for fast production programming] and read
with V
CC
at 2.7 V. Since many designs read from
the flash memory a large percentage of the time,
2.7 V V
CC
operation can provide substantial power
savings.
The Smart 3 Advanced Boot Block flash memory
products are available in either x8 or x16 packages
in the following densities: (see
Ordering Information
for availability.)
•
4-Mbit (4,194,304-bit) flash memory organized
as 256 Kwords of 16 bits each or 512 Kbytes of
8-bits each
•
8-Mbit (8,388,608-bit) flash memory organized
as 512 Kwords of 16 bits each or 1024 Kbytes
of 8-bits each
•
16-Mbit (16,777,216-bit) flash memory
organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
•
32-Mbit (33,554,432-bit) flash memory
organized as 2048 Kwords of 16 bits each or
4096 Kbytes of 8-bits each
The parameter blocks are located at either the top
(denoted by -T suffix) or the bottom (-B suffix) of the
address map in order to accommodate different
microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can
be locked to provide complete code security for
system initialization code. Locking and unlocking is
controlled by WP# (see Section 3.3 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby un-
burdening the microprocessor or microcontroller.
The status register indicates the status of the WSM
by signifying block erase or word program
completion and status.
The Smart 3 Advanced Boot Block flash memory is
also designed with an Automatic Power Savings
(APS) feature which minimizes system current
drain, allowing for very low power designs. This
mode is entered following the completion of a read
cycle (approximately 300 ns later).
The RP# pin provides additional protection against
unwanted command writes that may occur during
system reset and power-up/down sequences due to
invalid system bus conditions (see Section 3.6).
Section 3.0 gives detailed explanation of the
different modes of operation. Complete current and
voltage specifications can be found in the
DC
Characteristics section. Refer to AC Characteristics
for read, program and erase performance
specifications.
2.0
PRODUCT DESCRIPTION
This section explains device pin description and
package pinouts.
2.1
Package Pinouts
The Smart 3 Advanced Boot Block flash memory is
available in 40-lead TSOP (x8, Figure 1), 48-lead
TSOP (x16, Figure 2) and 48-ball
µ
BGA packages
(x8 and x16, Figure 3 and Figure 4 respectively). In
all figures, pin changes necessary for density
upgrades have been circled.
E
SMART 3 ADVANCED BOOT BLOCK
7
PRELIMINARY
A
17
GND
A
20
A
19
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
DQ
0
OE#
GND
CE#
A
0
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
V
PP
WP#
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
16 M
8 M
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0580_01
NOTES:
1.
40-Lead TSOP available for 8- and 16-Mbit densities only.
2.
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pin 38.
Figure 1. 40-Lead TSOP Package for x8 Configurations
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32 M
4 M
16 M
8 M
0580_02
NOTE:
Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 15.
Figure 2. 48-Lead TSOP Package for x16 Configurations
SMART 3 ADVANCED BOOT BLOCK
E
8
PRELIMINARY
A
14
A
15
A
16
A
17
V
CCQ
A
12
A
10
A
13
NC
A
11
A
8
WE#
A
9
D
5
D
6
V
PP
RP#
NC
NC
WP#
A
19
A
21
D
2
D
3
A
20
A
18
A
6
NC
NC
A
7
A
5
A
3
CE#
D
0
A
4
A
2
A
1
A
0
GND
GND
D
7
NC
D
4
V
CC
NC
D
1
OE#
A
B
C
D
E
F
1
3
2
5
4
7
6
8
16M
32M
8M
0580_04
NOTE:
1.
Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A
20
is the upgrade address for the 16-Mbit device. A
21
is the
upgrade address for the 32-Mbit device.
2.
4-Mbit density not available in
µ
BGA* CSP.
Figure 3. x8 48-Ball
µ
BGA* Chip Size Package (Top View, Ball Down)
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SMART 3 ADVANCED BOOT BLOCK
9
PRELIMINARY
A
13
A
14
A
15
A
16
V
CCQ
A
11
A
10
A
12
D
14
D
15
A
8
WE#
A
9
D
5
D
6
V
PP
RP#
D
11
D
12
WP#
A
18
A
20
D
2
D
3
A
19
A
17
A
6
D
8
D
9
A
7
A
5
A
3
CE#
D
0
A
4
A
2
A
1
A
0
GND
GND
D
7
D
13
D
4
V
CC
D
10
D
1
OE#
A
B
C
D
E
F
1
3
2
5
4
7
6
8
16M
32M
8M
0580_03
NOTES:
1.
Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address
solder balls. Routing is not recommended in this area. A
19
is the upgrade address for the 16-Mbit device. A
20
is the
upgrade address for the 32-Mbit device.
2.
4-Mbit density not available in
µ
BGA* CSP.
Figure 4. x16 48-Ball
µ
BGA* Chip Size Package (Top View, Ball Down)
SMART 3 ADVANCED BOOT BLOCK
E
10
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. Smart 3 Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20], 28F032B3: A[0-21],
28F800B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20]
DQ
0
–DQ
7
INPUT/OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The
data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and identifier data. The data pins float to tri-state when the
chip is de-selected. Not included on x8 products.
CE#
INPUT
CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN: Uses two voltage levels (V
IL
, V
IH
) to