Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993
November 1993
Order Number: 270727-006
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
• Two Instructions/Clock Sustained Execution
• Four 59 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-bit Burst Bus with Pipelining
s
32-bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-bit Global Registers
— Sixteen 32-bit Local Registers
— Manipulates 64-bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
s
Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
s
On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
s
On-Chip Instruction Cache
— 1 Kbyte Two-Way Set Associative
— 128-bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
s
High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
s
Four On-Chip DMA Channels
— 59 Mbytes/s Fly-by Transfers
— 32 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
s
32-Bit Demultiplexed Burst Bus
— 128-bit Internal Data Paths to and
from Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
s
Selectable Big or Little Endian Byte
Ordering
s
High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 750 ns Typical
ii
CONTENTS
PAGE
1.0 PURPOSE .................................................................................................................................................. 1
2.0 80960CA OVERVIEW................................................................................................................................. 1
2.1 The C-Series Core ..............................................................................................................................2
2.2 Pipelined, Burst Bus ...........................................................................................................................2
2.3 Flexible DMA Controller ......................................................................................................................2
2.4 Priority Interrupt Controller ..................................................................................................................2
2.5 Instruction Set Summary ....................................................................................................................3
3.0 PACKAGE INFORMATION.........................................................................................................................4
3.1 Package Introduction ..........................................................................................................................4
3.2 Pin Descriptions .................................................................................................................................. 4
3.3 80960CA Mechanical Data ............................................................................................................... 11
3.3.1 80960CA PGA Pinout ............................................................................................................ 11
3.3.2 80960CA PQFP Pinout .......................................................................................................... 15
3.4 Package Thermal Specifications ...................................................................................................... 18
3.5 Stepping Register Information .......................................................................................................... 20
3.6 Suggested Sources for 80960CA Accessories.................................................................................. 20
4.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 21
4.1 Absolute Maximum Ratings .............................................................................................................. 21
4.2 Operating Conditions ........................................................................................................................ 21
4.3 Recommended Connections ............................................................................................................ 21
4.4 DC Specifications ............................................................................................................................. 22
4.5 AC Specifications .............................................................................................................................. 23
4.5.1 AC Test Conditions ................................................................................................................ 29
4.5.2 AC Timing Waveforms ........................................................................................................... 29
4.5.3 Derating Curves ..................................................................................................................... 33
5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................. 35
6.0 BUS WAVEFORMS ................................................................................................................................. 36
7.0 REVISION HISTORY ................................................................................................................................ 64
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
iii
CONTENTS
PAGE
LIST OF FIGURES
Figure 1
80960CA Block Diagram .............................................................................................................. 1
Figure 2
80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13
Figure 3
80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14
Figure 4
80960CA PQFP Pinout (View from Top Side) ............................................................................ 17
Figure 5
Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18
Figure 6
Register g0 ................................................................................................................................. 20
Figure 7
AC Test Load .............................................................................................................................. 29
Figure 8
Input and Output Clocks Waveform ............................................................................................ 29
Figure 9
CLKIN Waveform ........................................................................................................................ 29
Figure 10
Output Delay and Float Waveform ............................................................................................. 30
Figure 11
Input Setup and Hold Waveform ................................................................................................ 30
Figure 12
NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31
Figure 13
Hold Acknowledge Timings ........................................................................................................ 31
Figure 14
Bus Backoff (BOFF) Timings ...................................................................................................... 32
Figure 15
Relative Timings Waveforms ...................................................................................................... 33
Figure 16
Output Delay or Hold vs. Load Capacitance .............................................................................. 33
Figure 17
Rise and Fall Time Derating at Highest Operating Temperature and Minimum V
CC
.................. 34
Figure 18
I
CC
vs. Frequency and Temperature ........................................................................................... 34
Figure 19
Cold Reset Waveform ................................................................................................................ 36
Figure 20
Warm Reset Waveform .............................................................................................................. 37
Figure 21
Entering the ONCE State ........................................................................................................... 38
Figure 22
Clock Synchronization in the 2-x Clock Mode ............................................................................ 39
Figure 23
Clock Synchronization in the 1-x Clock Mode ............................................................................ 39
Figure 24
Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40
Figure 25
Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41
Figure 26
Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42
Figure 27
Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43
Figure 28
Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44
Figure 29
Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45
Figure 30
Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46
Figure 31
Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47
Figure 32
Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48
Figure 33
Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49
Figure 34
Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50
Figure 35
Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51
Figure 36
Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52
Figure 37
Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53
Figure 38
Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54
iv
CONTENTS
PAGE
LIST OF FIGURES (continued)
Figure 39
Using External READY ............................................................................................................... 55
Figure 40
Terminating a Burst with BTERM ............................................................................................... 56
Figure 41
BOFF Functional Timing ............................................................................................................ 57
Figure 42
HOLD Functional Timing ............................................................................................................ 58
Figure 43
DREQ and DACK Functional Timing .......................................................................................... 59
Figure 44
EOP Functional Timing .............................................................................................................. 59
Figure 45
Terminal Count Functional Timing .............................................................................................. 60
Figure 46
FAIL Functional Timing ............................................................................................................... 60
Figure 47
A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61
Figure 48
A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62
Figure 49
Idle Bus Operation ...................................................................................................................... 63
LIST OF TABLES
Table 1
80960CA Instruction Set .............................................................................................................. 3
Table 2
Pin Description Nomenclature ...................................................................................................... 4
Table 3
80960CA Pin Description — External Bus Signals ...................................................................... 5
Table 4
80960CA Pin Description — Processor Control Signals .............................................................. 8
Table 5
80960CA Pin Description — DMA and Interrupt Unit Control Signals ....................................... 10
Table 6
80960CA PGA Pinout — In Signal Order ................................................................................... 11
Table 7
80960CA PGA Pinout — In Pin Order ........................................................................................ 12
Table 8
80960CA PQFP Pinout — In Signal Order ................................................................................. 15
Table 9
80960CA PQFP Pinout — In Pin Order ..................................................................................... 16
Table 10
Maximum T
A
at Various Airflows in
o
C (PGA Package Only) ..................................................... 18
Table 11
80960CA PGA Package Thermal Characteristics ...................................................................... 19
Table 12
80960CA PQFP Package Thermal Characteristics .................................................................... 19
Table 13
Die Stepping Cross Reference ................................................................................................... 20
Table 14
Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21
Table 15
DC Characteristics ..................................................................................................................... 22
Table 16
80960CA AC Characteristics (33 MHz) ...................................................................................... 23
Table 17
80960CA AC Characteristics (25 MHz) ...................................................................................... 25
Table 18
80960CA AC Characteristics (16 MHz) ...................................................................................... 27
Table 19
Reset Conditions ........................................................................................................................ 35
Table 20
Hold Acknowledge and Backoff Conditions ................................................................................ 35
1
80960CA-33, -25, -16
1.0
PURPOSE
This document provides electrical characteristics for
the 33, 25 and 16 MHz versions of the 80960CA. For
a detailed description of any 80960CA functional
topic—other than parametric performance—consult
the 80960CA Product Overview (Order No. 270669)
or the i960
®
CA Microprocessor User’s Manual
(Order No. 270710). To obtain data sheet updates
and errata, please call Intel’s FaxBACK
®
data-on-
demand system (1-800-628-2283 or 916-356-3105).
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600).
2.0
80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors. The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip
peripherals and instruction set extensions to shift 64-
bit operands and configure on-chip hardware.
Multiple 128-bit internal buses, on-chip instruction
caching and a sophisticated instruction scheduler
allow the processor to sustain execution of two
instructions every clock and peak at execution of
three instructions per clock.
A 32-bit demultiplexed and pipelined burst bus
provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory sub-system. In
addition, the 80960CA’s on-chip caching of instruc-
tions, procedure context and critical program data
substantially decouple system performance from the
wait states associated with accesses to the system’s
slower, cost sensitive, main memory subsystem.
The 80960CA bus controller integrates full wait state
and bus width control for highest system perfor-
mance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA.
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip. DMA channels perform: single-
cycle or two-cycle transfers, data packing and
unpacking and data chaining. Block transfers—in
addition to source or destination synchronized trans-
fers—are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (”latency”) time of
750 ns.
Figure 1. 80960CA Block Diagram
Execution
Unit
Programmable
Bus
Controller
Bus Request
Queues
Six-port
Register File
64-Bit
SRC1 Bus
64-Bit
SRC2 Bus
64-Bit
DST Bus
32-Bit
Base Bus
128-Bit
Load Bus
128-Bit
Store Bus
Instruction Prefetch Queue
Instruction Cache
(1 KByte, Two-way
Set Associative)
128-BIT CACHE BUS
Interrupt Controller
Control
Address
Data
Memory-side
Machine Bus
Register-side
Machine Bus
Parallel
Instruction
Scheduler
Memory Region
Configuration
Multiply/Divide
Unit
Four-Channel
DMA Controller
Interrupt
Port
1 KByte
5 to 15 Sets
Register Cache
Data RAM
Address
Generation Unit
F_CX001A
DMA
Port
2
80960CA-33, -25, -16
2.1
The C-Series Core
The C-Series core is a very high performance
microarchitectural implementation of the 80960 Core
Architecture. The C-Series core can sustain execu-
tion of two instructions per clock (66 MIPs at
33 MHz). To achieve this level of performance, Intel
has incorporated state-of-the-art silicon technology
and innovative microarchitectural constructs into the
implementation of the C-Series core. Factors that
contribute to the core’s performance include:
•
Parallel instruction decoding allows issuance of
up to three instructions per clock
•
Single-clock execution of most instructions
•
Parallel instruction decode allows sustained,
simultaneous execution of two single-clock
instructions every clock cycle
•
Efficient instruction pipeline minimizes pipeline
break losses
•
Register and resource scoreboarding allow simul-
taneous multi-clock instruction execution
•
Branch look-ahead and prediction allows many
branches to execute with no pipeline break
•
Local Register Cache integrated on-chip caches
Call/Return context
•
Two-way set associative, 1 Kbyte integrated
instruction cache
•
1 Kbyte integrated Data RAM sustains a four-
word (128-bit) access every clock cycle
2.2
Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces
the 80960CA to external memory and peripherals.
The Bus Control Unit features a maximum transfer
rate of 132 Mbytes per second (at 33 MHz). Inter-
nally programmable wait states and 16 separately
configurable memory regions allow the processor to
interface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance. The Bus Controller’s main features
include:
•
Demultiplexed, Burst Bus to exploit most efficient
DRAM access modes
•
Address Pipelining to reduce memory cost while
maintaining performance
•
32-, 16- and 8-bit modes for I/O interfacing ease
•
Full internal wait state generation to reduce
system cost
•
Little and Big Endian support to ease application
development
•
Unaligned access support for code portability
•
Three-deep request queue to decouple the bus
from the core
2.3
Flexible DMA Controller
A four-channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory. The DMA provides advanced features
such as data chaining, byte assembly and disas-
sembly and a high performance fly-by mode capable
of transfer speeds of up to 59 Mbytes per second at
33 MHz. The DMA controller features a performance
and flexibility which is only possible by integrating the
DMA controller and the 80960CA core.
2.4
Priority Interrupt Controller
A programmable-priority interrupt controller
manages up to 248 external sources through the 8-
bit external interrupt port. The Interrupt Unit also
handles the four internal sources from the DMA
controller and a single non-maskable interrupt input.
The 8-bit interrupt port can also be configured to
provide individual interrupt sources that are level or
edge triggered.
Interrupts in the 80960CA are prioritized and
signaled within 270 ns of the request. If the interrupt
is of higher priority than the processor priority, the
context switch to the interrupt routine typically is
complete in another 480 ns. The interrupt unit
provides the mechanism for the low latency and high
throughput interrupt service which is essential for
embedded applications.
3
80960CA-33, -25, -16
2.5
Instruction Set Summary
Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960
®
CA Microprocessor User’s
Manual for a complete description of the instruction set.
Table 1. 80960CA Instruction Set
Data
Movement
Arithmetic
Logical
Bit and Bit Field
and Byte
Load
Store
Move
Load Address
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
*Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
Rotate
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Modify
Scan Byte for Equal
Comparison
Branch
Call/Return
Fault
Compare
Conditional Compare
Compare and
Increment
Compare and
Decrement
Test Condition Code
Check Bit
Unconditional Branch
Conditional Branch
Compare and Branch
Call
Call Extended
Call System
Return
Branch and Link
Conditional Fault
Synchronize Faults
Debug
Processor
Management
Atomic
Modify Trace Controls
Mark
Force Mark
Flush Local Registers
Modify Arithmetic
Controls
Modify Process
Controls
*System Control
*DMA Control
Atomic Add
Atomic Modify
NOTES:
Instructions marked by (*) are 80960CA extensions to the 80960 instruction set.
4
80960CA-33, -25, -16
3.0
PACKAGE INFORMATION
3.1
Package Introduction
This section describes the pins, pinouts and thermal
characteristics for the 80960CA in the 168-pin
Ceramic Pin Grid Array (PGA) package and the 196-
pin Plastic Quad Flat Package (PQFP). For complete
package specifications and information, see the
Packaging Handbook (Order No. 240800).
3.2
Pin Descriptions
The 80960CA pins are described in this section.
Table 2 presents the legend for interpreting the pin
descriptions in the following tables. Pins associated
with the 32-bit demultiplexed processor bus are
described in Table 3. Pins associated with basic
processor configuration and control are described in
Table 4. Pins associated with the 80960CA DMA
Controller and Interrupt Unit are described in Table
5.
All pins float while the processor is in the ONCE
mode.
Table 2. Pin Description Nomenclature
Symbol
Description
I
Input only pin
O
Output only pin
I/O
Pin can be either an input or output
–
Pins “must be” connected as described
S(...)
Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. All outputs are
synchronous to PCLK2:1.
S(E)
Edge sensitive input
S(L)
Level sensitive input
A(...)
Asynchronous. Inputs may be
asynchronous to PCLK2:1.
A(E)
Edge sensitive input
A(L)
Level sensitive input
H(...)
While the processor’s bus is in the
Hold Acknowledge or Bus Backoff state,
the pin:
H(1)
is driven to V
CC
H(0)
is driven to V
SS
H(Z)
floats
H(Q)
continues to be a valid input
R(...)
While the processor’s RESET pin is low,
the pin:
R(1)
is driven to V
CC
R(0)
is driven to V
SS
R(Z)
floats
R(Q)
continues to be a valid output
5
80960CA-33, -25, -16
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 1 of 3)
Name
Type
Description
A31:2
O
S
H(Z)
R(Z)
ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most
significant address bit; A2 is the least significant. During a bus access, A31:2 identify
all external addresses to word (4-byte) boundaries. The byte enable signals indicate
the selected byte in each word. During burst accesses, A3:2 increment to indicate
successive data cycles.
D31:0
I/O
S(L)
H(Z)
R(Z)
DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configu-
ration. The least significant bit of the data is carried on D0 and the most significant on
D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used.
For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is
used.
BE3:0
O
S
H(Z)
R(1)
BYTE ENABLES select which of the four bytes addressed by A31:2 are active during
an access to a memory region configured for a 32-bit data-bus width. BE3 applies to
D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.
32-bit bus:
BE3
–Byte Enable 3
–enable D31:24
BE2
–Byte Enable 2
–enable D23:16
BE1
–Byte Enable 1
–enable D15:8
BE0
–Byte Enable 0
–enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the
processor uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.
16-bit bus:
BE3
–Byte High Enable (BHE)
–enable D15:8
BE2
–Not used (driven high or low)
BE1
–Address Bit 1 (A1)
BE0
–Byte Low Enable (BLE)
–enable D7:0
For accesses to a memory region configured for an 8-bit data-bus width, the
processor uses the BE1 and BE0 pins as A1 and A0 respectively.
8-bit bus:
BE3
–Not used (driven high or low)
BE2
–Not used (driven high or low)
BE1
–Address Bit 1 (A1)
BE0
–Address Bit 0 (A0)
W/R
O
S
H(Z)
R(0)
WRITE/READ is asserted for read requests and deasserted for write requests. The
W/R signal changes in the same clock cycle as ADS. It remains valid for the entire
access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be
valid in the last cycle of a read access.
ADS
O
S
H(Z)
R(1)
ADDRESS STROBE indicates a valid address and the start of a new bus access.
ADS is asserted for the first clock of a bus access.
6
80960CA-33, -25, -16
READY
I
S(L)
H(Z)
R(Z)
READY is an input which signals the termination of a data transfer. READY is used to
indicate that read data on the bus is valid or that a write-data transfer has completed.
The READY signal works in conjunction with the internally programmed wait-state
generator. If READY is enabled in a region, the pin is sampled after the programmed
number of wait-states has expired. If the READY pin is deasserted, wait states
continue to be inserted until READY becomes asserted. This is true for the N
RAD
,
N
RDD
, N
WAD
and N
WDD
wait states. The N
XDA
wait states cannot be extended.
BTERM
I
S(L)
H(Z)
R(Z)
BURST TERMINATE is an input which breaks up a burst access and causes another
address cycle to occur. The BTERM signal works in conjunction with the internally
programmed wait-state generator. If READY and BTERM are enabled in a region, the
BTERM pin is sampled after the programmed number of wait states has expired.
When BTERM is asserted, a new ADS signal is generated and the access is
completed. The READY input is ignored when BTERM is asserted. BTERM must be
externally synchronized to satisfy BTERM setup and hold times.
WAIT
O
S
H(Z)
R(1)
WAIT indicates internal wait state generator status. WAIT is asserted when wait
states are being caused by the internal wait state generator and not by the READY or
BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be
thought of as a READY output that the processor provides when it is inserting wait
states.
BLAST
O
S
H(Z)
R(0)
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses after the wait state counter reaches
zero. BLAST remains asserted until the clock following the last cycle of the last data
transfer of a bus access. If the READY or BTERM input is used to extend wait states,
the BLAST signal remains asserted until READY or BTERM terminates the access.
DT/R
O
S
H(Z)
R(0)
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in
conjunction with DEN to provide control for data transceivers attached to the external
bus. When DT/R is asserted, the signal indicates that the processor receives data.
Conversely, when deasserted, the processor sends data. DT/R changes only while
DEN is high.
DEN
O
S
H(Z)
R(1)
DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of
the bus request first data cycle and is deasserted at the end of the last data cycle.
DEN is used in conjunction with DT/R to provide control for data transceivers attached
to the external bus. DEN remains asserted for sequential reads from pipelined
memory regions. DEN is deasserted when DT/R changes.
LOCK
O
S
H(Z)
R(1)
BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK
may be used to prevent external agents from accessing memory which is currently
involved in an atomic operation. LOCK is asserted in the first clock of an atomic
operation and deasserted in the clock cycle following the last bus access for the
atomic operation. To allow the most flexibility for memory system enforcement of
locked accesses, the processor acknowledges a bus hold request when LOCK is
asserted. The processor performs DMA transfers while LOCK is active.
HOLD
I
S(L)
H(Z)
R(Z)
HOLD REQUEST signals that an external agent requests access to the external bus.
The processor asserts HOLDA after completing the current bus request. HOLD,
HOLDA and BREQ are used together to arbitrate access to the processor’s external
bus by external bus agents.
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 2 of 3)
Name
Type
Description
7
80960CA-33, -25, -16
BOFF
I
S(L)
H(Z)
R(Z)
BUS BACKOFF, when asserted, suspends the current access and causes the bus
pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock
cycle and the access is resumed.
HOLDA
O
S
H(1)
R(Q)
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relin-
quished control of the external bus. When HOLDA is asserted, the external address
bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ
are used together to arbitrate access to the processor’s external bus by external bus
agents. Since the processor grants HOLD requests and enters the Hold Acknowledge
state even while RESET is asserted, the state of the HOLDA pin is independent of the
RESET pin.
BREQ
O
S
H(Q)
R(0)
BUS REQUEST is asserted when the bus controller has a request pending. BREQ
can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to
determine when to return mastership of the external bus to the processor.
D/C
O
S
H(Z)
R(Z)
DATA OR CODE is asserted for a data request and deasserted for instruction
requests. D/C has the same timing as W/R.
DMA
O
S
H(Z)
R(Z)
DMA ACCESS indicates whether the bus request was initiated by the DMA controller.
DMA is asserted for any DMA request. DMA is deasserted for all other requests.
SUP
O
S
H(Z)
R(Z)
SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode. SUP is asserted when the request has supervisor privileges and is
deasserted otherwise. SUP can be used to isolate supervisor code and data
structures from non-supervisor requests.
Table 3. 80960CA Pin Description — External Bus Signals (Sheet 3 of 3)
Name
Type
Description
8
80960CA-33, -25, -16
Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 1 of 2)
Name
Type
Description
RESET
I
A(L)
H(Z)
R(Z)
RESET causes the chip to reset. When RESET is asserted, all external signals
return to the reset state. When RESET is deasserted, initialization begins. When
the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles
before being deasserted to guarantee correct processor initialization. When the 1-x
clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles
before being deasserted to guarantee correct processor initialization. The
CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin.
The processor’s Hold Acknowledge bus state functions while the chip is reset. If the
processor’s bus is in the Hold Acknowledge state when RESET is asserted, the
processor will internally reset, but maintains the Hold Acknowledge state on
external pins until the Hold request is removed. If a Hold request is made while the
processor is in the reset state, the processor bus will grant HOLDA and enter the
Hold Acknowledge state.
FAIL
O
S
H(Q)
R(0)
FAIL indicates failure of the processor’s self-test performed at initialization. When
RESET is deasserted and the processor begins initialization, the FAIL pin is
asserted. An internal self-test is performed as part of the initialization process. If
this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The
FAIL pin is reasserted while the processor performs an external bus self-confidence
test. If this self-test passes, the processor deasserts the FAIL pin and branches to
the user’s initialization routine; otherwise the FAIL pin remains asserted. Internal
self-test and the use of the FAIL pin can be disabled with the STEST pin.
STEST
I
S(L)
H(Z)
R(Z)
SELF TEST causes the processor’s internal self-test feature to be enabled or
disabled at initialization. STEST is read on the rising edge of RESET. When
asserted, the processor’s internal self-test and external bus confidence tests are
performed during processor initialization. When deasserted, only the bus
confidence tests are performed during initialization.
ONCE
I
A(L)
H(Z)
R(Z)
ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE
is continuously sampled while RESET is low and is latched on the rising edge of
RESET. To place the processor in the ONCE state:
(1)
assert RESET and ONCE (order does not matter)
(2)
wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN periods in
1-x mode—after V
CC
and CLKIN are within operating specifications
(3)
deassert RESET
(4)
wait at least 32 CLKIN periods
(The processor will now be latched in the ONCE state as long as RESET is high.)
To exit the ONCE state, bring V
CC
and CLKIN to operating conditions, then assert
RESET and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions of the processor until
Step 4 above has been completed. CLKIN may then be changed to DC to achieve
the lowest possible ONCE mode leakage current.
ONCE can be used by emulator products or for board testers to effectively make an
installed processor transparent in the board.
9
80960CA-33, -25, -16
CLKIN