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October 1994

Order Number 231244-006

82C54

CHMOS PROGRAMMABLE INTERVAL TIMER

Compatible with all Intel and most

other microprocessors

High Speed ‘‘Zero Wait State’’

Operation with 8 MHz 8086 88 and

80186 188

Handles Inputs from DC

10 MHz for 82C54-2

Available in EXPRESS

Standard Temperature Range

Extended Temperature Range

Three independent 16-bit counters

Low Power CHMOS

10 mA

8 MHz Count

frequency

Completely TTL Compatible

Six Programmable Counter Modes

Binary or BCD counting

Status Read Back Command

Available in 24-Pin DIP and 28-Pin PLCC

The Intel 82C54 is a high-performance CHMOS version of the industry standard 8254 counter timer which is

designed to solve the timing control problems common in microcomputer system design It provides three

independent 16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software

programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253

Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator

programmable one-shot and in many other applications

The 82C54 is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption

with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24-pin DIP

and 28-pin plastic leaded chip carrier (PLCC) packages

231244 – 1

Figure 1 82C54 Block Diagram

231244 – 3

PLASTIC LEADED CHIP CARRIER

231244 – 2

Diagrams are for pin reference only

Package sizes are not to scale

Figure 2 82C54 Pinout

82C54

Table 1 Pin Description

Symbol

Pin Number

Type

Function

DIP

PLCC

-D

1-8

2-9

I O

Data Bidirectional tri-state data bus lines

connected to system data bus

CLK 0

Clock 0 Clock input of Counter 0

OUT 0

Output 0 Output of Counter 0

GATE 0

Gate 0 Gate input of Counter 0

GND

Ground Power supply connection

OUT 1

Out 1 Output of Counter 1

GATE 1

Gate 1 Gate input of Counter 1

CLK 1

Clock 1 Clock input of Counter 1

GATE 2

Gate 2 Gate input of Counter 2

OUT 2

Out 2 Output of Counter 2

CLK 2

Clock 2 Clock input of Counter 2

20-19

23-22

Address Used to select one of the three Counters

or the Control Word Register for read or write

operations Normally connected to the system

address bus

Selects

Counter 0

Counter 1

Counter 2

Control Word Register

Chip Select A low on this input enables the 82C54

to respond to RD and WR signals RD and WR are

ignored otherwise

Read Control This input is low during CPU read

operations

Write Control This input is low during CPU write

operations

Power a5V power supply connection

1 11 15 25

No Connect

FUNCTIONAL DESCRIPTION

General

The 82C54 is a programmable interval timer counter

designed for use with Intel microcomputer systems

It is a general purpose multi-timing element that can

be treated as an array of I O ports in the system

software

The 82C54 solves one of the most common prob-

lems in any microcomputer system the generation

of accurate time delays under software control In-

stead of setting up timing loops in software the pro-

grammer configures the 82C54 to match his require-

ments and programs one of the counters for the de-

sired delay After the desired delay the 82C54 will

interrupt the CPU Software overhead is minimal and

variable length delays can easily be accommodated

Some of the other counter timer functions common

to microcomputers which can be implemented with

the 82C54 are

Real time clock

Even counter

Digital one-shot

Programmable rate generator

Square wave generator

Binary rate multiplier

Complex waveform generator

Complex motor controller

82C54

Block Diagram

DATA BUS BUFFER

This 3-state bi-directional 8-bit buffer is used to in-

terface the 82C54 to the system bus (see Figure 3)

231244 – 4

Figure 3 Block Diagram Showing Data Bus

Buffer and Read Write Logic Functions

READ WRITE LOGIC

The Read Write Logic accepts inputs from the sys-

tem bus and generates control signals for the other

functional blocks of the 82C54 A

and A

select

one of the three counters or the Control Word Regis-

ter to be read from written into A ‘‘low’’ on the RD

input tells the 82C54 that the CPU is reading one of

the counters A ‘‘low’’ on the WR input tells the

82C54 that the CPU is writing either a Control Word

or an initial count Both RD and WR are qualified by

CS RD and WR are ignored unless the 82C54 has

been selected by holding CS low

The WR

and CLK signals should be synchronous

This is accomplished by using a CLK input signal to

the 82C54 counters which is a derivative of the sys-

tem clock source Another technique is to externally

synchronize the WR

and CLK input signals This is

done by gating WR

with CLK

CONTROL WORD REGISTER

The Control Word Register (see Figure 4) is selected

by the Read Write Logic when A

11 If the

CPU then does a write operation to the 82C54 the

data is stored in the Control Word Register and is

interpreted as a Control Word used to define the

operation of the Counters

The Control Word Register can only be written to

status information is available with the Read-Back

Command

231244 – 5

Figure 4 Block Diagram Showing Control Word

COUNTER 0 COUNTER 1 COUNTER 2

These three functional blocks are identical in opera-

tion so only a single Counter will be described The

internal block diagram of a single counter is shown

in Figure 5

The Counters are fully independent Each Counter

may operate in a different Mode

The Control Word Register is shown in the figure it

is not part of the Counter itself but its contents de-

termine how the Counter operates

82C54

231244 – 6

Figure 5 Internal Block Diagram of a Counter

The status register shown in the Figure when

latched contains the current contents of the Control

Word Register and status of the output and null

count flag (See detailed explanation of the Read-

Back command )

The actual counter is labelled CE (for ‘‘Counting Ele-

ment’’) It is a 16-bit presettable synchronous down

counter

and OL

are two 8-bit latches OL stands for

‘‘Output Latch’’ the subscripts M and L stand for

‘‘Most significant byte’’ and ‘‘Least significant byte’’

respectively Both are normally referred to as one

unit and called just OL These latches normally ‘‘fol-

low’’ the CE but if a suitable Counter Latch Com-

mand is sent to the 82C54 the latches ‘‘latch’’ the

present count until read by the CPU and then return

to ‘‘following’’ the CE One latch at a time is enabled

by the counter’s Control Logic to drive the internal

bus This is how the 16-bit Counter communicates

over the 8-bit internal bus Note that the CE itself

cannot be read whenever you read the count it is

the OL that is being read

Similarly there are two 8-bit registers called CR

and CR

(for ‘‘Count Register’’) Both are normally

referred to as one unit and called just CR When a

new count is written to the Counter the count is

stored in the CR and later transferred to the CE The

Control Logic allows one register at a time to be

loaded from the internal bus Both bytes are trans-

ferred to the CE simultaneously CR

and CR

are

cleared when the Counter is programmed In this

way if the Counter has been programmed for one

byte counts (either most significant byte only or least

significant byte only) the other byte will be zero

Note that the CE cannot be written into whenever a

count is written it is written into the CR

The Control Logic is also shown in the diagram CLK

n GATE n and OUT n are all connected to the out-

side world through the Control Logic

82C54 SYSTEM INTERFACE

The 82C54 is treated by the systems software as an

array of peripheral I O ports three are counters and

the fourth is a control register for MODE program-

ming

Basically the select inputs A

connect to the A

address bus signals of the CPU The CS can be

derived directly from the address bus using a linear

select method Or it can be connected to the output

of a decoder such as an Intel 8205 for larger sys-

tems

231244 – 7

Figure 6 82C54 System Interface

82C54

OPERATIONAL DESCRIPTION

General

After power-up the state of the 82C54 is undefined

The Mode count value and output of all Counters

are undefined

How each Counter operates is determined when it is

programmed Each Counter must be programmed

before it can be used Unused counters need not be

programmed

Programming the 82C54

Counters are programmed by writing a Control Word

and then an initial count The control word format is

shown in Figure 7

All Control Words are written into the Control Word

11 The

Control Word itself specifies which Counter is being

programmed

By contrast initial counts are written into the Coun-

ters not the Control Word Register The A

in-

puts are used to select the Counter to be written

into The format of the initial count is determined by

the Control Word used

Control Word Format

CS e 0

RD e 1

WR e 0

SC1

SC0

RW1

RW0

BCD

Select Counter

SC1

SC0

Select Counter 0

Select Counter 1

Select Counter 2

Read-Back Command

(See Read Operations)

Read Write

RW1 RW0

Counter Latch Command (see Read

Operations)

Read Write least significant byte only

Read Write most significant byte only

Read Write least significant byte first

then most significant byte

NOTE

Don’t care bits (X) should be 0 to insure

compatibility with future Intel products

MODE

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

BCD

Binary Counter 16-bits

Binary Coded Decimal (BCD) Counter

(4 Decades)

Figure 7 Control Word Format

82C54

Write Operations

The programming procedure for the 82C54 is very

flexible Only two conventions need to be remem-

bered

1) For each Counter the Control Word must be

written before the initial count is written

2) The initial count must follow the count format

specified in the Control Word (least significant

byte only most significant byte only or least sig-

nificant byte and then most significant byte)

Since the Control Word Register and the three

Counters have separate addresses (selected by the

inputs) and each Control Word specifies the

Counter it applies to (SC0 SC1 bits) no special in-

struction sequence is required Any programming

sequence that follows the conventions above is ac-

ceptable

A new initial count may be written to a Counter at

any time without affecting the Counter’s pro-

grammed Mode in any way Counting will be affected

as described in the Mode definitions The new count

must follow the programmed count format

If a Counter is programmed to read write two-byte

counts the following precaution applies A program

must not transfer control between writing the first

and second byte to another routine which also writes

into that same Counter Otherwise the Counter will

be loaded with an incorrect count

Control Word

Counter 0

LSB of count

Counter 0

MSB of count

Counter 0

Control Word

Counter 1

LSB of count

Counter 1

MSB of count

Counter 1

Control Word

Counter 2

LSB of count

Counter 2

MSB of count

Counter 2

Control Word

Counter 0

Counter Word

Counter 1

Control Word

Counter 2

LSB of count

Counter 2

LSB of count

Counter 1

LSB of count

Counter 0

MSB of count

Counter 0

MSB of count

Counter 1

MSB of count

Counter 2

Control Word

Counter 2

Control Word

Counter 1

Control Word

Counter 0

LSB of count

Counter 2

MSB of count

Counter 2

LSB of count

Counter 1

MSB of count

Counter 1

LSB of count

Counter 0

MSB of count

Counter 0

Control Word

Counter 1

Control Word

Counter 0

LSB of count

Counter 1

Control Word

Counter 2

LSB of count

Counter 0

MSB of count

Counter 1

LSB of count

Counter 2

MSB of count

Counter 0

MSB of count

Counter 2

NOTE

In all four examples all counters are programmed to read write two-byte counts

These are only four of many possible programming sequences

Figure 8 A Few Possible Programming Sequences

Read Operations

It is often desirable to read the value of a Counter

without disturbing the count in progress This is easi-

ly done in the 82C54

There are three possible methods for reading the

counters

a simple read operation

the Counter

Latch Command and the Read-Back Command

Each is explained below The first method is to per-

form a simple read operation To read the Counter

which is selected with the A1 A0 inputs the CLK

input of the selected Counter must be inhibited by

using either the GATE input or external logic Other-

wise the count may be in the process of changing

when it is read giving an undefined result

82C54

COUNTER LATCH COMMAND

The second method uses the ‘‘Counter Latch Com-

mand’’ Like a Control Word this command is written

to the Control Word Register which is selected

when A

11 Also like a Control Word the

SC0 SC1 bits select one of the three Counters but

two other bits D5 and D4 distinguish this command

from a Control Word

11 CSe0 RDe1 WRe0

SC1

SC0

SC1 SC0 - specify counter to be latched

SC1

SC0

Counter

Read-Back Command

D5 D4 - 00 designates Counter Latch Command

X - don’t care

NOTE

Don’t care bits (X) should be 0 to insure compatibility

with future Intel products

Figure 9 Counter Latching Command Format

The selected Counter’s output latch (OL) latches the

count at the time the Counter Latch Command is

received This count is held in the latch until it is read

by the CPU (or until the Counter is reprogrammed)

The count is then unlatched automatically and the

OL returns to ‘‘following’’ the counting element (CE)

This allows reading the contents of the Counters

‘‘on the fly’’ without affecting counting in progress

Multiple Counter Latch Commands may be used to

latch more than one Counter Each latched Coun-

ter’s OL holds its count until it is read Counter Latch

Commands do not affect the programmed Mode of

the Counter in any way

If a Counter is latched and then some time later

latched again before the count is read the second

Counter Latch Command is ignored The count read

will be the count at the time the first Counter Latch

Command was issued

With either method the count must be read accord-

ing to the programmed format specifically if the

Counter is programmed for two byte counts two

bytes must be read The two bytes do not have to be

read one right after the other read or write or pro-

gramming operations of other Counters may be in-

serted between them

Another feature of the 82C54 is that reads and

writes of the same Counter may be interleaved for

example if the Counter is programmed for two byte

counts the following sequence is valid

1 Read least significant byte

2 Write new least significant byte

3 Read most significant byte

4 Write new most significant byte

If a Counter is programmed to read write two-byte

counts the following precaution applies A program

must not transfer control between reading the first

and second byte to another routine which also reads

from that same Counter Otherwise an incorrect

count will be read

READ-BACK COMMAND

The third method uses the Read-Back command

This command allows the user to check the count

value programmed Mode and current state of the

OUT pin and Null Count flag of the selected coun-

ter(s)

The command is written into the Control Word Reg-

ister and has the format shown in Figure 10 The

command applies to the counters selected by set-

ting their corresponding bits D3 D2 D1 e 1

A0 A1

COUNT STATUS CNT 2 CNT 1 CNT 0

Latch count of selected counter(s)

Latch status of selected counter(s)

Select counter 2

Select counter 1

Select counter 0

Reserved for future expansion must be 0

Figure 10 Read-Back Command Format

The read-back command may be used to latch multi-

ple counter output latches (OL) by setting the

COUNT bit D5e0 and selecting the desired coun-

ter(s) This single command is functionally equiva-

lent to several counter latch commands one for

each counter latched Each counter’s latched count

is held until it is read (or the counter is repro-

grammed) That counter is automatically unlatched

when read but other counters remain latched until

they are read If multiple count read-back commands

are issued to the same counter without reading the

82C54

count all but the first are ignored i e

the count

which will be read is the count at the time the first

read-back command was issued

The read-back command may also be used to latch

status information of selected counter(s) by setting

STATUS bit D4e0 Status must be latched to be

read status of a counter is accessed by a read from

that counter

The counter status format is shown in Figure 11 Bits

D5 through D0 contain the counter’s programmed

Mode exactly as written in the last Mode Control

Word OUTPUT bit D7 contains the current state of

the OUT pin This allows the user to monitor the

counter’s output via software possibly eliminating

some hardware from a system

OUTPUT

NULL

RW1 RW0 M2 M1 M0 BCD

COUNT

Out Pin is 1

Out Pin is 0

Null count

Count available for reading

-D

Counter Programmed Mode (See Figure 7)

Figure 11 Status Byte

NULL COUNT bit D6 indicates when the last count

written to the counter register (CR) has been loaded

into the counting element (CE) The exact time this

happens depends on the Mode of the counter and is

described in the Mode Definitions but until the count

is loaded into the counting element (CE) it can’t be

read from the counter If the count is latched or read

before this time the count value will not reflect the

new count just written The operation of Null Count

is shown in Figure 12

THIS ACTION

CAUSES

A Write to the control

Null count

word register

B Write to the count

Null count

C New count is loaded

Null count

into CE (CR

CE)

Only the counter specified by the control word will

have its null count set to 1 Null count bits of other

counters are unaffected

If the counter is programmed for two-byte counts

(least significant byte then most significant byte) null

count goes to 1 when the second byte is written

Figure 12 Null Count Operation

If multiple status latch operations of the counter(s)

are performed without reading the status all but the

first are ignored i e the status that will be read is

the status of the counter at the time the first status

read-back command was issued

Both count and status of the selected counter(s)

may be latched simultaneously by setting both

COUNT and STATUS bits D5 D4e0 This is func-

tionally the same as issuing two separate read-back

commands at once and the above discussions ap-

ply here also Specifically if multiple count and or

status read-back commands are issued to the same

counter(s) without any intervening reads all but the

first are ignored This is illustrated in Figure 13

If both count and status of a counter are latched the

first read operation of that counter will return latched

status regardless of which was latched first The

next one or two reads (depending on whether the

counter is programmed for one or two type counts)

return latched count Subsequent reads return un-

latched count

Command

Description

Results

Read back count and status of

Count and status latched

Counter 0

for Counter 0

Read back status of Counter 1

Status latched for Counter 1

Read back status of Counters 2 1 Status latched for Counter

2 but not Counter 1

Read back count of Counter 2

Count latched for Counter 2

Read back count and status of

Count latched for Counter 1

Counter 1

but not status

Read back status of Counter 1

Command ignored status

already latched for Counter 1

Figure 13 Read-Back Command Example