background image
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
April 1996
COPYRIGHT
INTEL CORPORATION 1996
Order Number 272322-004
8XC51FX
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS
Commercial Express
87C51FA 83C51FA 80C51FA 87C51FB 83C51FB 87C51FC 83C51FC
See Table 1 for Proliferation Options
Y
High Performance CHMOS
EPROM ROM CPU
Y
12 24 33 MHz Operation
Y
Three 16-Bit Timer Counters
Y
Programmable Counter Array with
High Speed Output
Compare Capture
Pulse Width Modulator
Watchdog Timer Capabilities
Y
Up Down Timer Counter
Y
Three Level Program Lock System
Y
8K 16K 32K On-Chip Program Memory
Y
256 Bytes of On-Chip Data RAM
Y
Improved Quick Pulse Programming
Algorithm
Y
Boolean Processor
Y
32 Programmable I O Lines
Y
7 Interrupt Sources
Y
Four Level Interrupt Priority
Y
Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y
TTL Compatible Logic Levels
Y
64K External Program Memory Space
Y
64K External Data Memory Space
Y
MCS
51 Controller Compatible
Instruction Set
Y
Power Saving Idle and Power Down
Modes
Y
ONCE (On-Circuit Emulation) Mode
Y
Extended Temperature Range Except
for 33 MHz Offering (
b
40 C to
a
85 C)
MEMORY ORGANIZATION
Device
ROM
Version
EPROM
ROMLESS
Version
ROM
Bytes
RAM
EPROM
Bytes
83C51FA
87C51FA
80C51FA
8K
256
83C51FB
87C51FB
80C51FA
16K
256
83C51FC
87C51FC
80C51FA
32K
256
These devices can address up to 64 Kbytes of external program data memory
The Intel 87C51FA 8XC51FB 8XC51FC is a single-chip control oriented microcontroller which is fabricated on
Intel’s reliable CHMOS III-E technology The Intel 83C51FA 80C51FA is fabricated on CHMOS III technology
Being a member of the MCS
51 controller family the 8XC51FA 8XC51FB 8XC51FC uses the same powerful
instruction set has the same architecture and is pin-for-pin compatible with the existing MCS 51 controller
products The 8XC51FA 8XC51FB 8XC51FC is an enhanced version of the 8XC52 8XC54 8XC58 Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation
High Speed I O and up down counting capabilities such as motor control
For the remainder of this document the 8XC51FA 8XC51FB 8XC51FC will be referred to as the 8XC51FX
unless information applies to a specific device
background image
8XC51FX
Table 1 Proliferation Options
Standard
1
-1
-2
-24
-33
80C51FA
X
X
X
X
X
83C51FA
X
X
X
X
X
87C51FA
X
X
X
X
X
83C51FB
X
X
X
X
X
87C51FB
X
X
X
X
X
83C51FC
X
X
X
X
X
87C51FC
X
X
X
X
X
NOTES
1
3 5 MHz to 12 MHz 5V
g
20%
-1
3 5 MHz to 16 MHz 5V
g
20%
-2
0 5 MHz to 12 MHz 5V
g
20%
-24
3 5 MHz to 24 MHz 5V
g
20%
-33
3 5 MHz to 33 MHz 5V
g
10%
272322 – 1
Figure 1 8XC51FX Block Diagram
2
background image
8XC51FX
PROCESS INFORMATION
The 87C51FA 8XC51FB 8XC51FC is manufactured
on P629 0 a CHMOS III-E process Additional pro-
cess and reliability information is available in Intel’s
Components Quality and Reliability Handbook
Or-
der No 210997
PACKAGES
Part
Prefix
Package Type
8XC51FX
P
40-Pin Plastic DIP
D
40-Pin CERDIP
N
44-Pin PLCC
S
44-Pin QFP
272322 – 2
DIP
272322 – 23
PLCC
272322 – 24
Do not connect Reserved Pins
QFP
Figure 2 Pin Connections
3
background image
8XC51FX
PIN DESCRIPTIONS
V
CC
Supply voltage
V
SS
Circuit ground
V
SS1
Secondary ground (not on DIP devices or any
83C51FA 80C51FA device)
Provided to reduce
ground bounce and improve power supply by-pass-
ing
NOTE
This pin is not a substitution for the V
SS
pin (Con-
nection not necessary for proper operation )
Port 0
Port 0 is an 8-bit open drain bidirectional
I O port As an output port each pin can sink several
LS TTL inputs Port 0 pins that have 1’s written to
them float and in that state can be used as high-im-
pedance inputs
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory In this application it uses strong inter-
nal pullups when emitting 1’s and can source and
sink several LS TTL inputs
Port 0 also receives the code bytes during EPROM
programming and outputs the code bytes during
program verification External pullup resistors are re-
quired during program verification
Port 1
Port 1 is an 8-bit bidirectional I O port with
internal pullups The Port 1 output buffers can drive
LS TTL inputs Port 1 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 1
pins that are externally pulled low will source current
(I
IL
on the data sheet) because of the internal pull-
ups
In addition Port 1 serves the functions of the follow-
ing special features of the 8XC51FX
Port Pin
Alternate Function
P1 0
T2 (External Count Input to Timer
Counter 2) Clock Out
P1 1
T2EX (Timer Counter 2 Capture
Reload Trigger and Direction Control)
P1 2
ECI (External Count Input to the PCA)
P1 3
CEX0 (External I O for Compare
Capture Module 0)
P1 4
CEX1 (External I O for Compare
Capture Module 1)
P1 5
CEX2 (External I O for Compare
Capture Module 2)
P1 6
CEX3 (External I O for Compare
Capture Module 3)
P1 7
CEX4 (External I O for Compare
Capture Module 4)
Port 1 receives the low-order address bytes during
EPROM programming and verifying
Port 2
Port 2 is an 8-bit bidirectional I O port with
internal pullups The Port 2 output buffers can drive
LS TTL inputs Port 2 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 2
pins that are externally pulled low will source current
(I
IL
on the data sheet) because of the internal pull-
ups
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX
DPTR) In this application it
uses strong internal pullups when emitting 1’s Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX
Ri) Port 2 emits the contents of
the P2 Special Function Register
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion
Port 3
Port 3 is an 8-bit bidirectional I O port with
internal pullups The Port 3 output buffers can drive
LS TTL inputs Port 3 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally pulled low will source current
(I
IL
on the data sheet) because of the pullups
4
background image
8XC51FX
Port 3 also serves the functions of various special
features of the MCS-51 Family as listed below
Port Pin
Alternate Function
P3 0
RXD (serial input port)
P3 1
TXD (serial output port)
P3 2
INT0 (external interrupt 0)
P3 3
INT1 (external interrupt 1)
P3 4
T0 (Timer 0 external input)
P3 5
T1 (Timer 1 external input)
P3 6
WR (external data memory write strobe)
P3 7
RD (external data memory read strobe)
RST
Reset input A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice The port pins will be driven to their reset condi-
tion when a minimum V
IH1
voltage is applied wheth-
er the oscillator is running or not An internal pull-
down resistor permits a power-on reset with only a
capacitor connected to V
CC
ALE
Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory This pin (ALE PROG) is also the
program pulse input during EPROM programming for
the 87C51FX
In normal operation ALE is emitted at a constant
rate of
the oscillator frequency and may be used
for external timing or clocking purposes Note how-
ever that one ALE pulse is skipped during each ac-
cess to external Data Memory
If desired ALE operation can be disabled by setting
bit 0 of SFR location 8EH With this bit set the pin is
weakly pulled high However the ALE disable fea-
ture will be suspended during a MOVX or MOVC in-
struction idle mode power down mode and ICE
mode The ALE disable feature will be terminated by
reset When the ALE disable feature is suspended or
terminated the ALE pin will no longer be pulled up
weakly Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode
Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin
PSEN
Program Store Enable is the read strobe to
external Program Memory
When the 8XC51FX is executing code from external
Program Memory PSEN is activated twice each ma-
chine cycle except that two PSEN activations are
skipped during each access to external Data Memo-
ry
EA V
PP
External Access enable
EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFH Note however that if either of the
Program Lock bits are programmed EA will be inter-
nally latched on reset
EA should be strapped to V
CC
for internal program
executions
This pin also receives the programming supply volt-
age (V
PP
) during EPROM programming
XTAL1
Input to the inverting oscillator amplifier
XTAL2
Output from the inverting oscillator amplifi-
er
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of a inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ‘‘Oscillators for Microcontrol-
lers ’’
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 floats as
shown in Figure 4 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a
divide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up This is due
to interaction between the amplifier and its feedback
capacitance Once the external signal meets the V
IL
and V
IH
specifications the capacitance will not ex-
ceed 20 pF
5
background image
8XC51FX
272322 – 3
C1 C2 e 30 pF
g
10 pF for Crystals
For Ceramic Resonators contact resonator manufacturer
Figure 3 Oscillator Connections
272322 – 4
Figure 4 External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions
Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs The PCA timer counter can
optionally be left running or paused during Idle
Mode
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the 8XC51FX either hardware reset or external
interrupt can cause an exit from Power Down Reset
redefines all the SFRs but does not change the on-
chip RAM An external interrupt allows both the
SFRs and the on-chip RAM to retain their values
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before V
CC
is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
With an external interrupt INT0 or INT1 must be en-
abled and configured as level-sensitive Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down
DESIGN CONSIDERATION

Ambient light is known to affect the internal RAM
contents during operation If the 87C51FX appli-
cation requires the part to be run under ambient
lighting an opaque label should be placed over
the window to exclude light

When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
Table 2 Status of the External Pins during Idle and Power Down
Mode
Program
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Memory
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I and Application Note AP-252 (Embedded Applications Handbook) ‘‘Designing with the 80C51BH ’’
6
background image
8XC51FX
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing
and
debugging
of
systems
using
the
8XC51FX without the 8XC51FX having to be re-
moved from the circuit The ONCE Mode is invoked
by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 8XC51FX is in this mode an emulator
or test CPU can be used to drive the circuit Normal
operation is restored when a normal reset is applied
8XC51FX EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS-51 family
of microcontrollers These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards
The EXPRESS program includes the commercial
standard temperature range with burn-in and an ex-
tended temperature range with or without burn-in
With the commercial standard temperature range
operational characteristics are guaranteed over the
temperature range of 0 C to 70 C With the extend-
ed temperature range option operational character-
istics are guaranteed over the range of b40 C to
a
85 C
The optional burn-in is dynamic for a minimum time
of 168 hours at 125 C with V
CC
e
6 9V
g
0 25V
following guidelines in MlL-STD-883 Method 1015
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number The
prefixes are listed in Table 3
For the extended temperature range option this
data sheet specifies the parameters which deviate
from their commercial temperature range limits
NOTE
Intel offers Express Temperature specifica-
tions for all 8XC51FX speed options except
for 33 MHz
Table 3 Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
D
Cerdip
Commercial
No
N
PLCC
Commercial
No
P
Plastic
Commercial
No
S
QFP
Commercial
No
LD
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
LP
Plastic
Extended
Yes
LS
QFP
Extended
Yes
TD
Cerdip
Extended
No
TN
PLCC
Extended
No
TP
Plastic
Extended
No
TS
QFP
Extended
No
NOTE
Contact distributor or local sales office to match EXPRESS prefix with proper device
EXAMPLES
P87C51FC indicates 87C51FC in a plastic package and specified for commercial temperature range without burn-in
LD87C51FC indicates 87C51FC in a cerdip package and specified for extended temperature range with burn-in
7
background image
8XC51FX
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias b40 C to a85 C
Storage Temperature
b
65 C to a150 C
Voltage on EA V
PP
Pin to V
SS
0V to a13 0V
Voltage on Any Other Pin to V
SS
b
0 5V to a6 5V
I
OL
per I O Pin
15 mA
Power Dissipation
1 5W
(based on PACKAGE heat transfer limitations not
device power consumption)
NOTICE This data sheet contains preliminary infor-
mation on new products in production It is valid for
the devices indicated in the revision history The
specifications are subject to change without notice
WARNING Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage
These are stress ratings only Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex-
tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability
OPERATING CONDITIONS
Symbol
Description
Min
Max
Units
T
A
Ambient Temperature Under Bias
Commercial
0
a
70
C
Express
b
40
a
85
V
CC
Supply Voltage
8XC51FX-33
4 5
5 5
V
All Others
4 0
6 0
f
OSC
Oscillator Frequency
8XC51FX
3 5
12
8XC51FX-1
3 5
16
MHz
8XC51FX-2
0 5
12
8XC51FX-24
3 5
24
8XC51FX-33
3 5
33
DC CHARACTERISTICS
(Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
(Note 4)
V
IL
Input Low Voltage
b
0 5
0 2 V
CC
b
0 1
V
V
IL1
Input Low Voltage EA
0
0 2 V
CC
b
0 3
V
V
IH
Input High Voltage
0 2 V
CC
a
0 9
V
CC
a
0 5
V
(Except XTAL1 RST)
V
IH1
Input High Voltage
0 7 V
CC
V
CC
a
0 5
V
(XTAL1 RST)
V
OL
Output Low Voltage (Note 5)
0 3
I
OL
e
100 mA
(Ports 1 2 and 3)
0 45
V
I
OL
e
1 6 mA (Note 1)
1 0
I
OL
e
3 5 mA
V
OL1
Output Low Voltage (Note 5)
0 3
I
OL
e
200 mA
(Port 0 ALE PROG PSEN)
0 45
V
I
OL
e
3 2 mA (Note 1)
1 0
I
OL
e
7 0 mA
V
OH
Output High Voltage
V
CC
b
0 3
I
OH
e b
10 mA
(Ports 1 2 and 3
V
CC
b
0 7
V
I
OH
e b
30 mA (Note 2)
ALE PROG and PSEN)
V
CC
b
1 5
I
OH
e b
60 mA
V
OH1
Output High Voltage
V
CC
b
0 3
I
OH
e b
200 mA
(Port 0 in External Bus Mode)
V
CC
b
0 7
V
I
OH
e b
3 2 mA (Note 2)
V
CC
b
1 5
I
OH
e b
7 0 mA
83C51FA 80C51FA (Express)
I
OH
e b
6 0 mA
I
IL
Logical 0 Input Current
b
50
m
A
V
IN
e
0 45V
(Ports 1 2 and 3)
8
background image
8XC51FX
DC CHARACTERISTICS
(Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated (Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
(Note 4)
I
LI
Input leakage Current (Port 0)
g
10
m
A
V
IN
e
V
IL
or V
IH
I
TL
Logical 1 to 0 Transition Current
V
IN
e
2V
(Ports 1 2 and 3)
Express
b
750
m
A
Commercial
b
650
RRST
RST Pulldown Resistor
40
225
KX
CIO
Pin Capacitance
10
pF
1MHz 25 C
I
CC
Power Supply Current
(Note 3)
Active Mode
At 12 MHz (Figure 5)
15
30
mA
At 16 MHz
20
38
mA
At 24 MHz
28
56
mA
At 33 MHz
35
56
mA
Idle Mode
At 12 MHz (Figure 5)
5
7 5
mA
At 16 MHz
6
9 5
mA
At 24 MHz
7
13 5
mA
At 33 MHz
7
15
mA
Power Down Mode
5
75
m
A
NOTES
1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the V
OL
s of ALE and
Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0 In applications where capacitance loading exceeds 100 pF the noise pulses on these signals may
exceed 0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic
2 Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the 0 9 V
CC
specification when the
address lines are stabilizing
3 See Figures 6 – 9 for test conditions Minimum V
CC
for power down is 2V
4 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and 5V
5 Under steady state (non-transient) conditions I
OL
must be externally limited as follows
Maximum I
OL
per port pin
10 mA
Maximum I
OL
per 8-bit port -
Port 0
26 mA
Ports 1 2 and 3
15 mA
Maximum total I
OL
for all output pins
71 mA
If I
OL
exceeds the test condition V
OL
may exceed the related specification Pins are not guaranteed to sink current greater
than the listed test conditions
272322 – 5
Note
I
CC
max at 33 MHz is at 5V
g
10% V
CC
while I
CC
max at 24 MHz and below is at 5V
g
20% V
CC
Figure 5 8XC51FA FB FC I
CC
vs Frequency
9
background image
8XC51FX
272322 – 6
All other pins disconnected
TCLCH e TCHCL e 5 ns
Figure 6 I
CC
Test Condition Active Mode
272322 – 7
All other pins disconnected
TCLCH e TCHCL e 5 ns
Figure 7 I
CC
Test Condition Idle Mode
272322 – 8
All other pins disconnected
Figure 8 I
CC
Test Condition Power Down Mode
V
CC
e
2 0V to 6 0V
272322 – 19
Figure 9 Clock Signal Waveform for I
CC
Tests in Active and Idle Modes TCLCH e TCHCL e 5 ns
10
background image
8XC51FX
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters The first char-
acter is always a ‘T’ (stands for time) The other
characters depending on their positions stand for
the name of a signal or the logical status of that
signal The following is a list of all the characters and
what they stand for
A Address
C Clock
D Input Data
H Logic level HIGH
I Instruction (program memory contents)
L Logic level LOW or ALE
P PSEN
Q Output Data
R RD signal
T Time
V Valid
W WR signal
X No longer a valid logic level
Z Float
For example
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
AC CHARACTERISTICS
(Over Operating Conditions Load Capacitance for Port 0 ALE PROG and
PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated In this table 8XC51FX refers to
8XC51FX 8XC51FX-1 and 8XC51FX-2
Symbol
Parameter
Oscillator
Units
12 MHz
24 MHz
33 MHz
Variable
Min Max Min Max Min Max
Min
Max
1 TCLCL Oscillator Frequency
MHz
8XC51FX
3 5
12
8XC51FX-1
3 5
16
8XC51FX-2