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October 1995

INTEL CORPORATION 1995

Order Number 272335-003

87C51 80C51BH 80C31BH

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Commercial Express

87C51 80C51BH 80C51BHP 80C31BH

See Table 1 for Proliferation Options

High Performance CHMOS EPROM

24 MHz Operation

Improved Quick-Pulse Programming

Algorithm

3-Level Program Memory Lock

Boolean Processor

128-Byte Data RAM

32 Programmable I O Lines

Two 16-Bit Timer Counters

Extended Temperature Range

(

40 C to

85 C)

5 Interrupt Sources

Programmable Serial Port

TTL- and CMOS-Compatible Logic

Levels

64K External Program Memory Space

64K External Data Memory Space

ONCE Mode Facilitates System Testing

Power Control Modes

Idle

Power Down

MEMORY ORGANIZATION

PROGRAM MEMORY Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH) In

addition the device can address up to 64K of program memory external to the chip

DATA MEMORY This microcontroller has a 128 x 8 on-chip RAM In addition it can address up to 64 Kbytes of

external data memory

The Intel 87C51 80C51BH 80C31BH is a single-chip control-oriented microcontroller which is fabricated on

Intel’s reliable CHMOS III-E technology

Being a member of the MCS

51 controller family

the

87C51 80C51BH 80C31BH uses the same powerful instruction set has the same architecture and is pin-for-

pin compatible with the existing MCS 51 controller family of products

The 80C51BHP is identical to the 80C51BH When ordering the 80C51BHP customers must submit the 64

byte encryption table together with the ROM code Lock bit 1 will be set to enable the internal ROM code

protection and at the same time allows code verification

The extremely low operating power along with the two reduced power modes Idle and Power Down make

this part very suitable for low power applications The Idle mode freezes the CPU while allowing the RAM

timer counters serial port and interrupt system to continue functioning The Power Down mode saves the

RAM contents but freezes the oscillator causing all other chip functions to be inoperative

For the remainder of this document the 87C51 80C51BH and 80C31BH will be referred to as the 87C51 BH

unless information applies to a specific device

87C51 80C51BH 80C31BH

PIN DESCRIPTION

Supply voltage during normal Idle and Power

Down operations

Circuit ground

Port 0

Port 0 is an 8-bit open drain bidirectional I O

port As an output port each pin can sink several LS

TTL inputs Port 0 pins that have 1’s written to them

float and in that state can be used as high-imped-

ance inputs

Port 0 is also the multiplexed low-order address and

data bus during accesses to external memory In this

application it uses strong internal pullups when emit-

ting 1’s

Port 0 also receives the code bytes during EPROM

programming and outputs the code bytes during

program verification External pullups are required

during program verification

Port 1

Port 1 is an 8-bit bidirectional I O port with

internal pullups The Port 1 output buffers can drive

LS TTL inputs Port 1 pins that have 1’s written to

them are pulled high by the internal pullups and in

that state can be used as inputs As inputs Port 1

pins that are externally pulled low will source current

on the data sheet) because of the internal pull-

ups

Port 1 also receives the low-order address bytes

during EPROM programming and program verifica-

tion

Port 2

Port 2 is an 8-bit bidirectional I O port with

internal pullups Port 2 pins that have 1’s written to

them are pulled high by the internal pullups and in

that state can be used as inputs As inputs Port 2

pins that are externally pulled low will source current

on the data sheet) because of the internal pull-

ups

Port 2 emits the high-order address byte during

fetches from external Program memory and during

accesses to external Data Memory that use 16-bit

address (MOVX

DPTR) In this application it uses

strong internal pullups when emitting 1’s

During accesses to external Data Memory that use

8-bit addresses (MOVX

Ri) Port 2 emits the con-

tents of the P2 Special Function Register

Port 2 also receives some control signals and the

high-order address bits during EPROM programming

and program verification

Port 3

Port 3 is an 8-bit bidirectional I O port with

internal pullups The Port 3 output buffers can drive

LS TTL inputs Port 3 pins that have 1’s written to

them are pulled high by the internal pullups and in

that state can be used as inputs As inputs Port 3

pins that are externally pulled low will source current

on the data sheet) because of the pullups

Port 3 also serves the functions of various special

features of the MCS-51 Family as listed below

Name

Alternate Function

P3 0

RXD

Serial input line

P3 1

TXD

Serial output line

P3 2

INT0

External Interrupt 0

P3 3

INT1

External Interrupt 1

P3 4

Timer 0 external input

P3 5

Timer 1 external input

P3 6

External Data Memory Write strobe

P3 7

External Data Memory Read strobe

Port 3 also receives some control signals for

EPROM programming and program verification

RST

Reset input A high on this pin for two machine

cycles while the oscillator is running resets the de-

vice The port pins will be driven to their reset condi-

tion when a minimum V

IH1

voltage is applied wheth-

er the oscillator is running or not An internal pull-

down resistor permits a power-on reset with only a

capacitor connected to V

ALE PROG

Address Latch Enable output signal for

latching the low byte of the address during accesses

to external memory This pin is also the program

pulse input (PROG) during EPROM programming for

the 87C51

If desired ALE operation can be disabled by setting

bit 0 of SFR location 8EH With this bit set the pin is

weakly pulled high However the ALE disable fea-

ture will be suspended during a MOVX or MOVC in-

struction idle mode power down mode and ICE

mode The ALE disable feature will be terminated by

reset When the ALE disable feature is suspended or

terminated the ALE pin will no longer be pulled up

weakly Setting the ALE-disable bit has no effect if

the microcontroller is in external execution mode

87C51 80C51BH 80C31BH

In normal operation ALE is emitted at a constant

rate of 1 6 the oscillator frequency and may be

used for external timing or clocking purposes Note

however that one ALE pulse is skipped during each

access to external Data Memory

PSEN

Program Store Enable is the Read strobe to

External Program Memory When the 87C51 BH is

executing from Internal Program Memory PSEN is

inactive (high) When the device is executing code

from External Program Memory PSEN is activated

twice each machine cycle except that two PSEN

activations are skipped during each access to Exter-

nal Data Memory

EA V

External Access enable

EA must be

strapped to V

in order to enable the 87C51 BH to

fetch code from External Program Memory locations

starting at 0000H up to FFFFH Note however that

if either of the Lock Bits is programmed the logic

level at EA is internally latched during reset

EA must be strapped to V

for internal program

execution

This pin also receives the programming supply volt-

age (V

) during EPROM programming

XTAL1

Input to the inverting oscillator amplifier

XTAL2

Output from the inverting oscillator amplifi-

272335 – 5

Figure 3 Using the On-Chip Oscillator

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output respec-

tively of an inverting amplifier which can be config-

ured for use as an on-chip oscillator as shown in

Figure 3

To drive the device from an external clock source

XTAL1 should be driven while XTAL2 is left uncon-

nected as shown in Figure 4 There are no require-

ments on the duty cycle of the external clock signal

since the input to the internal clocking circuitry is

through a divide-by-two flip-flop but minimum and

maximum high and low times specified on the data

sheet must be observed

An external oscillator may encounter as much as a

100 pF load at XTAL1 when it starts up This is due

to interaction between the amplifier and its feedback

capacitance Once the external signal meets the V

and V

specifications the capacitance will not ex-

ceed 20 pF

272335 – 6

Figure 4 External Clock Drive

87C51 80C51BH 80C31BH

IDLE MODE

In Idle Mode the CPU puts itself to sleep while all

the on-chip peripherals remain active The mode is

invoked by software The content of the on-chip

RAM and all the Special Functions Registers remain

unchanged during this mode The Idle Mode can be

terminated by any enabled interrupt or by a hard-

ware reset

It should be noted that when Idle is terminated by a

hardware reset the device normally resumes pro-

gram execution from where it left off up to two ma-

chine cycles before the internal reset algorithm

takes control On-chip hardware inhibits access to

internal RAM in this event but access to the port

pins is not inhibited To eliminate the possibility of an

unexpected write to a port pin when Idle is terminat-

ed by reset the instruction following the one that

invokes Idle should not be one that writes to a port

pin or to external memory

POWER DOWN MODE

To save even more power a Power Down mode can

be invoked by software In this mode the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is transmitted

On the 87C51 BH either a hardware reset or an ex-

ternal interrupt can cause an exit from Power Down

Reset redefines all the SFR’s but does not change

the on-chip RAM An external interrupt allows both

the SFRs and on-chip RAM to retain their values

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before V

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms)

With an external interrupt INT0 and INT1 must be

enabled and configured as level-sensitive Holding

the pin low restarts the oscillator but bringing the pin

back high completes the exit Once the interrupt is

serviced the next instruction to be executed after

RET1 will be the one following the instruction that

put the device into Power Down

DESIGN CONSIDERATIONS

Exposure to light when the device is in operation

may cause logic errors For this reason it is sug-

gested that an opaque label be placed over the

window when the die is exposed to ambient light

The 87C51 BH now have some additional fea-

tures The features are asynchronous port reset

4 interrupt priority levels power off flag ALE dis-

able serial port automatic address recognition

serial port framing error detection 64-byte en-

cryption array and 3 program lock bits These

features cannot be used with the older versions

of 80C51BH 80C31BH The newer version of

80C51BH 80C31BH will have change identifier

‘‘A’’ appended to the lot number

Table 2 Status of the External Pins during Idle and Power Down

Mode

Program

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

Power Down

External

Float

Data

87C51 80C51BH 80C31BH

ONCE MODE

The ONCE (‘‘On-Circuit Emulation’’) mode facilitates

testing

and

debugging

systems

using

the

87C51 BH without the 87C51 BH having to be re-

moved from the circuit The ONCE mode is invoked

1 Pull ALE low while the device is in reset and

PSEN is high

2 Hold ALE low as RST is deactivated

While the device is in ONCE mode the Port 0 pins

float and the other port pins and ALE and PSEN are

weakly pulled high The oscillator circuit remains ac-

tive While the 87C51 BH is in this mode an emula-

tor or test CPU can be used to drive the circuit Nor-

mal operation is restored when a normal reset is ap-

plied

87C51 BH EXPRESS

The Intel EXPRESS system offers enhancements to

the operational specifications of the MCS-51 family

of microcontrollers These EXPRESS products are

designed to meet the needs of those applications

whose operating requirements exceed commercial

temperature

The EXPRESS program includes the commercial

standard temperature range with burn-in and an ex-

tended temperature range with or without burn-in

With the commercial standard temperature range

operational characteristics are guaranteed over the

temperature range of 0 C to 70 C With the extend-

ed temperature range option operational character-

istics are guaranteed over the range of b40 C to

85 C

The optional burn-in is dynamic for a minimum time

of 160 hours at 125 C with V

6 9V

0 25V

following guidelines in MIL-STD-883 Method 1015

Package types and EXPRESS versions are identified

by a one- or two-letter prefix to the part number The

prefixes are listed in Table 3

For the extended temperature range option this

data sheet specifies the parameters which deviate

from their commercial temperature range limits

Table 3 Prefix Identification

Prefix

Package

Temperature

Burn-in

Type

Range

Plastic

Commercial

Cerdip

Commercial

PLCC

Commercial

QFP

Commercial

Plastic

Extended

Cerdip

Extended

PLCC

Extended

QFP

Extended

Plastic

Extended

Yes

Cerdip

Extended

Yes

PLCC

Extended

Yes

NOTE

Contact distributor or local sales office to match EXPRESS

prefix to proper device

Examples

P87C51 indicates 87C51 in a plastic package and

specified for commercial temperature range without

burn-in

LD87C51 indicates 87C51 in a cerdip package and

specified for extended temperature range with burn-

87C51 80C51BH 80C31BH

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias b40 C to a85 C

Storage Temperature

65 C to a150 C

Voltage on EA V

Pin to V

0V to a13 0V

Voltage on Any Other Pin to V

0 5V to a6 5V

Maximum I

per I O Pin

15 mA

Power Dissipation

1 5W

(Based on package heat transfer limitations not de-

vice power consumption )

NOTICE This data sheet contains preliminary infor-

mation on new products in production It is valid for

the devices indicated in the revision history The

specifications are subject to change without notice

WARNING Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage

These are stress ratings only Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability

OPERATING CONDITIONS

Symbol

Description

Min

Max

Unit

Ambient Temperature Under Bias

Commercial

Express

Supply Voltage

4 5

5 5

OSC

Oscillator Frequency

MHz

87C51 BH

3 5

87C51-1 BH-1

3 5

87C51-2 BH-2

0 5

87C51-24 BH-24

3 5

DC CHARACTERISTICS

(Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Min

Typ(1)

Max

Unit

Test Conditions

Input Low Voltage

Commercial

0 5

0 2 V

0 1

Express

0 5

0 2 V

0 15

IL1

Input Low Voltage EA

Commercial

0 2 V

0 3

Express

0 5

0 2 V

0 35

Input High Voltage

(Except XTAL1 RST)

Commercial

0 2 V

0 9

0 5

Express

0 2 V

0 5

IH1

Input High Voltage

(XTAL1 RST)

Commercial

0 7 V

0 5

Express

0 7 V

0 1

0 5

Output Low Voltage

(6)

0 3

100 mA

(2)

(Ports 1 2 3)

0 45

1 6 mA

(2)

1 0

3 5 mA

(2)

87C51 80C51BH 80C31BH

DC CHARACTERISTICS

(Over Operating Conditions) (Continued)

Symbol

Parameter

Min

Typ(1)

Max

Unit

Test Conditions

OL1

Output Low Voltage

(6)

0 3

200 mA

(2)

(Port 0 ALE PSEN)

0 45

3 2 mA

(2)

1 0

7 0 mA

(2)

Output High Voltage

0 3

e b

10 mA

(3)

(Ports 1 2 3 ALE PSEN)

0 7

e b

30 mA

(3)

1 5

e b

60 mA

(3)

OH1

Output High Voltage

0 3

e b

200 mA

(3)

(Port 0 in External Bus Mode)

0 7

e b

3 2 mA

(3)

1 5

e b

7 0 mA

(3)

Logical 0 Input Current

0 45V

(Ports 1 2 3)

Commercial

Express

Input Leakage Current

0 45

(Port 0)

Logical 1-to-0 Transition Current

(Ports 1 2 3)

Commercial

650

Express

750

RRST

RST Pulldown Resistor

225

Pin Capacitance

1 MHz 25 C

Power Supply Current

(Note 4)

Active Mode

12 MHz (Figure 5)

11 5

16 MHz

24 MHz

Idle Mode

12 MHz (Figure 5)

3 5

7 5

16 MHz

9 5

24 MHz

13 5

Power Down Mode

87C51 80C51BH 80C31BH

NOTES

1 ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed The

values listed are at room temp 5V

2 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the V

s of ALE and

Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed

0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic

3 Capacitive loading on Ports 0 and 2 may cause the V

on ALE and PSEN to momentarily fall below the 0 9V

specifi-

cation when the address bits are stabilizing

4 See Figures 6 through 8 for I

test conditions Minimum V

for Power Down is 2V

5 Under steady state (non-transient) conditions I

must be externally limited as follows

Maximum I

per port pin

10 mA

Maximum I

per 8-bit port

Port 0

26 mA

Ports 1 2 and 3

15 mA

Maximum total I

for all output pins

71 mA

If I

exceeds the test condition V

may exceed the related specification

Pins are not guaranteed to sink greater than the listed test conditions

272335 – 26

Figure 5 87C51 BH I

vs Frequency

87C51 80C51BH 80C31BH

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters The first char-

acter is always a ‘T’ (stands for time) The other

characters depending on their positions stand for

the name of a signal or the logical status of that

signal The following is a list of all the characters and

what they stand for

A Address

C Clock

D Input data

H Logic level HIGH

I Instruction (program memory contents)

L Logic level LOW or ALE

P PSEN

Q Output data

R RD signal

T Time

V Valid

W WR signal

X No longer a valid logic level

Z Float

For example

TAVLL e Time from Address Valid to ALE Low

TLLPL e Time from ALE Low to PSEN Low

AC CHARACTERISTICS

(Over Operating Conditions Load Capacitance for Port 0 ALE and

PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF)

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated In this table 87C51 BH refers to

87C51 BH 87C51-1 BH-1 and 87C51-2 BH-2

Symbol

Parameter

Oscillator

Units

12 MHz

24 MHz

Variable

Min

Max

Min

Max

Min

Max

1 TCLCL

Oscillator Frequency

87C51 BH

3 5

MHz

87C51-1 BH-1

3 5

MHz

87C51-2 BH-2

0 5

MHz

87C51-24 BH-24

3 5

MHz

TLHLL

ALE Pulse Width

127

2TCLCLb40

TAVLL

Address Valid to ALE Low

87C51 BH

TCLCLb40

87C51-24 BH-24

TCLCLb30

TLLAX

Address Hold After ALE Low

TCLCLb30

TLLIV

ALE Low to Valid Instr In

87C51 BH

234

4TCLCLb100

87C51-24 BH-24

4TCLCLb75

TLLPL

ALE Low to PSEN Low

TCLCLb30

TPLPH

PSEN Pulse Width