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March 1996

INTEL CORPORATION 1996

Order Number 272336-004

8XC52 54 58

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Commercial Express

87C52 80C52 80C32 87C54 80C54 87C58 80C58

See Table 1 for Proliferation Options

High Performance CHMOS EPROM

ROM CPU

12 24 33 MHz Operations

Three 16-Bit Timer Counters

Programmable Clock Out

Up Down Timer Counter

Three Level Program Lock System

8K 16K 32K On-Chip Program Memory

256 Bytes of On-Chip Data RAM

Improved Quick Pulse Programming

Algorithm

Boolean Processor

32 Programmable I O Lines

6 Interrupt Sources

Programmable Serial Channel with

Framing Error Detection

Automatic Address Recognition

TTL and CMOS Compatible Logic

Levels

64K External Program Memory Space

64K External Data Memory Space

MCS

51 Microcontroller Compatible

Instruction Set

Power Saving Idle and Power Down

Modes

ONCE (On-Circuit Emulation) Mode

Four-Level Interrupt Priority

Extended Temperature Range Except

for 33 MHz Offering (

40 C to

85 C)

MEMORY ORGANIZATION

ROM

EPROM

ROMless

ROM EPROM

RAM

Device

Version

Bytes

80C52

87C52

80C32

256

80C54

87C54

80C32

16K

256

80C58

87C58

80C32

32K

256

These devices can address up to 64 Kbytes of external program data memory

The Intel 8XC52 8XC54 8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s

reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC52 8XC54

8XC58 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with

the existing MCS 51 family of products The 8XC52 8XC54 8XC58 is an enhanced version of the

87C51 80C51BH 80C31BH The added features make it an even more powerful microcontroller for applica-

tions that require clock output and up down counting capabilities such as motor control It also has a more

versatile serial channel that facilitates multi-processor communications

Throughout this document 8XC5X will refer to the 8XC52 80C32 8XC54 and 8XC58 unless information

applies to a specific device

8XC52 54 58

PIN DESCRIPTIONS

Supply voltage

Circuit ground

SS1

Secondary ground (not on DIP) Provided to

reduce ground bounce and improve power supply

by-passing

NOTE

This pin is not a substitute for the V

pin (pin 22)

(Connection not necessary for proper operation )

Port 0

Port 0 is an 8-bit open drain bidirectional

I O port As an output port each pin can sink several

LS TTL inputs Port 0 pins that have 1’s written to

them float and in that state can be used as high-im-

pedance inputs

Port 0 is also the multiplexed low-order address and

data bus during accesses to external Program and

Data Memory In this application it uses strong inter-

nal pullups when emitting 1’s and can source and

sink several LS TTL inputs

Port 0 also receives the code bytes during EPROM

programming and outputs the code bytes during

program verification External pullup resistors are re-

quired during program verification

Port 1

Port 1 is an 8-bit bidirectional I O port with

internal pullups The Port 1 output buffers can drive

LS TTL inputs Port 1 pins that have 1’s written to

them are pulled high by the internal pullups and in

that state can be used as inputs As inputs Port 1

pins that are externally pulled low will source current

on the data sheet) because of the internal pull-

ups

In addition Port 1 serves the functions of the follow-

ing special features of the 8XC5X

Port Pin

Alternate Function

P1 0

T2 (External Count Input to Timer

Counter 2) Clock-Out

P1 1

T2EX (Timer Counter 2 Capture

Reload Trigger and Direction Control)

Port 1 receives the low-order address bytes during

EPROM programming and verifying

Port 2

Port 2 is an 8-bit bidirectional I O port with

internal pullups The Port 2 output buffers can drive

LS TTL inputs Port 2 pins that have 1’s written to

them are pulled high by the internal pullups and in

that state can be used as inputs As inputs Port 2

pins that are externally pulled low will source current

on the data sheet) because of the internal pull-

ups

Port 2 emits the high-order address byte during

fetches from external Program Memory and during

accesses to external Data Memory that use 16-bit

addresses (MOVX

DPTR) In this application it

uses strong internal pullups when emitting 1’s Dur-

ing accesses to external Data Memory that use 8-bit

addresses (MOVX

Ri) Port 2 emits the contents of

the P2 Special Function Register

Some Port 2 pins receive the high-order address bits

during EPROM programming and program verifica-

tion

Port 3

Port 3 is an 8-bit bidirectional I O port with

internal pullups The Port 3 output buffers can drive

LS TTL inputs Port 3 pins that have 1’s written to

them are pulled high by the internal pullups and in

that state can be used as inputs As inputs Port 3

pins that are externally pulled low will source current

on the data sheet) because of the pullups

Port 3 also serves the functions of various special

features of the 8051 Family as listed below

Port Pin

Alternate Function

P3 0

RXD (serial input port)

P3 1

TXD (serial output port)

P3 2

INT0 (external interrupt 0)

P3 3

INT1 (external interrupt 1)

P3 4

T0 (Timer 0 external input)

P3 5

T1 (Timer 1 external input)

P3 6

WR (external data memory write strobe)

P3 7

RD (external data memory read strobe)

RST

Reset input A high on this pin for two machine

cycles while the oscillator is running resets the de-

vice The port pins will be driven to their reset condi-

tion when a minimum V

IHI

voltage is applied whether

the oscillator is running or not An internal pulldown

resistor permits a power-on reset with only a capaci-

tor connected to V

ALE

Address Latch Enable output pulse for latching

the low byte of the address during accesses to ex-

ternal memory This pin (ALE PROG) is also the

program pulse input during EPROM programming for

the 87C5X

In normal operation ALE is emitted at a constant

rate of

the oscillator frequency and may be used

for external timing or clocking purposes Note how-

ever that one ALE pulse is skipped during each ac-

cess to external Data Memory

8XC52 54 58

If desired ALE operation can be disabled by setting

bit 0 of SFR location 8EH With this bit set the pin is

weakly pulled high However the ALE disable fea-

ture will be suspended during a MOVX or MOVC in-

struction idle mode power down mode and ICE

mode The ALE disable feature will be terminated by

reset When the ALE disable feature is suspended or

terminated the ALE pin will no longer be pulled up

weakly Setting the ALE-disable bit has no affect if

the microcontroller is in external execution mode

Throughout the remainder of this data sheet ALE

will refer to the signal coming out of the ALE PROG

pin and the pin will be referred to as the ALE PROG

PSEN

Program Store Enable is the read strobe to

external Program Memory

When the 8XC5X is executing code from external

Program Memory PSEN is activated twice each

machine cycle except that two PSEN activations

are skipped during each access to external Data

Memory

EA V

External Access enable

EA must be

strapped to VSS in order to enable the device to

fetch code from external Program Memory locations

0000H to 0FFFFH Note however that if any of the

Lock bits are programmed EA will be internally

latched on reset

EA should be strapped to V

for internal program

executions

This pin also receives the programming supply volt-

age (V

) during EPROM programming

XTAL1

Input to the inverting oscillator amplifier

XTAL2

Output from the inverting oscillator amplifi-

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output respec-

tively of a inverting amplifier which can be config-

ured for use as an on-chip oscillator as shown in

Figure 3 Either a quartz crystal or ceramic resonator

may be used More detailed information concerning

the use of the on-chip oscillator is available in Appli-

cation Note AP-155 ‘‘Oscillators for Microcontrol-

lers’’ Order No 230659

272336 – 5

C1 C2

30 pF

10 pF for Crystals

For Ceramic Resonators contact resonator manufac-

turer

Figure 3 Oscillator Connections

To drive the device from an external clock source

XTAL1 should be driven while XTAL2 floats as

shown in Figure 4 There are no requirements on the

duty cycle of the external clock signal since the in-

put to the internal clocking circuitry is through a di-

vide-by-two flip-flop but minimum and maximum

high and low times specified on the data sheet must

be observed

An external oscillator may encounter as much as a

100 pF load at XTAL1 when it starts up This is due

to interaction between the amplifier and its feedback

capacitance Once the external signal meets the V

and V

specifications the capacitance will not ex-

ceed 20 pF

272336 – 6

Figure 4 External Clock Drive Configuration

IDLE MODE

The user’s software can invoke the Idle Mode When

the microcontroller is in this mode power consump-

tion is reduced The Special Function Registers and

the onboard RAM retain their values during Idle but

the processor stops executing instructions

Idle

Mode will be exited if the chip is reset or if an en-

abled interrupt occurs

8XC52 54 58

Table 2 Status of the External Pins during Idle and Power Down

Mode

Program

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

Power Down

External

Float

Data

POWER DOWN MODE

To save even more power a Power Down mode can

be invoked by software In this mode the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated

On the 8XC5X either a hardware reset or an external

interrupt can cause an exit from Power Down Reset

redefines all the SFRs but does not change the on-

chip RAM An external interrupt allows both the

SFRs and on-chip RAM to retain their values

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before V

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms)

With an external interrupt INT0 and INT1 must be

enabled and configured as level-sensitive Holding

the pin low restarts the oscillator but bringing the pin

back high completes the exit Once the interrupt is

serviced the next instruction to be executed after

RETI will be the one following the instruction that put

the device into Power Down

DESIGN CONSIDERATION

The window on the D87C5X must be covered by

an opaque label Otherwise the DC and AC char-

acteristics may not be met and the device may

be functionally impaired

When the idle mode is terminated by a hardware

reset the device normally resumes program exe-

cution from where it left off up to two machine

cycles before the internal reset algorithm takes

control On-chip hardware inhibits access to inter-

nal RAM in this event but access to the port pins

is not inhibited To eliminate the possibility of an

unexpected write when Idle is terminated by re-

set the instruction following the one that invokes

Idle should not be one that writes to a port pin or

to external memory

ONCE MODE

The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates

testing and debugging of systems using the 8XC5X

without the 8XC5X having to be removed from the

circuit The ONCE Mode is invoked by

1) Pull ALE low while the device is in reset and

PSEN is high

2) Hold ALE low as RST is deactivated

While the device is in ONCE Mode the Port 0 pins

float and the other port pins and ALE and PSEN are

weakly pulled high The oscillator circuit remains ac-

tive While the 8XC5X is in this mode an emulator or

test CPU can be used to drive the circuit Normal

operation is restored when a normal reset is applied

NOTE

For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors

Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No

270648) ‘‘Designing with the 80C51BH ’’

8XC52 54 58

8XC5X EXPRESS

The Intel EXPRESS system offers enhancements to

the operational specifications of the MCS 51 family

of microcontrollers These EXPRESS products are

designed to meet the needs of those applications

whose operating requirements exceed commercial

standards

The EXPRESS program includes the commercial

standard temperature range with burn-in and an ex-

tended temperature range with or without burn-in

With the commercial standard temperature range

operational characteristics are guaranteed over the

temperature range of 0 C to a70 C With the ex-

tended temperature range option operational char-

acteristics are guaranteed over the range of b40 C

to a85 C

The optional burn-in is dynamic for a minimum time

of 168 hours at 125 C with V

6 9V

0 25V

following guidelines in MIL-STD-883 Method 1015

Package types and EXPRESS versions are identified

by a one- or two-letter prefix to the part number The

prefixes are listed in Table 3

For the extended temperature range option this

data sheet specifies the parameters which deviate

from their commercial temperature range limits

NOTE

Intel offers Express Temperature specifica-

tions for all 8XC5X speed options except for

33 MHz

Table 3 Prefix Identification

Prefix

Package

Temperature

Burn-In

Type

Range

Plastic

Commercial

Cerdip

Commercial

PLCC

Commercial

QFP

Commercial

Plastic

Extended

Cerdip

Extended

PLCC

Extended

QFP

Extended

Plastic

Extended

Yes

Cerdip

Extended

Yes

PLCC

Extended

Yes

QFP

Extended

Yes

NOTE

Contact distributor or local sales office to match EXPRESS prefix with proper device

EXAMPLES

P80C52 indicates 80C52 in a plastic package and specified for commercial temperature range without burn-in TD80C52

indicates 80C52 in a Cerdip package and specified for extended temperature range without burn-in

8XC52 54 58

ABSOLUTE MAXIMUM RATINGS

Ambient Temperature Under Bias b40 C to a85 C

Storage Temperature

65 C to a150 C

Voltage on EA V

Pin to V

0V to a13 0V

Voltage on Any Other Pin to V

0 5V to a6 5V

Per I O Pin

15 mA

Power Dissipation

1 5W

(based on PACKAGE heat transfer limitations not

device power consumption)

NOTICE This data sheet contains preliminary infor-

mation on new products in production The specifica-

tions are subject to change without notice Verify with

your local Intel Sales office that you have the latest

data sheet before finalizing a design

WARNING Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage

These are stress ratings only Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability

OPERATING CONDITIONS

Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

Commercial

Express

Supply Voltage

4 0

6 0

8XC5X-33

4 5

5 5

OSC

Oscillator Frequency

8XC5X

3 5

MHz

8XC5X-1

3 5

MHz

8XC5X-2

0 5

MHz

8XC5X-24

3 5

MHz

8XC5X-33

3 5

MHz

DC CHARACTERISTICS

(Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

(Note 4)

Input Low Voltage

0 5

0 2 V

0 1

IL1

Input Low Voltage EA

0 2 V

0 3

Input High Voltage

0 2 V

0 9

0 5

(Except XTAL1 RST)

IH1

Input High Voltage

0 7 V

0 5

(XTAL1 RST)

Output Low Voltage (Note 5)

0 3

100 mA (Note 1)

(Ports 1 2 and 3)

0 45

1 6 mA (Note 1)

1 0

3 5 mA (Note 1)

OL1

Output Low Voltage (Note 5)

0 3

200 mA (Note 1)

(Port 0 ALE PSEN)

0 45

3 2 mA (Note 1)

1 0

7 0 mA (Note 1)

Output High Voltage

0 3

e b

10 mA

(Ports 1 2 and 3 ALE PSEN)

0 7

e b

30 mA

1 5

e b

60 mA

8XC52 54 58

DC CHARACTERISTICS

(Over Operating Conditions) (Continued)

All parameter values apply to all devices unless otherwise indicated

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

(Note 4)

OH1

Output High Voltage

0 3

e b

200 mA

(Port 0 in External Bus Mode)

0 7

e b

3 2 mA

1 5

e b

7 0 mA

Logical 0 Input Current

(Ports 1 2 and 3)

0 45V

Input leakage Current (Port 0)

or V

Logical 1 to 0 Transition Current

(Ports 1 2 and 3)

Commercial

650

Express

750

RRST

RST Pulldown Resistor

225

CIO

Pin Capacitance

1 MHz 25 C

Power Supply Current

(Note 3)

Active Mode

at 12 MHz (Figure 5)

at 16 MHz

at 24 MHz

at 33 MHz (8XC5X-33)

Idle Mode

at 12 MHz (Figure 5)

7 5

at 16 MHz

9 5

at 24 MHz

13 5

at 33 MHz (8XC5X-33)

Power Down Mode

8XC5X-33

NOTES

1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 0 4V to be superimposed on the V

s of ALE and

Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed

0 8V It may be desirable to qualify ALE or other signals with a Schmitt Triggers or CMOS-level input logic

2 Capacitive loading on Ports 0 and 2 cause the V

on ALE and PSEN to drop below the 0 9 V

specification when the

address lines are stabilizing

3 See Figures 6 – 9 for test conditions Minimum V

for Power Down is 2V

4 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature

and 5V

5 Under steady state (non-transient) conditions I

must be externally limited as follows

Maximum I

per port pin

10mA

Maximum I

per 8-bit port

Port 0

26 mA

Ports 1 2 and 3

15 mA

Maximum total I

for all output pins

71 mA

If I

exceeds the test condition V

may exceed the related specification Pins are not guaranteed to sink current greater

than the listed test conditions

8XC52 54 58

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters The first char-

acter is always a ‘T’ (stands for time) The other

characters depending on their positions stand for

the name of a signal or the logical status of that

signal The following is a list of all the characters and

what they stand for

A Address

C Clock

D Input Data

H Logic level HIGH

I Instruction (program memory contents)

L Logic level LOW or ALE

P PSEN

Q Output Data

R RD signal

T Time

V Valid

W WR signal

X No longer a valid logic level

Z Float

For example

TAVLL e Time from Address Valid to ALE Low

TLLPL e Time from ALE Low to PSEN Low

AC CHARACTERISTICS

(Over Operating Conditions Load Capacitance for Port 0 ALE PROG and

PSEN e 100 pF Load Capacitance for All Other Outputs e 80 pF)

EXTERNAL MEMORY CHARACTERISTICS

All parameter values apply to all devices unless otherwise indicated In this table 8XC5X refers to 8XC5X

8XC5X-1 and 8XC5X-2

Symbol

Parameter

Oscillator

Units

12 MHz

24 MHz

33 MHz

Variable

Min Max Min Max Min Max

Min

Max

1 TCLCL Oscillator Frequency

8XC5X

3 5

MHz

8XC5X-1

3 5

MHz

8XC5X-2

0 5

MHz

8XC5X-24

3 5

MHz

8XC5X-33

3 5

MHz