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October 1995
COPYRIGHT
INTEL CORPORATION 1995
Order Number 272433-004
80C186EB 80C188EB AND 80L186EB 80L188EB
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
X
Full Static Operation
X
True CMOS Inputs and Outputs
Y
Integrated Feature Set
Low-Power Static CPU Core
Two Independent UARTs each with
an Integral Baud Rate Generator
Two 8-Bit Multiplexed I O Ports
Programmable Interrupt Controller
Three Programmable 16-Bit
Timer Counters
Clock Generator
Ten Programmable Chip Selects with
Integral Wait-State Generator
Memory Refresh Control Unit
System Level Testing Support (ONCE
Mode)
Y
Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I O
Y
Speed Versions Available (5V)
25 MHz (80C186EB25 80C188EB25)
20 MHz (80C186EB20 80C188EB20)
13 MHz (80C186EB13 80C188EB13)
Y
Available in Extended Temperature
Range (
b
40 C to
a
85 C)
Y
Speed Versions Available (3V)
16 MHz (80L186EB16 80L188EB16)
13 MHz (80L186EB13 80L188EB13)
8 MHz (80L186EB8 80L188EB8)
Y
Low-Power Operating Modes
Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Powerdown Mode Freezes All
Internal Clocks
Y
Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y
Available In
80-Pin Quad Flat Pack (QFP)
84-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor It has features that are new
to the 80C186 family and include a STATIC CPU core an enhanced Chip Select decode unit two independent
Serial Channels I O ports and the capability of Idle or Powerdown low power modes
272433 – 1
1
80C186EB 80C188EB and 80L186EB 80L188EB
16-Bit High-Integration Embedded Processors
CONTENTS
PAGE
INTRODUCTION
4
CORE ARCHITECTURE
4
Bus Interface Unit
4
Clock Generator
4
80C186EC PERIPHERAL
ARCHITECTURE
5
Interrupt Control Unit
5
Timer Counter Unit
5
Serial Communications Unit
7
Chip-Select Unit
7
I O Port Unit
7
Refresh Control Unit
7
Power Management Unit
7
80C187 Interface (80C186EB Only)
7
ONCE Test Mode
7
PACKAGE INFORMATION
8
Prefix Identification
8
Pin Descriptions
8
80C186EB PINOUT
14
PACKAGE THERMAL
SPECIFICATIONS
22
ELECTRICAL SPECIFICATIONS
23
Absolute Maximum Ratings
23
CONTENTS
PAGE
Recommended Connections
23
DC SPECIFICATIONS
24
I
CC
versus Frequency and Voltage
27
PDTMR Pin Delay Calculation
27
AC SPECIFICATIONS
28
AC Characteristics
80C186EB25
28
AC Characteristics
80C186EB20 13
30
AC Characteristics
80L186EB16
32
Relative Timings
36
Serial Port Mode 0 Timings
37
AC TEST CONDITIONS
38
AC TIMING WAVEFORMS
38
DERATING CURVES
41
RESET
42
BUS CYCLE WAVEFORMS
45
EXECUTION TIMINGS
52
INSTRUCTION SET SUMMARY
53
ERRATA
59
REVISION HISTORY
59
2
2
80C186EB 80C188EB 80L186EB 80L188EB
272433 – 2
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
Figure 1 80C186EB 80C188EB Block Diagram
3
3
80C186EB 80C188EB 80L186EB 80L188EB
INTRODUCTION
Unless specifically noted
all references to the
80C186EB apply to the 80C188EB 80L186EB and
80L188EB References to pins that differ between
the 80C186EB 80L186EB and the 80C188EB
80L188EB are given in parentheses The ‘‘L’’ in the
part number denotes low voltage operation Physi-
cally and functionally the ‘‘C’’ and ‘‘L’’ devices are
identical
The 80C186EB is the first product in a new genera-
tion of low-power high-integration microprocessors
It enhances the existing 186 family by offering new
features and new operating modes The 80C186EB
is object code compatible with the 80C186XL
80C188XL microprocessors
The 80L186EB is the 3V version of the 80C186EB
The 80L186EB is functionally identical to the
80C186EB
embedded
processor
Current
80C186EB users can easily upgrade their designs to
use the 80L186EB and benefit from the reduced
power consumption inherent in 3V operation
The feature set of the 80C186EB meets the needs
of low power space critical applications Low-Power
applications benefit from the static design of the
CPU core and the integrated peripherals as well as
low voltage operation Minimum current consump-
tion is achieved by providing a Powerdown mode
that halts operation of the device and freezes the
clock circuits Peripheral design enhancements en-
sure that non-initialized peripherals consume little
current
Space critical applications benefit from the inte-
gration of commonly used system peripherals Two
serial channels are provided for services such as
diagnostics inter-processor communication modem
interface terminal display interface and many oth-
ers A flexible chip select unit simplifies memory and
peripheral interfacing The interrupt unit provides
sources for up to 129 external interrupts and will pri-
oritize these interrupts with those generated from
the on-chip peripherals Three general purpose tim-
er counters and sixteen multiplexed I O port pins
round out the feature set of the 80C186EB
Figure 1 shows a block diagram of the 80C186EB
80C188EB The Execution Unit (EU) is an enhanced
8086 CPU core that includes dedicated hardware to
speed up effective address calculations enhance
execution speed for multiple-bit shift and rotate in-
structions and for multiply and divide instructions
string move instructions that operate at full bus
bandwidth ten new instruction and fully static oper-
ation The Bus Interface Unit (BIU) is the same as
that found on the original 186 family products ex-
cept the queue status mode has been deleted and
buffer interface control has been changed to ease
system design timings An independent internal bus
is used to allow communication between the BIU
and internal peripherals
CORE ARCHITECTURE
Bus Interface Unit
The 80C186EB core incorporates a bus controller
that generates local bus control signals In addition
it employs a HOLD HLDA protocol to share the local
bus with other bus masters
The bus controller is responsible for generating 20
bits of address read and write strobes bus cycle
status information and data (for write operations) in-
formation It is also responsible for reading data off
the local bus during a read operation A READY in-
put pin is provided to extend a bus cycle beyond the
minimum four states (clocks)
The local bus controller also generates two control
signals (DEN and DT R) when interfacing to exter-
nal transceiver chips (Both DEN and DT R are
available on the PLCC devices only DEN is avail-
able on the QFP and SQFP devices ) This capability
allows the addition of transceivers for simple buffer-
ing of the multiplexed address data bus
Clock Generator
The processor provides an on-chip clock generator
for both internal and external clock generation The
clock generator features a crystal oscillator a divide-
by-two counter
and two low-power operating
modes
The oscillator circuit is designed to be used with ei-
ther a parallel resonant fundamental or third-over-
tone mode crystal network Alternatively the oscilla-
tor circuit may be driven from an external clock
source Figure 2 shows the various operating modes
of the oscillator circuit
The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter This counter is
used to drive all internal phase clocks and the exter-
nal CLKOUT signal CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys-
tem components All AC timings are referenced to
CLKOUT
4
4
80C186EB 80C188EB 80L186EB 80L188EB
272433 – 3
(A) Crystal Connection
NOTE
The L
1
C
1
network is only required when using a third-
overtone crystal
272433 – 4
(B) Clock Connection
Figure 2 Clock Configurations
The following parameters are recommended when
choosing a crystal
Temperature Range
Application Specific
ESR (Equivalent Series Resistance)
40X max
C0 (Shunt Capacitance of Crystal)
7 0 pF max
C
L
(Load Capacitance)
20 pF
g
2 pF
Drive Level
1 mW max
80C186EB PERIPHERAL
ARCHITECTURE
The 80C186EB has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact yet powerful system The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e g the
interrupt control unit supports interrupt requests
from the timer counters or serial channels)
The list of integrated peripherals includes
7-Input Interrupt Control Unit
3-Channel Timer Counter Unit
2-Channel Serial Communications Unit
10-Output Chip-Select Unit
I O Port Unit
Refresh Control Unit
Power Management Unit
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB) The PCB
can be located in either memory or I O space on
any 256 Byte address boundary
Figure 3 provides a list of the registers associated
with the PCB The Register Bit Summary at the end
of this specification individually lists all of the regis-
ters and identifies each of their programming attri-
butes
Interrupt Control Unit
The 80C186EB can receive interrupts from a num-
ber of sources both internal and external The inter-
rupt control unit serves to merge these requests on
a priority basis for individual service by the CPU
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU
Internal interrupt sources include the Timers and Se-
rial channel 0 External interrupt sources come from
the five input pins INT4 0 The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU Although the Timer and Serial channel
each have only one request input to the ICU sepa-
rate vector types are generated to service individual
interrupts within the Timer and Serial channel units
Timer Counter Unit
The 80C186EB Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
control or clocking A third timer is not connected to
any external pins and can only be clocked internally
However it can be used to clock the other two timer
channels The TCU can be used to count external
events time external events generate non-repeti-
tive waveforms generate timed interrupts etc
5
5
80C186EB 80C188EB 80L186EB 80L188EB
PCB
Function
Offset
00H
Reserved
02H
End Of Interrupt
04H
Poll
06H
Poll Status
08H
Interrupt Mask
0AH
Priority Mask
0CH
In-Service
0EH
Interrupt Request
10H
Interrupt Status
12H
Timer Control
14H
Serial Control
16H
INT4 Control
18H
INT0 Control
1AH
INT1 Control
1CH
INT2 Control
1EH
INT3 Control
20H
Reserved
22H
Reserved
24H
Reserved
26H
Reserved
28H
Reserved
2AH
Reserved
2CH
Reserved
2EH
Reserved
30H
Timer0 Count
32H
Timer0 Compare A
34H
Timer0 Compare B
36H
Timer0 Control
38H
Timer1 Count
3AH Timer1 Compare A
3CH Timer1 Compare B
3EH
Timer1 Control
PCB
Function
Offset
40H
Timer2 Count
42H
Timer2 Compare
44H
Reserved
46H
Timer2 Control
48H
Reserved
4AH
Reserved
4CH
Reserved
4EH
Reserved
50H
Port 1 Direction
52H
Port 1 Pin
54H
Port 1 Control
56H
Port 1 Latch
58H
Port 2 Direction
5AH
Port 2 Pin
5CH
Port 2 Control
5EH
Port 2 Latch
60H
Serial0 Baud
62H
Serial0 Count
64H
Serial0 Control
66H
Serial0 Status
68H
Serial0 RBUF
6AH
Serial0 TBUF
6CH
Reserved
6EH
Reserved
70H
Serial1 Baud
72H
Serial1 Count
74H
Serial1 Control
76H
Serial1 Status
78H
Serial1 RBUF
7AH
Serial1 TBUF
7CH
Reserved
7EH
Reserved
PCB
Function
Offset
80H
GCS0 Start
82H
GCS0 Stop
84H
GCS1 Start
86H
GCS1 Stop
88H
GCS2 Start
8AH
GCS2 Stop
8CH
GCS3 Start
8EH
GCS3 Stop
90H
GCS4 Start
92H
GCS4 Stop
94H
GCS5 Start
96H
GCS5 Stop
98H
GCS6 Start
9AH
GCS6 Stop
9CH
GCS7 Start
9EH
GCS7 Stop
A0H
LCS Start
A2H
LCS Stop
A4H
UCS Start
A6H
UCS Stop
A8H
Relocation
AAH
Reserved
ACH
Reserved
AEH
Reserved
B0H
Refresh Base
B2H
Refresh Time
B4H
Refresh Control
B6H
Reserved
B8H
Power Control
BAH
Reserved
BCH
Step ID
BEH
Reserved
PCB
Function
Offset
C0H
Reserved
C2H
Reserved
C4H
Reserved
C6H
Reserved
C8H
Reserved
CAH
Reserved
CCH
Reserved
CEH
Reserved
D0H
Reserved
D2H
Reserved
D4H
Reserved
D6H
Reserved
D8H
Reserved
DAH
Reserved
DCH
Reserved
DEH
Reserved
E0H
Reserved
E2H
Reserved
E4H
Reserved
E6H
Reserved
E8H
Reserved
EAH
Reserved
ECH
Reserved
EEH
Reserved
F0H
Reserved
F2H
Reserved
F4H
Reserved
F6H
Reserved
F8H
Reserved
FAH
Reserved
FCH
Reserved
FEH
Reserved
Figure 3 Peripheral Control Block Registers
6
6
80C186EB 80C188EB 80L186EB 80L188EB
Serial Communications Unit
The Serial Control Unit (SCU) of the 80C186EB con-
tains two independent channels Each channel is
identical in operation except that only channel 0 is
supported by the integrated interrupt controller
(channel 1 has an external interrupt pin) Each
channel has its own baud rate generator that is in-
dependent of the Timer Counter Unit and can be
internally or externally clocked at up to one half the
80C186EB operating frequency
Independent baud rate generators are provided for
each of the serial channels For the asynchronous
modes the generator supplies an 8x baud clock to
both the receive and transmit register logic A 1x
baud clock is provided in the synchronous mode
Chip-Select Unit
The 80C186EB Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip-
selects to access both memories and peripherals In
addition each chip-select can be programmed to
automatically insert additional clocks (wait-states)
into the current bus cycle and automatically termi-
nate a bus cycle independent of the condition of the
READY input pin
I O Port Unit
The I O Port Unit (IPU) on the 80C186EB supports
two 8-bit channels of input output or input output
operation Port 1 is multiplexed with the chip select
pins and is output only Most of Port 2 is multiplexed
with the serial channel pins Port 2 pins are limited to
either an output or input function depending on the
operation of the serial pin it is multiplexed with
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed A 9-bit
counter controls the number of clocks between re-
fresh requests
A 12-bit address generator is maintained by the RCU
and is presented on the A12 1 address lines during
the refresh bus cycle Address bits A19 13 are pro-
grammable to allow the refresh address block to be
located on any 8 Kbyte boundary
Power Management Unit
The 80C186EB Power Management Unit (PMU) is
provided to control the power consumption of the
device The PMU provides three power modes Ac-
tive Idle and Powerdown
Active
Mode
indicates
that
all
units
on
the
80C186EB are functional and the device consumes
maximum power (depending on the level of periph-
eral operation) Idle Mode freezes the clocks of the
Execution and Bus units at a logic zero state (all
peripherals continue to operate normally)
The Powerdown mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator
All internal registers hold their values provided V
CC
is maintained Current consumption is reduced to
just transistor junction leakage
80C187 Interface (80C186EB Only)
The 80C186EB (PLCC package only) supports the
direct connection of the 80C187 Numerics Coproc-
essor
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system the 80C186EB has a test
mode available which forces all output and input
output pins to be placed in the high-impedance
state ONCE stands for ‘‘ON Circuit Emulation’’ The
ONCE mode is selected by forcing the A19 ONCE
pin LOW (0) during a processor reset (this pin is
weakly held to a HIGH (1) level) while RESIN is ac-
tive
7
7
80C186EB 80C188EB 80L186EB 80L188EB
PACKAGE INFORMATION
This section describes the pins pinouts and thermal
characteristics for the 80C186EB in the Plastic
Leaded Chip Carrier (PLCC) package Shrink Quad
Flat Pack (SQFP) and Quad Flat Pack (QFP) pack-
age For complete package specifications and infor-
mation see the Intel Packaging Outlines and Dimen-
sions Guide (Order Number 231369)
Prefix Identification
With the extended temperature range operational
characteristics are guaranteed over the temperature
range corresponding to b40 C to a85 C ambient
Package types are identified by a two-letter prefix to
the part number The prefixes are listed in Table 1
Table 1 Prefix Identification
Prefix Note
Package
Temperature
Type
Type
TN
PLCC
Extended
TS
QFP (EIAJ) Extended
SB
1
SQFP
Extended Commercial
N
1
PLCC
Commercial
S
1
QFP (EIAJ) Commercial
NOTE
1 The 5V 25 MHz and 3V 16 MHz versions are only avail-
able in commercial temperature range corresponding to
0 C to
a
70 C ambient
Pin Descriptions
Each pin or logical set of pins is described in Table
3 There are three columns for each entry in the Pin
Description Table
The Pin Name column contains a mnemonic that
describes the pin function Negation of the signal
name (for example RESIN) denotes a signal that is
active low
The Pin Type column contains two kinds of informa-
tion The first symbol indicates whether a pin is pow-
er (P) ground (G) input only (I) output only (O) or
input output (I O)
Some pins have multiplexed
functions (for example A19 S6) Additional symbols
indicate additional characteristics for each pin Table
2 lists all the possible symbols for this column
The Input Type column indicates the type of input
(Asynchronous or Synchronous)
Asynchronous pins require that setup and hold times
be met only in order to guarantee
recognition
at a
particular clock edge Synchronous pins require that
setup and hold times be met to guarantee proper
operation
For example missing the setup or hold
time for the SRDY pin (a synchronous input) will re-
sult in a system failure or lockup Input pins may also
be edge- or level-sensitive The possible character-
istics for input pins are S(E) S(L) A(E) and A(L)
The Output States column indicates the output
state as a function of the device operating mode
Output states are dependent upon the current activi-
ty of the processor There are four operational
states that are different from regular operation bus
hold reset Idle Mode and Powerdown Mode Ap-
propriate characteristics for these states are also in-
dicated in this column with the legend for all possi-
ble characteristics in Table 2
The Pin Description column contains a text de-
scription of each pin
As an example consider AD15 0 I O signifies the
pins are bidirectional S(L) signifies that the input
function is synchronous and level-sensitive H(Z)
signifies that as outputs the pins are high-imped-
ance upon acknowledgement of bus hold R(Z) sig-
nifies that the pins float during reset P(X) signifies
that the pins retain their states during Powerdown
Mode
8
8
80C186EB 80C188EB 80L186EB 80L188EB
Table 2 Pin Description Nomenclature
Symbol
Description
P
Power Pin (Apply aV
CC
Voltage)
G
Ground (Connect to V
SS
)
I
Input Only Pin
O
Output Only Pin
I O
Input Output Pin
S(E)
Synchronous Edge Sensitive
S(L)
Synchronous Level Sensitive
A(E)
Asynchronous Edge Sensitive
A(L)
Asynchronous Level Sensitive
H(1)
Output Driven to V
CC
during Bus Hold
H(0)
Output Driven to V
SS
during Bus Hold
H(Z)
Output Floats during Bus Hold
H(Q)
Output Remains Active during Bus Hold
H(X)
Output Retains Current State during Bus Hold
R(WH)
Output Weakly Held at V
CC
during Reset
R(1)
Output Driven to V
CC
during Reset
R(0)
Output Driven to V
SS
during Reset
R(Z)
Output Floats during Reset
R(Q)
Output Remains Active during Reset
R(X)
Output Retains Current State during Reset
I(1)
Output Driven to V
CC
during Idle Mode
I(0)
Output Driven to V
SS
during Idle Mode
I(Z)
Output Floats during Idle Mode
I(Q)
Output Remains Active during Idle Mode
I(X)
Output Retains Current State during Idle Mode
P(1)
Output Driven to V
CC
during Powerdown Mode
P(0)
Output Driven to V
SS
during Powerdown Mode
P(Z)
Output Floats during Powerdown Mode
P(Q)
Output Remains Active during Powerdown Mode
P(X)
Output Retains Current State during Powerdown Mode
9
9
80C186EB 80C188EB 80L186EB 80L188EB
Table 3 Pin Descriptions
Pin
Pin
Input
Output
Description
Name
Type
Type
States
V
CC
P
POWER
connections consist of four pins which must be
shorted externally to a V
CC
board plane
V
SS
G
GROUND
connections consist of six pins which must be
shorted externally to a V
SS
board plane
CLKIN
I
A(E)
CLocK INput
is an input for an external clock An external
oscillator operating at two times the required processor
operating frequency can be connected to CLKIN For crystal
operation CLKIN (along with OSCOUT) are the crystal
connections to an internal Pierce oscillator
OSCOUT
O
H(Q)
OSCillator OUTput
is only used when using a crystal to
generate the external clock OSCOUT (along with CLKIN)
R(Q)
are the crystal connections to an internal Pierce oscillator
P(Q)
This pin is not to be used as 2X clock output for non-crystal
applications (i e this pin is N C for non-crystal applications)
OSCOUT does not float in ONCE mode
CLKOUT
O
H(Q)
CLocK OUTput
provides a timing reference for inputs and
outputs of the processor and is one-half the input clock
R(Q)
(CLKIN) frequency CLKOUT has a 50% duty cycle and
P(Q)
transistions every falling edge of CLKIN
RESIN
I
A(L)
RESet IN
causes the processor to immediately terminate
any bus cycle in progress and assume an initialized state All
pins will be driven to a known state and RESOUT will also
be driven active The rising edge (low-to-high) transition
synchronizes CLKOUT with CLKIN before the processor
begins fetching opcodes at memory location 0FFFF0H
RESOUT
O
H(0)
RESet OUTput
that indicates the processor is currently in
the reset state RESOUT will remain active as long as RESIN
R(1)
remains active
P(0)
PDTMR
I O
A(L)
H(WH)
Power-Down TiMeR
pin (normally connected to an external
capacitor) that determines the amount of time the processor
R(Z)
waits after an exit from power down before resuming normal
P(1)
operation The duration of time required will depend on the
startup characteristics of the crystal oscillator
NMI
I
A(E)
Non-Maskable Interrupt
input causes a TYPE-2 interrupt to
be serviced by the CPU NMI is latched internally
TEST BUSY
I
A(E)
TEST
is used during the execution of the WAIT instruction to
suspend CPU operation until the pin is sampled active
(TEST)
(LOW) TEST is alternately known as BUSY when interfacing
with an 80C187 numerics coprocessor (80C186EB only)
AD15 0
I O
S(L)
H(Z)
These pins provide a multiplexed Address and Data bus
During the address phase of the bus cycle address bits 0
(AD7 0)
R(Z)
through 15 (0 through 7 on the 80C188EB) are presented on
P(X)
the bus and can be latched using ALE 8- or 16-bit data
information is transferred during the data phase of the bus
cycle
NOTE
Pin names in parentheses apply to the 80C188EB 80L188EB
10
10
80C186EB 80C188EB 80L186EB 80L188EB
Table 3 Pin Descriptions
(Continued)
Pin
Pin
Input
Output
Description
Name
Type
Type
States
A18 16
I O
A(L)
H(Z)
These pins provide multiplexed Address during the address
phase of the bus cycle Address bits 16 through 19 are presented
A19 ONCE
R(WH)
on these pins and can be latched using ALE These pins are
(A15 A8)
P(X)
driven to a logic 0 during the data phase of the bus cycle On the
(A18 16)
80C188EB A15 – A8 provide valid address information for the
(A19 ONCE)
entire bus cycle During a processor reset (RESIN active) A19
ONCE is used to enable ONCE mode A18 16 must not be driven
low during reset or improper operation may result
S2 0
O
H(Z)
Bus cycle Status are encoded on these pins to provide bus
transaction information S2 0 are encoded as follows
R(Z)
P(1)
S2
S1
S0
Bus Cycle Initiated
0
0
0
Interrupt Acknowledge
0
0
1
Read I O
0
1
0
Write I O
0
1
1
Processor HALT
1
0
0
Queue Instruction Fetch
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive (no bus activity)
ALE
O
H(0)
Address Latch Enable
output is used to strobe address
information into a transparent type latch during the address phase
R(0)
of the bus cycle
P(0)
BHE
O
H(Z)
Byte High Enable
output to indicate that the bus cycle in progress
is transferring data over the upper half of the data bus BHE and
(RFSH)
R(Z)
A0 have the f