80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any

patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information

contained herein supersedes previously published specifications on these devices from Intel.

September 1995

Order Number: 272504-004

PRELIMINARY

80960JA/JF

EMBEDDED 32-BIT MICROPROCESSOR

Figure 1. 80960JA/JF Microprocessors

Pin/Code Compatible with all 80960Jx

Processors

High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

— User/Supervisor Protection Model

Two-Way Set Associative Instruction Cache

— 80960JA - 2 Kbyte

— 80960JF - 4 Kbyte

— Programmable Cache Locking

Mechanism

Direct Mapped Data Cache

— 80960JA - 1 Kbyte

— 80960JF - 2 Kbyte

— Write Through Operation

On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority

Interrupts

On-Chip Data RAM

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

High Bandwidth Burst Bus

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

New Instructions

— Conditional Add, Subtract and Select

— Processor Management

High-Speed Interrupt Controller

— 31 Programmable Priorities

— Eight Maskable Pins plus NMI

— Up to 240 Vectors in Expanded Mode

Two On-Chip Timers

— Independent 32-Bit Counting

— Clock Prescaling by 1, 2, 4 or 8

— lnternal Interrupt Sources

Halt Mode for Low Power

IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

Packages

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack (PQFP)

PIN 1

132

i960

© 19xx

A80960Jx

NG80960Jx

XXXXXXXXA2

PRELIMINARY

80960JA/JF

EMBEDDED 32-BIT MICROPROCESSOR

1.0 PURPOSE ..................................................................................................................................................1

2.0 80960JA/JF OVERVIEW ............................................................................................................................1

2.1 80960 Processor Core ........................................................................................................................2

2.2 Burst Bus ............................................................................................................................................2

2.3 Timer Unit ...........................................................................................................................................3

2.4 Priority Interrupt Controller .................................................................................................................3

2.5 Instruction Set Summary ....................................................................................................................3

2.6 Faults and Debugging .........................................................................................................................3

2.7 Low Power Operation .........................................................................................................................4

2.8 Test Features ......................................................................................................................................4

2.9 Memory-Mapped Control Registers ....................................................................................................4

2.10 Data Types and Memory Addressing Modes ....................................................................................4

3.0 PACKAGE INFORMATION ........................................................................................................................6

3.1 Pin Descriptions .................................................................................................................................. 6

3.1.1 Functional Pin Definitions ........................................................................................................6

3.1.2 80960Jx 132-Lead PGA Pinout .............................................................................................13

3.1.3 80960Jx PQFP Pinout ...........................................................................................................17

3.2 Package Thermal Specifications ......................................................................................................20

4.0 ELECTRICAL SPECIFICATIONS ............................................................................................................22

4.1 Absolute Maximum Ratings ..............................................................................................................22

4.2 Operating Conditions ........................................................................................................................22

4.3 Connection Recommendations .........................................................................................................22

4.4 DC Specifications .............................................................................................................................23

4.5 AC Specifications ..............................................................................................................................25

4.5.1 AC Test Conditions and Derating Curves ...............................................................................32

4.5.2 AC Timing Waveforms ............................................................................................................33

5.0 BUS FUNCTIONAL WAVEFORMS .........................................................................................................41

6.0 DEVICE IDENTIFICATION .......................................................................................................................55

7.0 REVISION HISTORY ...............................................................................................................................55

iii

PRELIMINARY

80960JA/JF

FIGURES

Figure 1.

80960JA/JF Microprocessors ....................................................................................................0

Figure 2.

80960JA/JF Block Diagram ........................................................................................................2

Figure 3.

132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13

Figure 4.

132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14

Figure 5.

132-Lead PQFP - Top View ..................................................................................................... 17

Figure 6.

AC Test Load ............................................................................................................................ 32

Figure 7.

Output Delay or Hold vs. Load Capacitance ............................................................................ 32

Figure 8.

Rise and Fall Time Derating ..................................................................................................... 33

Figure 9.

CLKIN Waveform ..................................................................................................................... 33

Figure 10.

Output Delay Waveform for T

OV1

............................................................................................. 34

Figure 11.

Output Float Waveform for T

................................................................................................ 34

Figure 12.

Input Setup and Hold Waveform for T

IS1

and T

IH1

................................................................... 35

Figure 13.

Input Setup and Hold Waveform for T

IS2

and T

IH2

................................................................... 35

Figure 14.

Input Setup and Hold Waveform for T

IS3

and T

IH3

................................................................... 36

Figure 15.

Input Setup and Hold Waveform for T

IS4

and T

IH4

................................................................... 36

Figure 16.

Relative Timings Waveform for T

LXL

and T

LXA

........................................................................ 37

Figure 17.

DT/R and DEN Timings Waveform .......................................................................................... 37

Figure 18.

TCK Waveform ......................................................................................................................... 38

Figure 19.

Input Setup and Hold Waveforms for T

BSIS1

and T

BSIH1

.......................................................... 38

Figure 20.

Output Delay and Output Float Waveform for T

BSOV1

and T

BSOF1

.......................................... 39

Figure 21.

Output Delay and Output Float Waveform for T

BSOV2

and T

BSOF2

.......................................... 39

Figure 22.

Input Setup and Hold Waveform for T

BSIS2

and T

BSIH2

........................................................... 40

Figure 23.

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 41

Figure 24.

Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 42

Figure 25.

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 43

Figure 26.

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 44

Figure 27.

Burst Read and Write Transactions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus ................................................................................... 45

Figure 28.

Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian

Figure 29.

HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 47

Figure 30.

Cold Reset Waveform .............................................................................................................. 48

Figure 31.

Warm Reset Waveform ............................................................................................................ 49

Figure 32.

Entering the ONCE State ......................................................................................................... 50

Figure 33.

Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 53

Figure 34.

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 54

PRELIMINARY

80960JA/JF

TABLES

Table 1.

80960Jx Instruction Set .............................................................................................................5

Table 2.

Pin Description Nomenclature ...................................................................................................6

Table 3.

Pin Description — External Bus Signals ...................................................................................7

Table 4.

Pin Description — Processor Control Signals, Test Signals and Power .................................. 10

Table 5.

Pin Description — Interrupt Unit Signals ................................................................................. 12

Table 6.

132-Lead PGA Pinout — In Signal Order ................................................................................ 15

Table 7.

132-Lead PGA Pinout — In Pin Order .................................................................................... 16

Table 8.

132-Lead PQFP Pinout — In Signal Order ............................................................................. 18

Table 9.

132-Lead PQFP Pinout — In Pin Order .................................................................................. 19

Table 10.

132-Lead PGA Package Thermal Characteristics ................................................................... 20

Table 11.

132-Lead PQFP Package Thermal Characteristics ................................................................ 21

Table 12.

80960JA/JF Operating Conditions .......................................................................................... 22

Table 13.

80960JA/JF DC Characteristics .............................................................................................. 23

Table 14.

80960JA/JF I

Characteristics .............................................................................................. 23

Table 15.

80960JA/JF AC Characteristics (33 MHz) ............................................................................... 25

Table 16.

Note Definitions for Table 15, 80960JA/JF AC Characteristics (33 MHz) ............................... 27

Table 17.

80960JA/JF AC Characteristics (25 MHz) ............................................................................... 27

Table 18.

80960JA/JF AC Characteristics (16 MHz) ............................................................................... 29

Table 19.

Natural Boundaries for Load and Store Accesses .................................................................. 51

Table 20.

Summary of Byte Load and Store Accesses ........................................................................... 51

Table 21.

Summary of Short Word Load and Store Accesses ................................................................ 51

Table 22.

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ............................................... 52

Table 23.

80960JA/JF Die and Stepping Reference ............................................................................... 55

Table 24.

Data Sheet Version -003 to -004 Revision History .................................................................. 55

Table 25.

Data Sheet Version -002 to -003 Revision History .................................................................. 56

Table 26.

Data Sheet Version -001 to -002 Revision History .................................................................. 57

Table 27.

Data Sheet Version -002 to -003 Revision History .................................................................. 58

80960JA/JF

PRELIMINARY

1.0

PURPOSE

This document contains preliminary information for

the 80960JA/JF microprocessor, including electrical

characteristics and package pinout information.

Detailed functional descriptions — other than

parametric performance — are published in the

i960

Jx Microprocessor User’s Guide (272483).

Throughout this data sheet, references to “80960Jx”

indicate features which apply to all of the following:

• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte

data cache

• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache

• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte

data cache and clock doubling

• 80L960JA — 3.3 V version of the 80960JA

• 80L960JF — 3.3 V version of the 80960JF

2.0

80960JA/JF OVERVIEW

The 80960JA/JF offers high performance to cost-

sensitive 32-bit embedded applications. The

80960JA/JF is object code compatible with the

80960 Core Architecture and is capable of sustained

execution at the rate of one instruction per clock.

This processor’s features include generous

instruction cache, data cache and data RAM. It also

boasts a fast interrupt mechanism, dual program-

mable timer units and new instructions.

Memory subsystems for cost-sensitive embedded

applications often impose substantial wait state

penalties. The 80960JA/JF integrates considerable

storage resources on-chip to decouple CPU

execution from the external bus.

The 80960JA/JF rapidly allocates and deallocates

local register sets during context switches. The

processor needs to flush a register set to the stack

only when it saves more than seven sets to its local

A 32-bit multiplexed burst bus provides a high-speed

interface to system memory and I/O. A full

complement of control signals simplifies the

connection of the 80960JA/JF to external compo-

nents. The user programs physical and logical

memory attributes through memory-mapped control

registers (MMRs) — an extension not found on the

i960 Kx, Sx or Cx processors. Physical and logical

configuration registers enable the processor to

operate with all combinations of bus width and data

object alignment. The processor supports a homoge-

neous byte ordering model.

This processor integrates two important peripherals:

a timer unit and an interrupt controller. These and

other hardware resources are programmed through

memory-mapped control registers, an extension to

the familiar 80960 architecture.

The timer unit (TU) offers two independent 32-bit

timers for use as real-time system clocks and

general-purpose system timing. These operate in

either single-shot or auto-reload mode and can

generate interrupts.

The interrupt controller unit (ICU) provides a flexible,

low-latency means for requesting interrupts.The ICU

provides full programmability of up to 240 interrupt

sources into 31 priority levels. The ICU takes

advantage of a cached priority table and optional

routine caching to minimize interrupt latency. Local

registers may be dedicated to high-priority interrupts

to further reduce latency. Acting independently from

the core, the ICU compares the priorities of posted

interrupts with the current process priority, off-

loading this task from the core. The ICU also

supports the integrated timer interrupts.

The 80960JA/JF features a Halt mode designed to

support applications where low power consumption

is critical. The halt instruction shuts down instruction

execution, resulting in a power savings of up to 90

percent.

The 80960JA/JF’s testability features, including

ONCE (On-Circuit Emulation) mode and Boundary

Scan (JTAG), provide a powerful environment for

design debug and fault diagnosis.

The Solutions960® program features a wide variety

of development tools which support the i960

processor family. Many of these tools are developed

by partner companies; some are developed by Intel,

such as profile-driven optimizing compilers. For

more information on these products, contact your

local Intel representative.

PRELIMINARY

80960JA/JF

Figure 2. 80960JA/JF Block Diagram

Programmable

Bus

Control Unit

Interrupt Controller

Control

Address/

Instruction Sequencer

Physical Region

Configuration

Interrupt

Port

1 K byte

Data RAM

Memory

Interface

Execution

Multiply

Unit

Divide

Unit

Memory-Mapped

Data Bus

Global / Local

SRC2

DEST

SRC1

address

Control

effective

Constants

Generation

Unit

Address

32-bit Address

32-bit Data

Bus Request

Queues

and

Two 32-Bit

Timers

8-Set

Local Register Cache

PLL, Clocks,

Power Mgmt

Boundary Scan

Controller

TAP

CLKIN

128

32-bit buses

address / data

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

Instruction Cache

4 Kbyte (80960JF) or 2 Kbyte (80960JA)

Two-Way Set Associative

2 Kbyte (80960JF)

1 Kbyte (80960JA)

Direct Mapped

Data Cache

2.1

80960 Processor Core

The 80960Jx family is a scalar implementation of the

80960 Core Architecture. Intel designed this

processor core as a very high performance device

that is also cost-effective. Factors that contribute to

the core’s performance include:

• Single-clock execution of most instructions

• Independent Multiply/Divide Unit

• Efficient instruction pipeline minimizes pipeline

break latency

• Register and resource scoreboarding allow

overlapped instruction execution

• 128-bit register bus speeds local register caching

• Two-way set associative, integrated instruction

cache

• Direct-mapped, integrated data cache

• 1 Kbyte integrated data RAM delivers zero wait

state program data

2.2

Burst Bus

A 32-bit high-performance bus controller interfaces

the 80960JA/JF to external memory and peripherals.

The BCU fetches instructions and transfers data at

the rate of up to four 32-bit words per six clock

cycles. The external address/data bus is multi-

plexed.

80960JA/JF

PRELIMINARY

Users may configure the 80960JA/JF’s bus controller

to match an application’s fundamental memory

organization. Physical bus width is register-

programmed for up to eight regions. Byte ordering

and data caching are programmed through a group

of logical memory templates and a defaults register.

The BCU’s features include:

• Multiplexed external bus to minimize pin count

• 32-, 16- and 8-bit bus widths to simplify I/O

interfaces

• External ready control for address-to-data, data-to-

data and data-to-next-address wait state types

• Support for big or little endian byte ordering to

facilitate the porting of existing program code

• Unaligned bus accesses performed transparently

• Three-deep load/store queue to decouple the bus

from the core

Upon reset, the 80960JA/JF conducts an internal

self test. Then, before executing its first instruction, it

performs an external bus confidence test by

performing a checksum on the first words of the

initialization boot record (IBR).

The user may examine the contents of the caches at

any time by executing special cache control instruc-

tions.

2.3

Timer Unit

The timer unit (TU) contains two independent 32-bit

timers which are capable of counting at several clock

rates and generating interrupts. Each is programmed

by use of the TU registers. These memory-mapped

registers are addressable on 32-bit boundaries. The

timers have a single-shot mode and auto-reload

capabilities for continuous operation. Each timer has

an independent interrupt request to the interrupt

controller. The TU can generate a fault when

unauthorized writes from user mode are detected.

Clock prescaling is supported.

2.4

Priority Interrupt Controller

A programmable interrupt controller manages up to

240 external sources through an 8-bit external

interrupt port. Alternatively, the interrupt inputs may

be configured for individual edge- or level-triggered

inputs. The interrupt unit (IU) also accepts interrupts

from the two on-chip timer channels and a single

Non-Maskable Interrupt (NMI) pin. Interrupts are

serviced according to their priority levels relative to

the current process priority.

Low interrupt latency is critical to many embedded

applications. As part of its highly flexible interrupt

mechanism, the 80960JA/JF exploits several

techniques to minimize latency:

• Interrupt vectors and interrupt handler routines can

be reserved on-chip

• Register frames for high-priority interrupt handlers

can be cached on-chip

• The interrupt stack can be placed in cacheable

memory space

2.5

Instruction Set Summary

The 80960JA/JF adds several new instructions to the

i960 core architecture. The new instructions are:

• Conditional Move

• Conditional Add

• Conditional Subtract

• Byte Swap

• Halt

• Cache Control

• Interrupt Control

Table 1 identifies the instructions that the 80960Jx

supports. Refer to i960

Jx Microprocessor User’s

Guide (272483) for a detailed description of each

instruction.

2.6

Faults and Debugging

The 80960Jx employs a comprehensive fault model.

The processor responds to faults by making implicit

calls to a fault handling routine. Specific information

collected for each fault allows the fault handler to

diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In

software, the 80960Jx may be configured to detect

as many as seven different trace event types. Alter-

natively, mark and fmark instructions can generate

80960JA/JF

PRELIMINARY

trace events explicitly in the instruction stream.

Hardware breakpoint registers are also available to

trap on execution and data addresses.

2.7

Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-

micron manufacturing process. The processor’s sub-

micron topology provides the circuit density for

optimal cache size and high operating speeds while

dissipating modest power. The processor also uses

dynamic power management to turn off clocks to

unused circuits.

Users may program the 80960Jx to enter Halt mode

for maximum power savings. In Halt mode, the

processor core stops completely while the integrated

peripherals continue to function, reducing overall

power requirements up to 90 percent. Processor

execution resumes from internally or externally

generated interrupts.

2.8

Test Features

The 80960Jx incorporates numerous features which

enhance the user’s ability to test both the processor

and the system to which it is attached. These

features include ONCE (On-Circuit Emulation) mode

and Boundary Scan (JTAG).

The 80960Jx provides testability features compatible

with IEEE Standard Test Access Port and Boundary

Scan Architecture (IEEE Std. 1149.1).

One of the boundary scan instructions, HIGHZ,

forces the processor to float all its output pins

(ONCE mode). ONCE mode can also be initiated at

reset without using the boundary scan mechanism.

ONCE mode is useful for board-level testing. This

feature allows a mounted 80960JA/JF to electrically

“remove” itself from a circuit board. This allows for

system-level testing where a remote tester — such

as an in-circuit emulator — can exercise the

processor system.

The provided test logic does not interfere with

component or circuit board behavior and ensures

that components function correctly, connections

between various components are correct, and

various components interact correctly on the printed

circuit board.

The JTAG Boundary Scan feature is an attractive

alternative to conventional “bed-of-nails” testing. It

can examine connections which might otherwise be

inaccessible to a test system.

2.9

Memory-Mapped Control

Registers

The 80960JA/JF, though compliant with i960 series

processor core, has the added advantage of

memory-mapped, internal control registers not found

on the i960 Kx, Sx or Cx processors. These give

software the interface to easily read and modify

internal control registers.

Each of these registers is accessed as a memory-

mapped, 32-bit register. Access is accomplished

through regular memory-format instructions. The

processor ensures that these accesses do not

generate external bus cycles.

2.10

Data Types and Memory

Addressing Modes

As with all i960 family processors, the 80960JA/JF

instruction set supports several data types and

formats:

• Bit

• Bit fields

• Integer (8-, 16-, 32-, 64-bit)

• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

• Triple word (96 bits)

• Quad word (128 bits)

The 80960JA/JF provides a full set of addressing

modes for C and assembly programming:

• Two Absolute modes

• Five Register Indirect modes

• Index with displacement

• IP with displacement

PRELIMINARY

80960JA/JF

Table 1. 80960Jx Instruction Set

Data Movement

Arithmetic

Logical

Bit, Bit Field and Byte

Load

Store

Move

*Conditional Select

Load Address

Add

Subtract

Multiply

Divide

Remainder

Modulo

Shift

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

*Conditional Add

*Conditional Subtract

Rotate

And

Not And

And Not

Exclusive Or

Not Or

Or Not

Nor

Exclusive Nor

Not

Nand

Set Bit

Clear Bit

Not Bit

Alter Bit

Scan For Bit

Span Over Bit

Extract

Modify

Scan Byte for Equal

*Byte Swap

Comparison

Branch

Call/Return

Fault

Compare

Conditional Compare

Compare and

Increment

Compare and

Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Call Extended

Call System

Return

Branch and Link

Conditional Fault

Synchronize Faults

Debug

Processor

Management

Atomic

Modify Trace Controls

Mark

Force Mark

Flush Local Registers

Modify Arithmetic

Controls

Modify Process

Controls

*Halt

System Control

*Cache Control

*Interrupt Control

Atomic Add

Atomic Modify

NOTE:

Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB

implementations.

80960JA/JF

PRELIMINARY

3.0

PACKAGE INFORMATION

The 80960JA/JF will be offered in several speed and

package types. The 132-pin Pin Grid Array (PGA)

device will be specified for operation at

= 5.0 V ± 5% over a case temperature range of

0° to 100°C:

• A80960JA/JF-33 (33 MHz)

• A80960JA/JF-25 (25 MHz)

• A80960JA/JF-16 (16 MHz)

The 132-pin Plastic Quad Flatpack (PQFP) devices

will be specified for operation at V

= 5.0 V ± 5%

over a case temperature range of 0° to 100°C:

• NG80960JA/JF-33 (33 MHz)

• NG80960JA/JF-25 (25 MHz)

• NG80960JA/JF-16 (16 MHz)

For complete package specifications and infor-

mation, refer to Intel’s Packaging Handbook

(240800).

3.1

Pin Descriptions

This section describes the pins for the 80960JA/JF in

the 132-pin ceramic Pin Grid Array (PGA) package

and 132-lead Plastic Quad Flatpack Package

(PQFP).

Section 3.1.1, Functional Pin Definitions

describes pin function; Section 3.1.2, 80960Jx 132-

Lead PGA Pinout and Section 3.1.3, 80960Jx

PQFP Pinout define the signal and pin locations for

the supported package types.

3.1.1

Functional Pin Definitions

Table 2 presents the legend for interpreting the pin

descriptions which follow. Pins associated with the

bus interface are described in Table 3. Pins

associated with basic control and test functions are

described in Table 4. Pins associated with the

Interrupt Unit are described in Table 5.

Table 2. Pin Description Nomenclature

Symbol

Description

Input pin only.

Output pin only.

I/O

Pin can be either an input or output.

–

Pin must be connected as described.

Synchronous. Inputs must meet setup

and hold times relative to CLKIN for

proper operation.

S(E) Edge sensitive input

S(L) Level sensitive input

A (...)

Asynchronous. Inputs may be

asynchronous relative to CLKIN.

A(E) Edge sensitive input

A(L) Level sensitive input

R (...)

While the processor’s RESET pin is

asserted, the pin:

R(1) is driven to V

R(0) is driven to V

R(Q) is a valid output

R(X) is driven to unknown state

R(H) is pulled up to V

H (...)

While the processor is in the hold state,

the pin:

H(1) is driven to V

H(0) is driven to V

H(Q) Maintains previous state or

continues to be a valid output

H(Z) Floats

P (...)

While the processor is halted, the pin:

P(1) is driven to V

P(0) is driven to V

P(Q) Maintains previous state or

continues to be a valid output

PRELIMINARY

80960JA/JF

Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)

NAME

TYPE

DESCRIPTION

AD31:0

I/O

S(L)

R(X)

H(Z)

P(Q)

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data

to and from memory. During an address (

) cycle, bits 31:2 contain a physical word

address (bits 0-1 indicate SIZE; see below). During a data (T

) cycle, read or write

data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,

AD15:8 and AD7:0. During write operations, unused pins are driven to determinate

values.

SIZE, which comprises bits 0-1 of the AD lines during a

cycle, specifies the

number of data transfers during the bus transaction.

AD1

AD0

Bus Transfers

1 Transfer

2 Transfers

3 Transfers

4 Transfers

When the processor enters Halt mode, if the previous bus operation was a:

• write — AD31:2 are driven with the last data value on the AD bus.

• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are

driven with the value of A3:2 from the last data cycle.

Typically, AD1:0 reflect the SIZE information of the last bus transaction (either

instruction fetch or load/store) that was executed before entering Halt mode.

ALE

R(0)

H(Z)

P(0)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is

asserted during a

cycle and deasserted before the beginning of the T

state. It is

active HIGH and floats to a high impedance state during a hold cycle (T

ALE

R(1)

H(Z)

P(1)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the

inverted version of ALE. This signal gives the 80960JA/JF a high degree of compat-

ibility with existing 80960Kx systems.

ADS

R(1)

H(Z)

P(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

The processor asserts ADS for the entire

cycle. External bus control logic typically

samples ADS at the end of the cycle.

A3:2

R(X)

H(Z)

P(Q)

ADDRESS3:2 comprise a partial demultiplexed address bus.

32-bit memory accesses: the processor asserts address bits A3:2 during

. The

partial word address increments with each assertion of RDYRCV during a burst.

16-bit memory accesses: the processor asserts address bits A3:1 during

with A1

driven on the BE1 pin. The partial short word address increments with each

assertion of RDYRCV during a burst.

8-bit memory accesses: the processor asserts address bits A3:0 during

, with A1:0

driven on BE1:0. The partial byte address increments with each assertion of