© INTEL CORPORATION, 1996
November 1996
Order Number: 272971-001
PRODUCT PREVIEW
80960JD
3.3 V EMBEDDED 32-BIT MICROPROCESSOR
• 3.3 V, 5 V Tolerant, Version of the 80960JD Processor
Figure 1.
80960JD Microprocessor
s
Pin/Code Compatible with all 80960Jx
Processors
s
High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s
Two-Way Set Associative Instruction Cache
— 80960JD - 4 Kbyte
— Programmable Cache Locking
Mechanism
s
Direct Mapped Data Cache
— 80960JD - 2 Kbyte
— Write Through Operation
s
On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s
On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
s
3.3 V Supply Voltage
— 5 V Tolerant Inputs
— TTL Compatible Outputs
s
High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
s
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
s
Halt Mode for Low Power
s
IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s
Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
PIN 1
132
99
66
33
i960
®
i
M
i
© 19xx
M
© 19xx
A80960JD
NG80960JD
XXXXXXXXC0
XXXXXXXXC0S
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
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*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
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or call 1-800-548-4725
©INTEL CORPORATION, 1996
Contents
iii
CC5
Pin Requirements (V
DIFF
) ........................................................................................................ 23
Contents
iv
FIGURES
................................................................................................ 30
................................................................................................... 31
and T
IH1
...................................................................... 31
and T
IH2
...................................................................... 32
and T
IH3
...................................................................... 32
and T
IH4
...................................................................... 33
, T
LXL
and T
LXA
.................................................................... 33
and T
BSIH1
............................................................. 35
AND T
BSOF1
............................................ 35
and T
BSOF2
............................................. 36
and T
BSIH2
............................................................... 36
Contents
v
TABLES
at Various Airflows in °C ......................................................................................... 21
80960JD
PRODUCT PREVIEW
1
1.0
PURPOSE
This document contains preview information for the
80960JD microprocessor, including electrical
characteristics and package pinout information.
Detailed functional descriptions — other than
parametric performance — are published in the
i960
®
Jx Microprocessor User’s Guide
(272483).
Throughout this data sheet, references to “80960Jx”
indicate features which apply to all of the following:
• 80960JA — 5V, 2 Kbyte instruction cache, 1 Kbyte
data cache
• 80L960JA — 3.3 V version of the 80960JA
• 80960JD — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache and clock doubling
• 80960JD — 3.3V, 5V Tolerant version of the
80960JD
• 80960JF — 5V, 4 Kbyte instruction cache, 2 Kbyte
data cache
• 80L960JF — 3.3 V version of the 80960JF
2.0
80960JD OVERVIEW
The 80960JD offers high performance to cost-
sensitive 32-bit embedded applications. The
80960JD is object code compatible with the 80960
Core Architecture and is capable of sustained
execution at the rate of one instruction per clock.
This processor’s features include generous
instruction cache, data cache and data RAM. It also
boasts a fast interrupt mechanism, dual program-
mable timer units and new instructions.
The 80960JD’s clock doubler operates the processor
core at twice the bus clock rate to improve execution
performance without increasing the complexity of
board designs.
Memory subsystems for cost-sensitive embedded
applications often impose substantial wait state
penalties. The 80960JD integrates considerable
storage resources on-chip to decouple CPU
execution from the external bus.
The 80960JD rapidly allocates and deallocates local
register sets during context switches. The processor
needs to flush a register set to the stack only when it
saves more than seven sets to its local register cache.
A 32-bit multiplexed burst bus provides a high-speed
interface to system memory and I/O. A full
complement of control signals simplifies the
connection of the 80960JD to external components.
The user programs physical and logical memory
attributes through memory-mapped control registers
(MMRs) — an extension not found on the i960 Kx,
Sx or Cx processors. Physical and logical configu-
ration registers enable the processor to operate with
all combinations of bus width and data object
alignment. The processor supports a homogeneous
byte ordering model.
This processor integrates two important peripherals:
a timer unit and an interrupt controller. These and
other hardware resources are programmed through
memory-mapped control registers, an extension to
the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit
timers for use as real-time system clocks and
general-purpose system timing. These operate in
either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible
means for requesting interrupts. The ICU provides
full programmability of up to 240 interrupt sources
into 31 priority levels. The ICU takes advantage of a
cached priority table and optional routine caching to
minimize interrupt latency. Clock doubling reduces
interrupt latency by 40% compared to the
80960JA/JF. Local registers may be dedicated to
high-priority interrupts to further reduce latency.
Acting independently from the core, the ICU
compares the priorities of posted interrupts with the
current process priority, off-loading this task from the
core. The ICU also supports the integrated timer
interrupts.
The 80960JD features a Halt mode designed to
support applications where low power consumption
is critical. The halt instruction shuts down instruction
execution, resulting in a power savings of up to 90
percent.
The 80960JD’s testability features, including ONCE
(On-Circuit Emulation) mode and Boundary Scan
(JTAG), provide a powerful environment for design
debug and fault diagnosis.
The
Solutions960®
program features a wide variety
of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For
more information on these products, contact your
local Intel representative.
80960JD
2
PRODUCT PREVIEW
Figure 2. 80960JD Block Diagram
Programmable
Bus
Control Unit
Interrupt Controller
Control
Address/
Instruction Sequencer
Physical Region
Configuration
Interrupt
Port
1 K byte
Data RAM
Memory
Interface
Execution
Multiply
Unit
Divide
Unit
Memory-Mapped
Register Interface
Data Bus
Global / Local
Register File
SRC2 DEST
SRC1
address
Control
effective
Constants
Generation
Unit
Address
32-bit Address
32-bit Data
Bus Request
Queues
and
Two 32-Bit
Timers
8-Set
Local Register Cache
S
RC1
S
RC2
DE
ST
PLL, Clocks,
Power Mgmt
Boundary Scan
Controller
TAP
5
CLKIN
128
SRC1
SRC2
DEST
SRC1
DEST
9
32
32-bit buses
address / data
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
21
4 KByte Instruction Cache
Two-Way Set Associative
2 Kbyte Direct
Mapped Data
Cache
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effective. Factors that contribute to
the core’s performance include:
• Core operates at twice the bus speed (80960JD
only)
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
2.2
Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multi-
plexed.
Users may configure the 80960JD’s bus controller to
match an application’s fundamental memory organi-
zation. Physical bus width is register-programmed
for up to eight regions. Byte ordering and data
caching are programmed through a group of logical
memory templates and a defaults register.
80960JD
PRODUCT PREVIEW
3
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16- and 8-bit bus widths to simplify I/O
interfaces
• External ready control for address-to-data, data-to-
data and data-to-next-address wait state types
• Support for big or little endian byte ordering to
facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus
from the core
Upon reset, the 80960JD conducts an internal self
test. Then, before executing its first instruction, it
performs an external bus confidence test by
performing a checksum on the first words of the
initialization boot record (IBR).
The user may examine the contents of the caches at
any time by executing special cache control instruc-
tions.
2.3
Timer Unit
The timer unit (TU) contains two independent 32-bit
timers which are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the TU registers. These memory-mapped
registers are addressable on 32-bit boundaries. The
timers have a single-shot mode and auto-reload
capabilities for continuous operation. Each timer has
an independent interrupt request to the 80960JD’s
interrupt controller. The TU can generate a fault
when unauthorized writes from user mode are
detected. Clock prescaling is supported.
2.4
Priority Interrupt Controller
A programmable interrupt controller manages up to
240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may
be configured for individual edge- or level-triggered
inputs. The interrupt unit (IU) also accepts interrupts
from the two on-chip timer channels and a single
Non-Maskable Interrupt (NMI) pin. Interrupts are
serviced according to their priority levels relative to
the current process priority.
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960JD exploits several
techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
• Interrupt microcode executes at twice the bus
frequency
2.5
Instruction Set Summary
The 80960Jx adds several new instructions to the
i960 core architecture. The new instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control
Table 1 identifies the instructions that the 80960Jx
supports. Refer to
i960
®
Jx Microprocessor User’s
Guide
(272483) for a detailed description of each
instruction.
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In
software, the 80960Jx may be configured to detect
as many as seven different trace event types. Alter-
natively, mark and fmark instructions can generate
trace events explicitly in the instruction stream.
Hardware breakpoint registers are also available to
trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-
micron manufacturing process. The processor’s sub-
micron topology provides the circuit density for
optimal cache size and high operating speeds while
80960JD
4
PRODUCT PREVIEW
dissipating modest power. The processor also uses
dynamic power management to turn off clocks to
unused circuits.
Users may program the 80960Jx to enter Halt mode
for maximum power savings. In Halt mode, the
processor core stops completely while the integrated
peripherals continue to function, reducing overall
power requirements up to 90 percent. Processor
execution resumes from internally or externally
generated interrupts.
2.8
Test Features
The 80960Jx incorporates numerous features which
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible
with IEEE Standard Test Access Port and Boundary
Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This
feature allows a mounted 80960JD to electrically
“remove” itself from a circuit board. This allows for
system-level testing where a remote tester — such
as an in-circuit emulator — can exercise the
processor system.
The provided test logic does not interfere with
component or circuit board behavior and ensures
that components function correctly, connections
between various components are correct, and
various components interact correctly on the printed
circuit board.
The JTAG Boundary Scan feature is an attractive
alternative to conventional “bed-of-nails” testing. It
can examine connections which might otherwise be
inaccessible to a test system.
2.9
Memory-Mapped Control
Registers
The 80960JD, though compliant with i960 series
processor core, has the added advantage of
memory-mapped, internal control registers not found
on the i960 Kx, Sx or Cx processors. These give
software the interface to easily read and modify
internal control registers.
Each of these registers is accessed as a memory-
mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.
2.10 Data Types and Memory
Addressing Modes
As with all i960 family processors, the 80960Jx
instruction set supports several data types and
formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960Jx provides a full set of addressing modes
for C and assembly programming:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement
• IP with displacement
80960JD
PRODUCT PREVIEW
5
Table 1. 80960Jx Instruction Set
Data Movement
Arithmetic
Logical
Bit, Bit Field and Byte
Load
Store
Move
*Conditional Select
Load Address
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
*Conditional Add
*Conditional Subtract
Rotate
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Modify
Scan Byte for Equal
*Byte Swap
Comparison
Branch
Call/Return
Fault
Compare
Conditional Compare
Compare and
Increment
Compare and
Decrement
Test Condition Code
Check Bit
Unconditional Branch
Conditional Branch
Compare and Branch
Call
Call Extended
Call System
Return
Branch and Link
Conditional Fault
Synchronize Faults
Debug
Processor
Management
Atomic
Modify Trace Controls
Mark
Force Mark
Flush Local Registers
Modify Arithmetic
Controls
Modify Process
Controls
*Halt
System Control
*Cache Control
*Interrupt Control
Atomic Add
Atomic Modify
NOTES:
Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB
implementations.
80960JD
6
PRODUCT PREVIEW
3.0
PACKAGE INFORMATION
The 80960JD is offered with three speeds and two
package types. The 132-pin Pin Grid Array (PGA)
device is specified for operation at V
CC
= 3.3 V ± 5%
over a case temperature range of 0° to 100°C:
• A80960JD-66 (66 MHz core, 33 MHz bus)
• A80960JD-50 (50 MHz core, 25 MHz bus)
• A80960JD-40 (40 MHz core, 20 MHz bus)
The 132-pin Plastic Quad Flatpack (PQFP) devices
will be specified for operation at V
CC
= 3.3 V ± 5%
over a case temperature range of 0° to 100°C:
• NG80960JD-66 (66 MHz core, 33 MHz bus)
• NG80960JD-50 (50 MHz core, 25 MHz bus)
• NG80960JD-40 (40 MHz core, 20 MHz bus)
For complete package specifications and infor-
mation, refer to Intel’s
Packaging Handbook
(240800).
3.1
Pin Descriptions
This section describes the pins for the 80960JD in
the 132-pin ceramic Pin Grid Array (PGA) package
and 132-lead Plastic Quad Flatpack Package
(PQFP).
the supported package types.
3.1.1
Functional Pin Definitions
Table 2 presents the legend for interpreting the pin
descriptions which follow. Pins associated with the
bus interface are described in Table 3. Pins
associated with basic control and test functions are
described in Table 4. Pins associated with the
Interrupt Unit are described in Table 5.
Table 2. Pin Description Nomenclature
Symbol
Description
I
Input pin only.
O
Output pin only.
I/O
Pin can be either an input or output.
–
Pin must be connected as described.
S
Synchronous. Inputs must meet setup
and hold times relative to CLKIN for
proper operation.
S(E) Edge sensitive input
S(L) Level sensitive input
A (...)
Asynchronous. Inputs may be
asynchronous relative to CLKIN.
A(E) Edge sensitive input
A(L) Level sensitive input
R (...)
While the processor’s RESET pin is
asserted, the pin:
R(1) is driven to V
CC
R(0) is driven to V
SS
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to V
CC
H (...)
While the processor is in the hold state,
the pin:
H(1) is driven to V
CC
H(0) is driven to V
SS
H(Q) Maintains previous state or
continues to be a valid output
H(Z) Floats
P (...)
While the processor is halted, the pin:
P(1) is driven to V
CC
P(0) is driven to V
SS
P(Q) Maintains previous state or
continues to be a valid output
80960JD
PRODUCT PREVIEW
7
Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)
NAME
TYPE
DESCRIPTION
AD31:0
I/O
S(L)
R(X)
H(Z)
P(Q)
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (
T
a
) cycle, bits 31:2 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (T
d
) cycle, read or write
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
SIZE, which comprises bits 0-1 of the AD lines during a
T
a
cycle, specifies the
number of data transfers during the bus transaction.
AD1
AD0
Bus Transfers
0
0
1 Transfer
0
1
2 Transfers
1
0
3 Transfers
1
1
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ALE
O
R(0)
H(Z)
P(0)