© INTEL CORPORATION, 1997
September, 1997
Order Number: 273001-002
ADVANCE INFORMATION
i960
®
RP/RD I/O PROCESSOR AT 3.3 VOLTS
• 33 MHz, 3.3 Volt Version (80960RP 33/3.3)
• 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core
• Complies with PCI Local Bus Specification Revision 2.1
• 5 Volt PCI Signalling Environment
s
High Performance 80960JF Core
— Sustained One Instruction/Clock
Execution
— 4 Kbyte Two-Way Set-Associative
Instruction Cache
— 2 Kbyte Direct-Mapped Data Cache
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Programmable Bus Widths:
8-, 16-, 32-Bit
— 1 Kbyte Internal Data RAM
— Local Register Cache
(Eight Available Stack Frames)
— Two 32-Bit On-Chip Timer Units
s
PCI-to-PCI Bridge Unit
— Primary and Secondary PCI Interfaces
— Two 64-Byte Posting Buffers
— Delayed and Posted Transaction
Support
— Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
s
Two Address Translation Units
— Connects Local Bus to PCI Buses
— Inbound/Outbound Address Translation
Support
— Direct Outbound Addressing Support
s
Messaging Unit
— Four Message Registers
— Two Doorbell Registers
— Four Circular Queues
— 1004 Index Registers
s
Memory Controller
— 256 Mbytes of 32- or 36-Bit DRAM
— Interleaved or Non-Interleaved DRAM
— Fast Page-Mode DRAM Support
— Extended Data Out and Burst
— Extended Data Out DRAM Support
— Two Independent Banks for SRAM / ROM
/ Flash (16 Mbytes/Bank; 8- or 32-Bit)
s
DMA Controller
— Three Independent Channels
— PCI Memory Controller Interface
— 32-Bit Local Bus Addressing
— 64-Bit PCI Bus Addressing
— Independent Interface to Primary and
Secondary PCI Buses
— 132 Mbyte/sec Burst Transfers to PCI
and Local Buses
— Direct Addressing to and from PCI
Buses
— Unaligned Transfers Supported in
Hardware
— Two Channels Dedicated to Primary
PCI Bus
— One Channel Dedicated to Secondary
PCI Bus
s
I/O APIC Bus Interface Unit
— Multiprocessor Interrupt Management
for Intel Architecture CPUs
(Pentium
®
and Pentium
®
Pro
Processors)
— Dynamic Interrupt Distribution
— Multiple I/O Subsystem Support
s
I
2
C Bus Interface Unit
— Serial Bus
— Master/Slave Capabilities
— System Management Functions
s
Secondary PCI Arbitration Unit
— Supports Six Secondary PCI Devices
— Multi-priority Arbitration Algorithm
— External Arbitration Support Mode
s
Private PCI Device Support
s
SuperBGA* Package
— 352 Ball-Grid Array (HL-PBGA)
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
©INTEL CORPORATION, 1997
i960
®
Rx I/O Processor at 3.3 V
iii
Program ...................................................................................................................... 1
CC5
Pin Requirements (V
DIFF
) ........................................................................................................ 34
i960
®
Rx I/O Processor at 3.3 V
iv
FIGURES
®
Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2
OV
Output Delay Waveform ....................................................................................................... 45
OF
Output Float Waveform ......................................................................................................... 45
IS
and T
IH
Input Setup and Hold Waveform ............................................................................... 46
LXL
and T
LXA
Relative Timings Waveform ................................................................................. 46
2
C Interface Signal Timings ........................................................................................................ 47
TABLES
C Units Signal Descriptions .................................................................................. 19
(Sheet 1 of 4) ........................................... 23
Specification for Dual Power Supply Requirements (3.3 V, 5 V) ....................................... 34
Characteristics ....................................................................................................................... 36
i960
®
Rx I/O Processor at 3.3 V
vi
i960
®
Rx I/O Processor at 3.3 V
ADVANCE INFORMATION
1
1.0
ABOUT THIS DOCUMENT
This is the ADVANCE INFORMATION data sheet for
the low-power (3.3 V) versions of Intel’s i960
®
Rx I/O
Processor family, including:
• 80960RD 66/3.3
• 80960RP 33/3.3
Throughout this document, these family members
are referred to as
80960Rx
when the information is
common to both. For product-specific information,
such as electrical characteristics, the family member
names are used.
This does not contain specifications for the 5 Volt
version (80960RP 33/5.0). For specifications on that
product, refer to the
i960
®
RP I/O Processor
Data
Sheet (272737).
This data sheet contains a functional overview,
mechanical data (package signal locations and
simulated thermal characteristics), targeted electrical
specifications (simulated), and bus functional wave-
forms. Detailed functional descriptions other than
parametric performance is published in the
i960
®
RP
Microprocessor User’s Guide
(272736).
1.1
Solutions960
®
Program
Intel’s
Solutions960
®
program features a wide
variety of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For
more information on these products, contact your
local Intel representative.
1.2
Terminology
In this document, the following terms are used:
•
local bus
refers to the 80960Rx’s internal local
bus, not the PCI local bus.
•
Primary and Secondary PCI buses
are the
80960Rx’s internal PCI buses which conform to
PCI SIG specifications.
•
80960 core
refers to the 80960JF processor which
is integrated into the 80960Rx.
1.3
Additional Information Sources
Intel documentation is available from your local Intel
Sales Representative or Intel Literature Sales.
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect IL 60056-7641
1-800-879-4683
Table 1. Related Documentation
Document Title
Order / Contact
i960
®
RP Microprocessor User’s Guide
Intel Order # 272736
i960
®
RP Processor: A Single-Chip Intelligent I/O Subsystem
Technical Brief
Intel Order # 272738
i960
®
Jx Microprocessor User’s Guide
Intel Order # 272483
80960RP Specification Update
Intel Order # 272918
PCI Local Bus Specification
Revision 2.1
PCI Special Interest Group 1-800-433-5177
PCI-to-PCI Bridge Architecture Specification
Revision 1.0
PCI Special Interest Group 1-800-433-5177
I
2
C Peripherals for Microcontrollers
Philips Semiconductor
2
ADVANCE INFORMATION
i960
®
Rx I/O Processor at 3.3 V
2.0
FUNCTIONAL OVERVIEW
As indicated in
many features with the 80960JF to create an intelli-
gent I/O processor. Subsections following the figure
briefly describe the main features; for detailed func-
tional descriptions, refer to the
i960
®
RP Micropro-
cessor User’s Guide
(272736).
The PCI bus is an industry standard, high perfor-
mance, low latency system bus that operates up to
132 Mbyte/s. The 80960Rx, a multi-function PCI
device, is fully compliant with the
PCI Local Bus
Specification
Revision 2.1. Function 0 is the PCI-to-
PCI bridge unit; Function 1 is the address translation
unit.
The PCI-to-PCI bridge unit is the connection path
between two independent 32-bit PCI buses and
provides the ability to overcome PCI electrical load
limits. The addition of the i960 core processor brings
intelligence to the bridge.
The 80960Rx, object code compatible with the i960
core processor, is capable of sustained execution at
the rate of one instruction per clock.
The local bus, a 32-bit multiplexed burst bus, is a
high-speed interface to system memory and I/O. A
full complement of control signals simplifies the
connection of the 80960Rx to external components.
Physical and logical memory attributes are
programmed via memory-mapped control registers
(MMRs), an extension not found on the i960 Kx, Sx
or Cx processors. Physical and logical configuration
registers enable the processor to operate with all
combinations of bus width and data object align-
ment.
Figure 1. i960
®
Rx I/O Processor at 3.3 V Functional Block Diagram
PCI-to-PCI
Bridge Unit
i
960
®
JF
Core
Processor
Secondary
PCI Arbitration
Unit
Secondary PCI Bus
Primary PCI Bus
Local Memory
I
2
C Bus
Interface Unit
Memory
Controller
Internal
Arbitration
I
2
C Serial Bus
I/O APIC Bus
Interface Unit
I/O APIC Bus
Address
Translation
Unit
Two DMA
Channels
Address
Translation
Unit
One DMA
Channel
Message
Unit
Local Bus
Primary ATU
Secondary ATU
i960
®
Rx I/O Processor at 3.3 V
ADVANCE INFORMATION
3
2.1
Key Functional Units
2.1.1
PCI-to-PCI Bridge Unit
The PCI-to-PCI bridge unit (referred to as “bridge”)
connects two independent PCI buses. It is fully
compliant with the
PCI-to-PCI Bridge Architecture
Specification
Revision 1.0 published by the PCI
Special Interest Group. It allows certain bus transac-
tions on one PCI bus to be forwarded to the other
PCI bus. Dedicated data queues support high perfor-
mance bandwidth on the PCI buses. The i960
®
Rx
I/O Processor at 3.3 V supports PCI 64-bit Dual
Address Cycle (DAC) addressing.
The bridge has dedicated PCI configuration space
that is accessible through the primary PCI bus.
2.1.2
Private PCI Device Support
A key design feature is that the 80960Rx explicitly
supports private PCI devices on the secondary PCI
bus without being detected by PCI configuration soft-
ware. The bridge and Address Translation Unit work
together to hide private devices from PCI configura-
tion cycles and allow these devices to use a private
PCI address space. The Address Translation Unit
uses normal PCI configuration cycles to configure
these devices.
2.1.3
DMA Controller
The DMA Controller supports low-latency, high-
throughput data transfers between PCI bus agents
and 80960 local memory. Three separate DMA
channels accommodate data transfers: two for
primary PCI bus, one for the secondary PCI bus.
The DMA Controller supports chaining and
unaligned data transfers. It is programmable only
through the i960 core processor.
2.1.4
Address Translation Unit
The Address Translation Unit (ATU) allows PCI
transactions direct access to the 80960Rx local
memory. The 80960Rx has direct access to both PCI
buses. The ATU supports transactions between PCI
address space and 80960Rx address space.
Address translation is controlled through program-
mable registers accessible from both the PCI inter-
face and the 80960 core. Dual access to registers
allows flexibility in mapping the two address spaces.
2.1.5
Messaging Unit
The Messaging Unit (MU) provides data transfer
between the PCI system and the 80960Rx. It uses
interrupts to notify each system when new data
arrives. The MU has four messaging mechanisms.
Each allows a host processor or external PCI device
and the 80960Rx to communicate through message
passing and interrupt generation. The four mecha-
nisms are Message Registers, Doorbell Registers,
Circular Queues, and Index Registers.
2.1.6
Memory Controller
The Memory Controller allows direct control of
external memory systems, including DRAM, SRAM,
ROM and Flash Memory. It provides a direct connect
interface to memory that typically does not require
external logic. It features programmable chip selects,
a wait state generator and byte parity. External
memory can be configured as PCI addressable
memory or private processor memory.
2.1.7
I
2
C Bus Interface Unit
The I
2
C (Inter-Integrated Circuit) Bus Interface Unit
allows the 80960 core to serve as a master and
slave device residing on the I
2
C bus. The I
2
C bus is
a serial bus developed by Philips Semiconductor
consisting of a two pin interface. The bus allows the
80960Rx to interface to other I
2
C peripherals and
microcontrollers for system management functions.
It requires a minimum of hardware for an economical
system to relay status and reliability information on
the I/O subsystem to an external device. For more
information, see
I
2
C Peripherals for Microcontrollers
(Philips Semiconductor)
2.1.8
I/O APIC Bus Interface Unit
The I/O APIC Bus Interface Unit provides an inter-
face to the three-wire Advanced Programmable
Interrupt Controller (APIC) bus that allows I/O APIC
emulation in software. Interrupt messages can be
sent on the bus and EOI messages can be received.
4
ADVANCE INFORMATION
i960
®
Rx I/O Processor at 3.3 V
2.1.9
Secondary PCI Arbitration Unit
The Secondary PCI Arbitration Unit provides PCI
arbitration for the secondary PCI bus. It includes a
fairness algorithm with programmable priorities and
six PCI Request and Grant signal pairs. This arbitra-
tion unit can also be disabled to allow for external
arbitration.
2.2
i960 Core Features (80960JF)
The processing power of the 80960Rx comes from
the 80960JF processor core. The 80960JF is a new,
scalar implementation of the 80960 Core Architec-
Core processor.
Factors that contribute to the 80960 family core’s
performance include:
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set-associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
The 80960 core operates out of its own 32-bit
address space, which is independent of the PCI
address space. The local bus memory can be:
• Made visible to the PCI address space
• Kept private to the 80960 core
• Allocated as a combination of the two
Figure 2. 80960JF Core Block Diagram
Programmable
Bus
Control Unit
Interrupt Controller
Control
Address/
Instruction Sequencer
Physical Region
Configuration
Interrupt
Port
1 K byte
Data RAM
Memory
Interface
Execution
Multiply
Unit
Divide
Unit
Memory-Mapped
Register Interface
Data Bus
Global / Local
Register File
SRC2
DST
SRC1
Address
Control
Effective
Constants
Generation
Unit
Address
32-bit Addr
32-bit Data
Bus Request
Queues
and
Two 32-Bit
Timers
8-Set
Local Register
S
RC1
S
RC2
DS
T
PLL, Clocks,
Power Mgmt
Boundary Scan
Controller
TAP
5
128
S
RC1
S
RC2
DS
T
S
RC1
DS
T
9
32
32-bit buses
address / data
3 Independent 32-Bit SRC1, SRC2, and DST Buses
Instruction Cache
4 Kbyte Two-Way Set Associative
2 Kbyte
Direct Mapped
Data Cache
S_CLK
Cache
i960
®
Rx I/O Processor at 3.3 V
ADVANCE INFORMATION
5
2.2.1
Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960Rx to external memory and peripherals.
The Bus Control Unit fetches instructions and trans-
fers data on the local bus at the rate of up to four 32-
bit words per six clock cycles. The external
address/data bus is multiplexed.
Users may configure the 80960Rx’s bus controller to
match an application’s fundamental memory organi-
zation. Physical bus width is programmable for up to
eight regions. Data caching is programmed through
a group of logical memory templates and a defaults
register. The Bus Control Unit’s features include:
• Multiplexed external bus minimizes pin count
• 32-, 16- and 8-bit bus widths simplify I/O interfaces
• External ready control for address-to-data, data-to-
data and data-to-next-address wait state types
• Little endian byte ordering
• Unaligned bus accesses performed transparently
• Three-deep load/store queue decouples the bus
from the 80960 core
Upon reset, the 80960Rx conducts an internal self
test. Before executing its first instruction, it performs
an external bus confidence test by performing a
checksum on the first words of the Initialization Boot
Record.
2.2.2
Timer Unit
The timer unit (TU) contains two independent 32-bit
timers that are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the Timer Unit registers. These memory-
mapped registers are addressable on 32-bit bound-
aries. The timers have a single-shot mode and auto-
reload capabilities for continuous operation. Each
timer has an independent interrupt request to the
80960Rx’s interrupt controller. The TU can generate
a fault when unauthorized writes from user mode are
detected.
2.2.3
Priority Interrupt Controller
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960Rx exploits several tech-
niques to minimize latency:
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
2.2.4
Faults and Debugging
The 80960Rx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities.
Via software, the 80960Rx may be configured to
detect as many as seven different trace event types.
Alternatively, mark and fmark instructions can
generate trace events explicitly in the instruction
stream. Hardware breakpoint registers are also
available to trap on execution and data addresses.
2.2.5
On-Chip Cache and Data RAM
Memory subsystems often impose substantial wait
state penalties. The 80960Rx integrates consider-
able storage resources on-chip to decouple CPU
execution from the external bus. It also includes a
4 Kbyte instruction cache, a 2 Kbyte data cache and
1 Kbyte data RAM.
2.2.6
Local Register Cache
The 80960Rx rapidly allocates and deallocates local
register sets during context switches. The processor
needs to flush a register set to the stack only when it
saves more than seven sets to its local register
cache.
2.2.7
Test Features
The 80960Rx incorporates numerous features that
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
The 80960Rx provides testability features compat-
ible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
i960
®
Rx I/O Processor at 3.3 V
6
ADVANCE INFORMATION
One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This
feature allows a mounted 80960Rx to electrically
“remove” itself from a circuit board. This mode allows
system-level testing where a remote tester can
exercise the processor system.
The test logic does not interfere with component or
system behavior and ensures that components
function correctly, and also the connections between
various components are correct.
The JTAG Boundary Scan feature is an alternative
to conventional “bed-of-nails” testing. It can examine
connections that might otherwise be inaccessible to
a test system.
2.2.8
Memory-Mapped Control Registers
The 80960Rx is compliant with 80960 family archi-
tecture and has the added advantage of memory-
mapped, internal control registers not found on the
80960Kx, Sx or Cx processors. This feature provides
software an interface to easily read and modify
internal control registers.
Each memory-mapped, 32-bit register is accessed
via regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.
2.2.9
Instructions, Data Types and Memory
Addressing Modes
As with all 80960 family processors, the 80960Rx