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November 1995

INTEL CORPORATION 1995

Order Number 290406-007

1-MBIT (128K x 8)

BOOT BLOCK FLASH MEMORY

28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B

High-Integration Blocked Architecture

One 8 KB Boot Block w Lock Out

Two 4 KB Parameter Blocks

One 112 KB Main Block

100 000 Erase Program Cycles Per

Block

Simplified Program and Erase

Automated Algorithms via On-Chip

Write State Machine (WSM)

SRAM-Compatible Write Interface

Deep Power-Down Mode

0 05 mA I

Typical

0 8 mA I

Typical

12 0V

5% V

High-Performance Read

70 75 ns 90 ns 120 ns 150 ns

Maximum Access Time

5 0V

10% V

Hardware Data Protection Feature

Erase Write Lockout during Power

Transitions

Advanced Packaging JEDEC Pinouts

32-Pin PDIP

32-Lead PLCC TSOP

ETOX

II Nonvolatile Flash

Technology

EPROM-Compatible Process Base

High-Volume Manufacturing

Experience

Extended Temperature Options

Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with

features that simplify write and allow block erase These devices aid the system designer by combining the

functions of several components into one making boot block flash an innovative alternative to EPROM and

EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the

28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor

interface

The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of

8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment

conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and

state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-

vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s

MCS -186 family 80286 i386

i486

i860

and 80960CA With exactly the same memory segmentation

the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory

such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless

otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document

The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is

designed to contain secure code which will bring up the system minimally and download code to the other

locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-

performance access speeds low power consumption and immunity to noise Its access time provides

no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown

mode lowers power consumption to 0 25 mW typical through V

crucial in laptop computer handheld instru-

mentation and other low-power applications The RP

power control input also provides absolute data protec-

tion during system powerup or power loss

Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the

highest levels of quality reliability and cost-effectiveness

NOTE

The 28F001BN is equivalent to the 28F001BX

28F001BX-T 28F001BX-B

290406 – 1

Figure 1 28F001BX Block Diagram

Table 1 Pin Description

Symbol

Type

Name and Function

– A

INPUT

ADDRESS INPUTS

for memory addresses Addresses are internally latched during

a write cycle

– DQ

INPUT

DATA INPUTS OUTPUTS

Inputs data and commands during memory write

cycles outputs data during memory Status Register and Identifier read cycles The

OUTPUT

data pins are active high and float to tri-state off when the chip is deselected or the

outputs are disabled Data is internally latched during a write cycle

INPUT

CHIP ENABLE

Activates the device’s control logic input buffers decoders and

sense amplifiers CE

is active low CE

high deselects the memory device and

reduces power consumption to standby levels

INPUT

POWERDOWN

Puts the device in deep powerdown mode RP

is active low

high gates normal operation RP

allows programming of the boot

block RP

also locks out erase or write operations when active low providing data

protection during power transitions RP

active resets internal automation Exit

from deep powerdown sets device to Read Array mode

INPUT

OUTPUT ENABLE

Gates the device’s outputs through the data buffers during a

read cycle OE

is active low OE

(pulsed) allows programming of the

boot block

INPUT

WRITE ENABLE

Controls writes to the Command Register and array blocks WE

is active low Addresses and data are latched on the rising edge of the WE

pulse

ERASE PROGRAM POWER SUPPLY

for erasing blocks of the array or

programming bytes of each block Note With V

PPL

max memory contents

cannot be altered

DEVICE POWER SUPPLY

(5V

10%)

GND

GROUND

28F001BX-T 28F001BX-B

290406 – 4

Figure 4 PLCC Lead Configuration

APPLICATIONS

The 28F001BX flash ‘boot block’ memory augments

the non-volatility in-system electrical erasure and

reprogrammability of Intel’s standard flash memory

by offering four separately erasable blocks and inte-

grating a state machine to control erase and pro-

gram functions The specialized blocking architec-

ture and automated programming of the 28F001BX

provide a full-function non-volatile flash memory

ideal for a wide range of applications including PC

boot BIOS memory minimum-chip embedded pro-

gram memory and parametric data storage The

28F001BX combines the safety of a hardware-pro-

tected 8-KByte boot block with the flexibility of three

separately reprogrammable blocks (two 4-KByte pa-

rameter blocks and one 112-KByte code block) into

one versatile cost-effective flash memory Addition-

ally reprogramming one block does not affect code

stored in another block ensuring data integrity

The flexibility of flash memory reduces costs

throughout the life cycle of a design During the early

stages of a system’s life flash memory reduces pro-

totype development and testing time allowing the

system designer to modify in-system software elec-

trically versus manual removal of components Dur-

ing production flash memory provides flexible firm-

ware for just-in-time configuration reducing system

inventory and eliminating unnecessary handling and

less reliable socketed connections Late in the life

cycle when software updates or code ‘‘bugs’’ are

often unpredictable and costly flash memory reduc-

es update costs by allowing the manufacturers to

send floppy updates versus a technician Alterna-

tively remote updates over a communication link are

possible at speeds up to 9600 baud due to flash

memory’s fast programming time

28F001BX-T 28F001BX-B

Reprogrammable environments such as the per-

sonal computer

are ideal applications for the

28F001BX

The internal state machine provides

SRAM-like timings for program and erasure using

the Command and Status Registers The blocking

scheme allows BIOS update in the main and param-

eter blocks while still providing recovery code in the

boot block in the unlikely event a power failure oc-

curs during an update or where BIOS code is cor-

rupted Parameter blocks also provide convenient

configuration storage backing up SRAM and battery

configurations

EISA systems

for example

can

store hardware configurations in a flash parameter

block reducing system SRAM

Laptop BIOSs are becoming increasingly complex

with the addition of power management software

and extended system setup screens BIOS code

complexity increases the potential for code updates

after the sale but the compactness of laptop de-

signs makes hardware updates very costly Boot

block flash memory provides an inexpensive update

solution for laptops while reducing laptop obsoles-

cence For portable PCs and hand-held equipment

the deep powerdown mode dramatically lowers sys-

tem power requirements during periods of slow op-

eration or sleep modes

The 28F001BX gives the embedded system design-

er several desired features The internal state ma-

chine reduces the size of external code dedicated to

the erase and program algorithms as well as freeing

the microcontroller or microprocessor to respond to

other system requests during program and erasure

The four blocks allow logical segmentation of the

entire embedded software the 8-KByte block for the

boot code the 112-KByte block for the main pro-

gram code and the two 4-KByte blocks for updatable

parametric data storage diagnostic messages and

data or extensions of either the boot code or pro-

gram code The boot block is hardware protected

against unauthorized write or erase of its vital code

in the field Further the powerdown mode also locks

out erase or write operations providing absolute

data protection during system powerup or power

loss This hardware protection provides obvious ad-

vantages for safety related applications such as

transportation military and medical The 28F001BX

is well suited for minimum-chip embedded applica-

tions ranging from communications to automotive

290406 – 5

Figure 5 28F001BX-T in a 80C188 System

290406 – 6

Figure 6 28F001BX-B in a 80C51 System

28F001BX-T 28F001BX-B

PRINCIPLES OF OPERATION

The 28F001BX introduces on-chip write automation

to manage write and erase functions The write state

machine allows for 100% TTL-level control inputs

fixed power supplies during erasure and program-

ming minimal processor overhead with RAM-like

write timings and maximum EPROM compatiblity

After initial device powerup or after return from

deep powerdown mode (see Bus Operations) the

28F001BX functions as a read-only memory Manip-

ulation of external memory-control pins yield stan-

dard EPROM read standby output disable or Intelli-

gent Identifier operations Both Status Register and

Intelligent Identifiers can be accessed through the

Command Register when V

PPL

This same subset of operations is also available

when high voltage is applied to the V

pin In addi-

tion high voltage on V

enables successful erasure

and programming of the device All functions associ-

ated with

altering memory contents

program

erase status and inteligent Identifier are accessed

via the Command Register and verified through the

Status Register

Commands are written using standard microproces-

sor write timings Register contents serve as input to

the WSM which controls the erase and program-

ming circuitry Write cycles also internally latch ad-

dresses and data needed for programming or erase

operations With the appropriate command written to

the register standard microprocessor read timings

output array data access the intelligent identifier

codes or output program and erase status for verifi-

cation

Interface software to initiate and poll progress of in-

ternal program and erase can be stored in any of the

28F001BX blocks This code is copied to and exe-

cuted from system RAM during actual flash memory

update

After successful completion of program

and or erase code execution out of the 28F001BX

is again possible via the Read Array command

Erase suspend resume capability allows system

software to suspend block erase and read data exe-

cute code from any other block

Command Register and Write

Automation

An on-chip state machine controls block erase and

byte program freeing the system processor for other

tasks After receiving the erase setup and erase

confirm commands

the state machine controls

block pre-conditioning and erase returning progress

via the Status Register Programming is similarly

controlled after destination address and expected

data are supplied The program algorithm of past In-

tel Flash Memories is now regulated by the state

machine including program pulse repetition where

required and internal verification and margining of

data

Data Protection

Depending on the application the system designer

may choose to make the V

power supply switcha-

ble (available only when memory updates are re-

quired) or hardwired to V

PPH

When V

PPL

memory contents cannot be altered The 28F001BX

Command Register architecture provides protection

from unwanted program or erase operations even

when high voltage is applied to V

Additionally all

functions are disabled whenever V

is below the

write lockout voltage V

LKO

or when RP

is at V

The 28F001BX accommodates either design prac-

tice and encourages optimization of the processor-

memory interface

The two-step program erase write sequence to the

Command Register provides additional software

write protection

1FFFF

8-KByte BOOT BLOCK

1DFFF

1E000

4-KByte PARAMETER BLOCK

1CFFF

1D000

4-KByte PARAMETER BLOCK

1BFFF

1C000

112-KByte MAIN BLOCK

00000

Figure 7 28F001BX-T Memory Map

1FFFF

112-KByte MAIN BLOCK

03FFF

04000

4-KByte PARAMETER BLOCK

02FFF

03000

4-KByte PARAMETER BLOCK

01FFF

02000

8-KByte BOOT BLOCK

00000

Figure 8 28F001BX-B Memory Map

28F001BX-T 28F001BX-B

BUS OPERATION

Flash memory reads erases and writes in-system

via the local CPU All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles

Read

The 28F001BX has three read modes The memory

can be read from any of its blocks and information

can be read from the Intelligent Identifier or the

Status Register V

can be at either V

PPL

or V

PPH

The first task is to write the appropriate read mode

command to the Command Register (array Intelli-

gent Identifier or Status Register) The 28F001BX

automatically resets to Read Array mode upon initial

device powerup or after exit from deep powerdown

The 28F001BX has four control pins two of which

must be logically active to obtain data at the outputs

Chip Enable (CE ) is the device selection control

and when active enables the selected memory de-

vice Output Enable (OE ) is the data input output

(DQ

– DQ

) direction control

and when active

drives data from the selected memory onto the I O

bus RP

and WE

must also be at V

Figure 12

illustrates read bus cycle waveforms

Output Disable

With OE

at a logic-high level (V

) the device out-

puts are disabled

Output pins (DQ

– DQ

) are

placed in a high-impedance state

Standby

at a logic-high level (V

) places the 28F001BX

in standby mode Standby operation disables much

of the 28F001BX’s circuitry and substantially reduc-

es device power consumption The outputs (DQ

–

) are placed in a high-impedance state indepen-

dent of the status of OE

If the 28F001BX is dese-

lected during erase or program the device will

continue functioning and consuming normal active

power until the operation is completed

Deep Power-Down

The 28F001BX offers a 0 25 mW V

power-down

feature entered when RP

is at V

During read

modes RP

low deselects the memory places out-

put drivers in a high-impedance state and turns off

all internal circuits The 28F001BX requires time

PHQV

(see AC Characteristics-Read Only Opera-

tions) after return from power-down until initial mem-

ory access outputs are valid After this wakeup inter-

val normal operation is restored The Command

ister is cleared to value 80H upon return to normal

operation

During erase or program modes RP

low will abort

either operation Memory contents of the block be-

ing altered are no longer valid as the data will be

partially programmed or erased Time t

PHWL

after

goes to logic-high (V

) is required before an-

other command can be written

Table 2 28F001BX Bus Operations

Mode

Notes

0–7

Read

1 2 3

OUT

Output Disable

High Z

Standby

High Z

Deep Power Down

High Z

Intelligent Identifier (Mfr)

2 3 4

89H

Intelligent Identifier (Device)

2 3 4 5

94H 95H

Write

2 6 7 8

NOTES

1 Refer to DC Characteristics When V

PPL

memory contents can be read but not programmed or erased

2 X can be V

or V

for control pins and addresses and V

PPL

or V

PPH

for V

3 See DC Characteristics for V

PPL

PPH

and V

voltages

4 Manufacturer and device codes may also be accessed via a Command Register write sequence Refer to Table 3 A

– A

5 Device ID

94H for the 28F001BX-T and 95H for the 28F001BX-B

6 Command writes involving block erase or byte program are successfully executed only when V

PPH

7 Refer to Table 3 for valid D

during a write operation

8 Program or erase the boot block by holding RP

at V

or toggling OE

to V

See AC Waveforms for program erase

operations

28F001BX-T 28F001BX-B

The use of RP

during system reset is important

with automated write erase devices When the sys-

tem comes out of reset it expects to read from the

flash memory Automated flash memories provide

status information when accessed during write

erase modes If a CPU reset occurs with no flash

memory reset proper CPU initialization would not

occur because the flash memory would be providing

the status information instead of array data Intel’s

Flash Memories allow proper CPU initialization fol-

lowing a system reset through the use of the RP

input In this application RP

is controlled by the

same RESET

signal that resets the system CPU

Intelligent Identifier Operation

The Intelligent Identifier operation outputs the manu-

facturer code 89H and the device code 94H for the

28F001BX-T and 95H for the 28F001BX-B Pro-

gramming equipment or the system CPU can then

automatically match the device with its proper erase

and programming algorithms

PROGRAMMING EQUIPMENT

and OE

at a logic low level (V

) with A

high voltage V

(see DC Characteristics) activates

this operation Data read from locations 00000H and

00001H represent the manufacturer’s code and the

device code respectively

IN-SYSTEM PROGRAMMING

The manufacturer- and device-codes can also be

read via the Command Register Following a write of

90H to the Command Register a read from address

location 00000H outputs the manufacturer code

(89H) A read from address 00001H outputs the de-

vice code (94H for the 28F001BX-T and 95H for the

28F001BX-B) It is not necessary to have high volt-

age applied to V

to read the Intelligent Identifiers

from the Command Register

Write

Writes to the Command Register allow read of de-

vice data and Intelligent Identifiers They also con-

trol inspection and clearing of the Status Register

Additionally when V

PPH

the Command Reg-

ister controls device erasure and programming The

contents of the register serve as input to the internal

state machine

The Command Register itself does not occupy an

addressable memory location The register is a latch

used to store the command and address and data

information needed to execute the command Erase

Setup and Erase Confirm commands require both

appropriate command data and an address within

the block to be erased The Program Setup Com-

mand requires both appropriate command data and

the address of the location to be programmed while

the Program command consists of the data to be

written and the address of the location to be pro-

grammed

The Command Register is written by bringing WE

to a logic-low level (V

) while CE

is low Address-

es and data are latched on the rising edge of WE

Standard microprocessor write timings are used

Refer to AC Write Characteristics and the AC Wave-

form for Write Operations Figure 13 for specific tim-

ing parameters

COMMAND DEFINITIONS

When V

PPL

is applied to the V

pin read opera-

tions from the Status Register intelligent identifiers

or array blocks are enabled Placing V

PPH

on V

enables successful program and erase operations

as well

Device operations are selected by writing specific

commands into the Command Register Table 3 de-

fines these 28F001BX commands

Read Array Command

Upon initial device powerup and after exit from

deep-powerdown mode the 28F001BX defaults to

Read Array mode This operation is also initiated by

writing FFH into the Command Register Microproc-

essor read cycles retrieve array data The device re-

mains enabled for reads until the Command Regis-

ter contents are altered Once the internal write

state machine has started an erase or program op-

eration the device will not recognize the Read Array

command until the WSM has completed its opera-

tion The Read Array command is functional when

PPL

or V

PPH

Intelligent Identifier Command for

In-System Programming

The 28F001BX contains an Intelligent Identifier op-

eration to supplement traditional PROM-program-

ming methodology The operation is initiated by writ-

ing 90H into the Command Register Following the

command write a read cycle from address 00000H

retrieves the manufacturer code of 89H A read cy-

cle from address 00001H returns the device code of

94H (28F001BX-T) or 95H (28F001BX-B) To termi-

nate the operation it is necessary to write another

valid command into the register Like the Read Array

command the Intelligent Identifier command is func-

tional when V

PPL

or V

PPH

28F001BX-T 28F001BX-B

Table 3 28F001BX Command Definitions

Command

Cycles

Req’d

Bus

Notes

First Bus Cycle

Second Bus Cycle

Operation Address Data Operation Address Data

Read Array Reset

Write

FFH

Intelligent Identifier

2 3 4

Write

90H

Read

IID

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Erase Setup Erase Confirm

Write

20H

Write

D0H

Erase Suspend Erase Resume

Write

B0H

Write

D0H

Program Setup Program

2 3

Write

40H

Write

NOTES

1 Bus operations are defined in Table 2

2 IA

Identifier Address 00H for manufacturer code 01H for device code

Address within the block being erased

Address of memory location to be programmed

3 SRD

Data read from Status Register See Table 4 for a description of the Status Register bits

Data to be programmed at location PA Data is latched on the rising edge of WE

IID

Data read from Intelligent Identifiers

4 Following the Intelligent Identifier command two read operations access manufacture and device codes

5 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

Read Status Register Command

The 28F001BX contains a Status Register which

may be read to determine when a program or erase

operation is complete and whether that operation

completed successfully The Status Register may be

read at any time by writing the Read Status Register

command (70H) to the Command Register After

writing this command all subsequent read opera-

tions output data from the Status Register until an-

other valid command is written to the Command

latched on the falling edge of OE

or CE

which-

ever occurs last in the read cycle OE

or CE

must be toggled to V

before further reads to up-

date the Status Register latch The Read Status

PPL

PPH

Clear Status Register Command

The Erase Status and Program Status bits are set to

‘‘1’’ by the Write State Machine and can only be

reset by the Clear Status Register command These

bits indicate various failure conditions (see Table 4)

By allowing system software to control the resetting

of these bits several operations may be performed

(such as cumulatively programming several bytes or

erasing multiple blocks in sequence) The Status

occurred during that series This adds flexibility to

the way the device may be used

Additionally the V

Status bit (SR 3) when set to

‘‘1’’ MUST be reset by system software before fur-

ther byte programs or block erases are attempted

To clear the Status Register the Clear Status Regis-

ter command (50H) is written to the Command Reg-

ister The Clear Status Register command is func-

tional when V

PPL

or V

PPH