/home/techdatasheets.com/WWW/datasheets_html/207091/datasheet-PA28F200BX-T80

Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or

copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make

changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

November 1995

INTEL CORPORATION 1995

Order Number 290448-005

2-MBIT (128K x 16 256K x 8)

BOOT BLOCK

FLASH MEMORY FAMILY

28F200BX-T B 28F002BX-T B

x8 x16 Input Output Architecture

28F200BX-T 28F200BX-B

For High Performance and High

Integration 16-bit and 32-bit CPUs

x8-only Input Output Architecture

28F002BX-T 28F002BX-B

For Space Constrained 8-bit

Applications

Upgradeable to Intel’s SmartVoltage

Products

Optimized High-Density Blocked

Architecture

One 16-KB Protected Boot Block

Two 8-KB Parameter Blocks

One 96-KB Main Block

One 128 KB Main Block

Top or Bottom Boot Locations

Extended Cycling Capability

100 000 Block Erase Cycles

Automated Word Byte Write and

Block Erase

Command User Interface

Status Registers

Erase Suspend Capability

SRAM-Compatible Write Interface

Automatic Power Savings Feature

1 mA Typical I

Active Current in

Static Operation

Hardware Data Protection Feature

Erase Write Lockout during Power

Transitions

Very High-Performance Read

60 80 120 ns Maximum Access Time

30 40 40 ns Maximum Output Enable

Time

Low Power Consumption

20 mA Typical Active Read Current

Reset Deep Power-Down Input

0 2 mA I

Typical

Acts as Reset for Boot Operations

Extended Temperature Operation

40 C to

85 C

Write Protection for Boot Block

Industry Standard Surface Mount

Packaging

28F200BX JEDEC ROM Compatible

44-Lead PSOP

56-Lead TSOP

28F002BX 40-Lead TSOP

12V Word Byte Write and Block Erase

12V

5% Standard

12V

10% Option

ETOX

III Flash Technology

5V Read

Independent Software Vendor Support

28F200BX-T B 28F002BX-T B

Intel’s 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec-

tive erasure automated write and erase operations and standard microprocessor interface The 2-Mbit Flash

Memory Family enhances the Boot Block Architecture by adding more density and blocks x8 x16 input out-

put control very high speed low power an industry-standard ROM compatible pinout and surface mount

packaging The 2-Mbit flash family allows for an easy upgrade to Intel’s 4-Mbit Boot Block Flash Memory

Family

The Intel 28F200BX-T B are 16-bit wide flash memory offerings These high-density flash memories provide

user selectable bus operation for either 8-bit or 16-bit applications The 28F200BX-T and 28F200BX-B are

2 097 152-bit nonvolatile memories organized as either 262 144 bytes or 131 072 words of information They

are offered in 44-Lead plastic SOP and 56-Lead TSOP packages The x8 x16 pinout conforms to the industry-

standard ROM EPROM pinout

The Intel 28F002BX-T B are 8-bit wide flash memories with 2 097 152 bits organized as 262 144 bytes of

information They are offered in a 40-lead TSOP package which is ideal for space-constrained portable

systems

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified

word byte write and block erasure The 28F200BX-T 28F002BX-T provide block locations compatible with

Intel’s MCS -186 family 80286 i386

i486

i860

and 80960CA microprocessors The 28F200BX-B

28F002BX-B provide compatibility with Intel’s 80960KX and 80960SX families as well as other embedded

microprocessors

The boot block includes a data protection feature to protect the boot code in critical applications With a

maximum access time of 60 ns these 2-Mbit flash devices are very high-performance memories which inter-

face at zero wait-state to a wide range of microprocessors and microcontrollers A deep power-down mode

lowers the total V

power consumption to 1 mW typical This is critical in handheld battery-powered systems

For very low-power applications using a 3 3V supply refer to the Intel 28F200BX-TL BL 28F002BX-TL BL

2-Mbit Boot Block Flash Memory Family datasheet

Manufactured on Intel’s 0 8 micron ETOX III process the 2-Mbit flash memory family provides world-class

quality reliability and cost-effectiveness at the 2-Mbit density level

28F200BX-T B 28F002BX-T B

1 0

PRODUCT FAMILY OVERVIEW

Throughout this datasheet the 28F200BX refers to

both the 28F200BX-T and 28F200BX-B devices and

28F002BX refers to both the 28F002BX-T and

28F002BX-B devices The 2-Mbit flash memory fam-

ily refers to both the 28F200BX and 28F002BX prod-

ucts This datasheet comprises the specifications for

four separate products in the 2-Mbit flash memory

family Section 1 provides an overview of the 2-Mbit

flash memory family including applications pinouts

and pin descriptions Sections 2 and 3 describe in

detail the specific memory organizations for the

28F200BX and 28F002BX products respectively

Section 4 combines a description of the family’s

principles of operations Finally Section 5 describes

the family’s operating specifications

PRODUCT FAMILY

x8 x16 Products

x8-Only Products

28F200BX-T

28F002BX-T

28F200BX-B

28F002BX-B

1 1 Designing for Upgrade to

SmartVoltage Products

Today’s high volume boot block products are up-

gradable to Intel’s SmartVoltage boot block prod-

ucts that provide program and erase operation at 5V

or 12V V

and read operation at 3V or 5V V

Intel’s SmartVoltage boot block products provide the

following enhancements to the boot block products

described in this data sheet

1 DU pin is replaced by WP

to provide a means

to lock and unlock the boot block with logic sig-

nals

2 5V Program Erase operation uses proven pro-

gram and erase techniques with 5V

10% ap-

plied to VPP

3 Enhanced circuits optimize performance at 3 3V

Refer to the 2 4 or 8 Mbit SmartVoltage Boot Block

Flash Memory Data Sheets for complete specifica-

tions

When you design with 12V V

boot block products

you should provide the capability in your board de-

sign to upgrade to SmartVoltage products

Follow these guidelines to ensure compatibility

1 Connect DU (WP

on SmartVoltage products) to

a control signal or to V

or GND

2 If adding a switch on V

for write protection

switch to GND for complete write protection

3 Allow for connecting 5V to V

and disconnect

12V from the V

line if desired

1 2 Main Features

The 28F200BX 28F002BX boot block flash memory

family is a very high performance 2-Mbit (2 097 152

bit) memory family organized as either 128 KWords

(131 072 words) of 16 bits each or 256 Kbytes

(262 144 bytes) of 8 bits each

Five Separately Erasable Blocks

including a hard-

ware-lockable boot block

(16 384 Bytes) two pa-

rameter blocks

(8 192 Bytes each) and two main

blocks

(1 block of 98 304 Bytes and 1 block of

131 072 Bytes) are included on the 2-Mbit family An

erase operation erases one of the main blocks in

typically 2 4 seconds and the boot or parameter

blocks in typically 1 0 second Each block can be

independently erased and programmed 100 000

times

The Boot Block

is located at either the top

(28F200BX-T

28F002BX-T)

the

bottom

(28F200BX-B 28F002BX-B) of the address map in

order to accommodate different microprocessor pro-

tocols for boot code location The hardware locka-

ble boot block

provides the most secure code stor-

age The boot block is intended to store the kernel

code required for booting-up a system When the

pin is between 11 4V and 12 6V the boot block

is unlocked and program and erase operations can

be performed When the RP

pin is at or below 6 5V

the boot block is locked and program and erase op-

erations to the boot block are ignored

The 28F200BX products are available in the ROM

EPROM compatible pinout and housed in the 44-

Lead PSOP (Plastic Small Outline) package and the

56-Lead TSOP (Thin Small Outline 1 2mm thick)

package as shown in Figures 3 and 4

The

28F002BX products are available in the 40-Lead

TSOP (1 2mm thick) package as shown in Figure 5

The Command User Interface (CUI) serves as the

interface between the microprocessor or microcon-

troller and the internal operation of the 28F200BX

and 28F002BX flash memory products

Program and Erase Automation

allows program

and erase operations to be executed using a two-

write command sequence to the CUI The internal

Write State Machine (WSM) automatically executes

the algorithms and timings necessary for program

and erase operations including verifications there-

by unburdening the microprocessor or microcontrol-

ler Writing of memory data is performed in word or

byte increments for the 28F200BX family and in byte

increments for the 28F002BX family typically within

9 ms which is a 100% improvement over current

flash memory products

28F200BX-T B 28F002BX-T B

The Status Register (SR) indicates the status of the

WSM and whether the WSM successfully completed

the desired program or erase operation

Maximum Access Time of 60 ns (t

ACC

)

is achieved

over the commercial temperature range (0 C to

70 C) 5% V

supply voltage range (4 75V to

5 25V) and 30 pF output load Refer to Figure 19

ACC

vs Output Load Capacitance for larger output

loads Maximum Access Time of 80 ns (t

ACC

)

achieved over the commercial temperature range

10% V

supply range (4 5V to 5 5V) and 100 pF

output load

maximum Program current is 40 mA for x16

operation and 30 mA for x8 operation I

Erase

current is 30 mA maximum V

erase and pro-

gramming voltage is 11 4V to 12 6V (V

12V

5%) under all operating conditions

As an op-

tion V

can also vary between 10 8V to 13 2V (V

12V

10%) with a guaranteed number of 100

block erase cycles

Typical I

Active Current of 25 mA

is achieved

for the x16 products (28F200BX) typical I

Active

Current of 20 mA

is achieved for the x8 products

(28F200BX 28F002BX) Refer to the I

active cur-

rent derating curves in this datasheet

The 2-Mbit boot block flash family is also designed

with an Automatic Power Savings (APS) feature to

minimize system battery current drain and allow for

very low power designs Once the device is ac-

cessed to read array data APS mode will immedi-

ately put the memory in static mode of operation

where I

active current is typically 1 mA until the

next read is initiated

When the CE

and RP

pins are at V

and the

BYTE

pin (28F200BX-only) is at either V

GND the CMOS Standby mode is enabled where

is typically 50 mA

A Deep Power-Down Mode is enabled when the

pin is at ground minimizing power consumption

and providing write protection during power-up con-

ditions I

current

during deep power-down mode

is 0 20 mA typical An initial maximum access time

or Reset Time of 300 ns is required from RP

switching until outputs are valid Equivalently the

device has a maximum wake-up time of 215 ns until

writes to the Command User Interface are recog-

nized When RP

is at ground the WSM is reset the

Status Register is cleared and the entire device is

protected from being written to This feature pre-

vents data corruption and protects the code stored

in the device during system reset The system Reset

pin can be tied to RP

to reset the memory to nor-

mal read mode upon activation of the Reset pin

With on-chip program erase automation in the

2-Mbit family and the RP

functionality for data pro-

tection when the CPU is reset and even if a program

or erase command is issued the device will not rec-

ognize any operation until RP

returns to its normal

state

For the 28F200BX Byte-wide or Word-wide In-

put Output Control

is possible by controlling the

BYTE

pin When the BYTE

pin is at a logic low

the device is in the byte-wide mode (x8) and data is

read and written through DQ 0 7

During the byte-

wide mode DQ 8 14 are tri-stated and DQ15 Ab1

becomes the lowest order address pin When the

BYTE

pin is at a logic high the device is in the

word-wide mode (x16) and data is read and written

through DQ 0 15

1 3 Applications

The 2-Mbit boot block flash family combines high

density high performance cost-effective flash mem-

ories with blocking and hardware protection capabili-

ties Its flexibility and versatility will reduce costs

throughout the product life cycle Flash memory is

ideal for Just-In-Time production flow reducing sys-

tem inventory and costs and eliminating component

handling during the production phase During the

product life cycle when code updates or feature en-

hancements become necessary flash memory will

reduce the update costs by allowing either a user-

performed code change via floppy disk or a remote

code change via a serial link The 2-Mbit boot block

flash family provides full function blocked flash

memories suitable for a wide range of applications

These applications include Extended PC BIOS

Digital Cellular Phone

program and data storage

Telecommunication

boot firmware

and various

other embedded applications where both program

and data storage are required

Reprogrammable systems such as personal com-

puters are ideal applications for the 2-Mbit flash

products Portable and handheld personal computer

applications are becoming more complex with the

addition of power management software to take ad-

vantage of the latest microprocessor technology

the availability of ROM-based application software

pen tablet code for electronic hand writing and diag-

nostic code

Figure 1 shows an example of a

28F200BX-T application

This increase in software sophistication augments

the probability that a code update will be required

after the PC is shipped The 2-Mbit flash products

provide an inexpensive update solution for the note-

book and handheld personal computers while ex-

tending their product lifetime

Furthermore

the

2-Mbit flash products’ power-down mode provides

added flexibility for these battery-operated portable

designs which require operation at very low power

levels

28F200BX-T B 28F002BX-T B

The 2-Mbit flash products also provide excellent de-

sign solutions for Digital Cellular Phone and Tele-

communication switching applications requiring high

performance high density storage capability cou-

pled with modular software designs and a small

form factor package (x8-only bus) The 2-Mbit’s

blocking scheme allows for an easy segmentation of

the embedded code with 16 Kbytes of Hardware-

Protected Boot code 2 Main Blocks of program

code and 2 Parameter Blocks of 8 Kbytes each for

frequently updatable data storage and diagnostic

messages

(e g

phone

numbers

authorization

codes) Figure 2 is an example of such an applica-

tion with the 28F002BX-T

These are a few actual examples of the wide range

of applications for the 2-Mbit Boot Block flash mem-

ory family which enable system designers to achieve

the best possible product design Only your imagina-

tion limits the applicability of such a versatile product

family

290448 – 4

Figure 1 28F200BX Interface to Intel386

EX Embedded Processor

290448 – 24

Figure 2 28F002BX Interface to INTEL 80C188EB 8-Bit Embedded Microprocessor

28F200BX-T B 28F002BX-T B

1 5 Pin Descriptions for the x8 x16 28F200BX

Symbol

Type

Name and Function

– A

ADDRESS INPUTS

for memory addresses Addresses are internally latched

during a write cycle

ADDRESS INPUT

When A

is at 12V the signature mode is accessed During this

mode A

decodes between the manufacturer and device ID’s When BYTE

is at

a logic low only the lower byte of the signatures are read DQ

is a don’t

care in the signature mode when BYTE

is low

– DQ

I O

DATA INPUTS OUTPUTS

Inputs array data on the second CE

and WE

cycle

during a program command Inputs commands to the Command User Interface

when CE

and WE

are active Data is internally latched during the write and

program cycles Outputs array Intelligent Identifier and Status Register data The

data pins float to tri-state when the chip is deselected or the outputs are disabled

– DQ

I O

DATA INPUTS OUTPUTS

Inputs array data on the second CE

and WE

cycle

during a program command Data is internally latched during the write and program

cycles Outputs array data The data pins float to tri-state when the chip is

deselected or the outputs are disabled as in the byte-wide mode (BYTE

‘‘0’’)

In the byte-wide mode DQ

becomes the lowest order address for data

output on DQ

– DQ

CHIP ENABLE

Activates the device’s control logic input buffers decoders and

sense amplifiers CE

is active low CE

high deselects the memory device and

reduces power consumption to standby levels If CE

and RP

are high but not

at a CMOS high level the standby current will increase due to current flow through

the CE

and RP

input stages

RESET DEEP POWER-DOWN

Provides three-state control Puts the device in

deep power-down mode Locks the boot block from program erase

When RP

is at logic high level and equals 6 5V maximum the boot block is

locked and cannot be programmed or erased

When RP

11 4V minimum the boot block is unlocked and can be programmed

or erased

When RP

is at a logic low level the boot block is locked the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being

programmed or erased therefore providing data protection during power

transitions When RP

transitions from logic low to logic high the flash memory

enters the read array mode

OUTPUT ENABLE

Gates the device’s outputs through the data buffers during a

read cycle OE

is active low

WRITE ENABLE

Controls writes to the Command Register and array blocks

is active low Addresses and data are latched on the rising edge of the WE

pulse

BYTE

ENABLE

Controls whether the device operates in the byte-wide mode

(x8) or the word-wide mode (x16) BYTE

pin must be controlled at CMOS levels

to meet 100 mA CMOS current in the standby mode BYTE

‘‘0’’ enables the

byte-wide mode where data is read and programmed on DQ

– DQ

and

becomes the lowest order address that decodes between the upper

and lower byte DQ

– DQ

are tri-stated during the byte-wide mode

BYTE

‘‘1’’ enables the word-wide mode where data is read and programmed

on DQ

– DQ

PROGRAM ERASE POWER SUPPLY

For erasing memory array blocks or

programming data in each block

Note

PPLMAX

memory contents cannot be altered

DEVICE POWER SUPPLY (5V

10% 5V

5%)

GND

GROUND

For all internal circuitry

NO CONNECT

Pin may be driven or left floating

DON’T USE PIN

Pin should not be connected to anything

28F200BX-T B 28F002BX-T B

1 6 Pin Descriptions for x8 28F002BX

Symbol

Type

Name and Function

– A

ADDRESS INPUTS

for memory addresses Addresses are internally latched during

a write cycle

ADDRESS INPUT

When A

is at 12V the signature mode is accessed During this

mode A

decodes between the manufacturer and device ID’s

– DQ

I O

DATA INPUTS OUTPUTS

Inputs array data on the second CE

and WE

cycle

during a program command Inputs commands to the command user interface

when CE

and WE

are active Data is internally latched during the write and

program cycles Outputs array Intelligent Identifier and status register data The

data pins float to tri-state when the chip is deselected or the outputs are disabled

CHIP ENABLE

Activates the device’s control logic input buffers decoders and

sense amplifiers CE

is active low CE

high deselects the memory device and

reduces power consumption to standby levels If CE

and RP

are high but not at

a CMOS high level the standby current will increase due to current flow through the

and RP

input stages

RESET DEEP POWERDOWN

Provides Three-State control Puts the device in

deep powerdown mode Locks the Boot Block from program erase

When RP

is at logic high level and equals 6 5V maximum the Boot Block is locked

and cannot be programmed or erased

When RP

11 4V minimum the Boot Block is unlocked and can be programmed

or erased

When RP

is at a logic low level the Boot Block is locked the deep powerdown

mode is enabled and the WSM is reset preventing any blocks from being

programmed or erased therefore providing data protection during power

transitions When RP

transitions from logic low to logic high the flash memory

enters the read-array mode

OUTPUT ENABLE

Gates the device’s outputs through the data buffers during a

read cycle OE

is active low

WRITE ENABLE

Controls writes to the Command Register and array blocks WE

is active low Addresses and data are latched on the rising edge of the WE

pulse

PROGRAM ERASE POWER SUPPLY

For erasing memory array blocks or

programming data in each block

Note

PPLMAX

memory contents cannot be altered

DEVICE POWER SUPPLY (5V

10% 5V

5%)

GND

GROUND

For all internal circuitry

NO CONNECT

Pin may be driven or left floating

DON’T USE PIN

Pin should not be connected to anything

28F200BX-T B 28F002BX-T B

2 1 28F200BX Memory Organization

2 1 1 BLOCKING

The 28F200BX uses a blocked array architecture to

provide independent erasure of memory blocks A

block is erased independently of other blocks in the

array when an address is given within the block ad-

dress range and the Erase Setup and Erase Confirm

commands are written to the CUI The 28F200BX is

a random read write memory only erasure is per-

formed by block

2 1 1 1 Boot Block Operation and Data

Protection

The 16-Kbyte boot block provides a lock feature for

secure code storage The intent of the boot block is

to provide a secure storage area for the kernel code

that is required to boot a system in the event of pow-

er failure or other disruption during code update

This lock feature ensures absolute data integrity by

preventing the boot block from being written or

erased when RP

is not at 12V The boot block can

be erased and written when RP

is held at 12V for

the duration of the erase or program operation This

allows customers to change the boot code when

necessary while providing security when needed

See the Block Memory Map section for address

locations of the boot block for the 28F200BX-T

and 28F200BX-B

2 1 1 2 Parameter Block Operation

The 28F200BX has 2 parameter blocks (8 Kbytes

each) The parameter blocks are intended to provide

storage for frequently updated system parameters

and configuration or diagnostic information The pa-

rameter blocks can also be used to store additional

boot or main code The parameter blocks however

do not have the hardware write protection feature

that the boot block has The parameter blocks pro-

vide for more efficient memory utilization when deal-

ing with parameter changes versus regularly blocked

devices See the Block Memory Map section for ad-

dress locations of the parameter blocks for the

28F200BX-T and 28F200BX-B

2 1 1 3 Main Block Operation

Two main blocks of memory exist on the 28F200BX

(1 x 128 Kbyte block and 1 x 96-Kbyte block) See

the following section on Block Memory Map for the

address location of these blocks for the 28F200BX-T

and 28F200BX-B products

2 1 2 BLOCK MEMORY MAP

Two versions of the 28F200BX product exist to sup-

port two different memory maps of the array blocks

in order to accommodate different microprocessor

protocols for boot code location The 28F200BX-T

memory map is inverted from the 28F200BX-B

memory map

2 1 2 1 28F200BX-B Memory Map

The 28F200BX-B device has the 16-Kbyte boot

block located from 00000H to 01FFFH to accommo-

date those microprocessors that boot from the bot-

tom of the address map at 00000H

In the

28F200BX-B the first 8-Kbyte parameter block re-

sides in memory space from 02000H to 02FFFH

The second 8-Kbyte parameter block resides in

memory space from 03000H to 03FFFH

The

96-Kbyte main block resides in memory space from

04000H to 0FFFFH The 128-Kbyte main block re-

sides in memory space from 10000H to 1FFFFH

(word locations) See Figure 7

(Word Addresses)

1FFFFH

128-Kbyte MAIN BLOCK

0FFFFH

10000H

96-Kbyte MAIN BLOCK

03FFFH

04000H

8-Kbyte PARAMETER BLOCK

02FFFH

03000H

8-Kbyte PARAMETER BLOCK

01FFFH

02000H

16-Kbyte BOOT BLOCK

00000H

Figure 7 28F200BX-B Memory Map

28F200BX-T B 28F002BX-T B

3 1 28F002BX Memory Organization

3 1 1 BLOCKING

The 28F002BX uses a blocked array architecture to

provide independent erasure of memory blocks A

block is erased independently of other blocks in the

array when an address is given within the block ad-

dress range and the Erase Setup and Erase Confirm

commands are written to the CUI The 28F002BX is

a random read write memory only erasure is per-

formed by block

3 1 1 1 Boot Block Operation and Data

Protection

The 16-Kbyte boot block provides a lock feature for

secure code storage The intent of the boot block is

to provide a secure storage area for the kernel code

that is required to boot a system in the event of pow-

er failure or other disruption during code update

This lock feature ensures absolute data integrity by

preventing the boot block from being programmed

or erased when RP

is not at 12V The boot block

can be erased and programmed when RP

is held

at 12V for the duration of the erase or program oper-

ation This allows customers to change the boot

code when necessary while still providing security

when needed See the Block Memory Map section

for address locations of the boot block for the

28F002BX-T and 28F002BX-B

3 1 1 2 Parameter Block Operation

The 28F002BX has 2 parameter blocks (8 Kbytes

each) The parameter blocks are intended to provide

storage for frequently updated system parameters

and configuration or diagnostic information The pa-

rameter blocks can also be used to store additional

boot or main code The parameter blocks however

do not have the hardware write protection feature

that the boot block has Parameter blocks provide

for more efficient memory utilization when dealing

with small parameter changes versus regularly

blocked devices See the Block Memory Map sec-

tion for address locations of the parameter blocks

for the 28F002BX-T and 28F002BX-B

3 1 1 3 Main Block Operation

Two main blocks of memory exist on the 28F002BX

(1 x 128-Kbyte block and 1 x 96-Kbyte block) See

the following section on Block Memory Map for

address

location

these

blocks

for

the

28F002BX-T and 28F002BX-B

3 1 2 BLOCK MEMORY MAP

Two versions of the 28F002BX product exist to sup-

port two different memory maps of the array blocks

in order to accommodate different microprocessor

protocols for boot code location The 28F002BX-T

memory map is inverted from the 28F002BX-B

memory map

3 1 2 1 28F002BX-B Memory Map

The 28F002BX-B device has the 16-Kbyte boot

block located from 00000H to 03FFFH to accommo-

date those microprocessors that boot from the bot-

tom of the address map at 00000H

In the

28F002BX-B the first 8-Kbyte parameter block re-

sides in memory from 04000H to 05FFFH The sec-

ond 8-Kbyte parameter block resides in memory

space from 06000H to 07FFFH The 96-Kbyte main

block resides in memory space from 08000H to

1FFFFH The 128-Kbyte main block resides in mem-

ory space from 20000H to 3FFFFH See Figure 10

3FFFFH

128-Kbyte MAIN BLOCK

1FFFFH

20000H

96-Kbyte MAIN BLOCK

07FFFH

08000H

8-Kbyte PARAMETER BLOCK

05FFFH

06000H

8-Kbyte PARAMETER BLOCK

03FFFH

04000H

16-Kbyte BOOT BLOCK

00000H

Figure 10 28F002BX-B Memory Map