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PRELIMINARY

July 1997

Order Number: 290530-005

Intel SmartVoltage Technology



5V or 12V Program/Erase



2.7V, 3.3V or 5V Read Operation



Increased Programming Throughput

at 12V V

Very High-Performance Read



5V: 60/80/120 ns Max. Access Time,

30/40 ns Max. Output Enable Time



3V: 110/150/180 ns Max Access

65/90 ns Max. Output Enable Time



2.7V: 120 ns Max Access 65 ns Max.

Output Enable Time

Low Power Consumption



Max 60 mA Read Current at 5V



Max 30 mA Read Current at

2.7V–3.6V

x8/x16-Selectable Input/Output Bus



28F400 for High Performance 16- or

32-bit CPUs

x8-Only Input/Output Architecture



28F004B for Space-Constrained

8-bit Applications

Optimized Array Blocking Architecture



One 16-KB Protected Boot Block



Two 8-KB Parameter Blocks



One 96-KB Main Block



Three 128-KB Main Blocks



Top or Bottom Boot Locations

Absolute Hardware-Protection for Boot

Block

Software EEPROM Emulation with

Parameter Blocks

Extended Temperature Operation



–40°C to +85°C

Extended Cycling Capability



100,000 Block Erase Cycles

(Commercial Temperature)



10,000 Block Erase Cycles

(Extended Temperature)

Automated Word/Byte Program and

Block Erase



Industry-Standard Command User

Interface



Status Registers



Erase Suspend Capability

SRAM-Compatible Write Interface

Automatic Power Savings Feature



1 mA Typical I

Active Current in

Static Operation

Reset/Deep Power-Down Input



0.2 µA I

Typical



Provides Reset for Boot Operations

Hardware Data Protection Feature



Write Lockout during Power

Transitions

Industry-Standard Surface Mount

Packaging



40-Lead TSOP



44-Lead PSOP: JEDEC ROM

Compatible



48-Lead TSOP



56-Lead TSOP

Footprint Upgradeable from 2-Mbit and

to 8-Mbit Boot Block Flash Memories

ETOX™ IV Flash Technology

4-MBIT (256K X 16, 512K X 8)

SmartVoltage BOOT BLOCK FLASH

MEMORY FAMILY

28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B

28F400CE-T/B, 28F004BE-T/B

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B may contain design defects or errors

known as errata which may cause the product to deviate from published specifications. Current characterized errata are

available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s Website at http:\\www.intel.com

CG-041493

Third-party brands and names are the property of their respective owners.

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

CONTENTS

PAGE

1.0 PRODUCT FAMILY OVERVIEW .................... 5

1.1 New Features in the SmartVoltage

Products ..................................................... 5

1.2 Main Features.............................................. 5

1.3 Applications ................................................. 7

1.4 Pinouts......................................................... 7

1.5 Pin Descriptions ......................................... 11

2.0 PRODUCT DESCRIPTION............................ 13

2.1 Memory Blocking Organization .................. 13

2.1.1 Boot Block........................................... 13

2.1.2 Parameter Blocks................................ 13

2.1.3 Main Blocks......................................... 13

3.0 PRODUCT FAMILY PRINCIPLES OF

OPERATION ................................................ 15

3.1 Bus Operations .......................................... 15

3.2 Read Operations........................................ 15

3.2.1 Read Array.......................................... 15

3.2.2 Intelligent Identifiers ............................ 17

3.3 Write Operations ........................................ 17

3.3.1 Command User Interface (CUI) ........... 17

3.3.2 Status Register ................................... 20

3.3.3 Program Mode .................................... 21

3.3.4 Erase Mode......................................... 21

3.4 Boot Block Locking .................................... 22

3.4.1 V

= V

for Complete Protection ....... 22

3.4.2 WP# = V

for Boot Block Locking ....... 22

3.4.3 RP# = V

or WP# = V

forr Boot Block

Unlocking ........................................... 22

3.4.4 Upgrade Note for 8-Mbit 44-PSOP

Package............................................. 22

3.5 Power Consumption................................... 26

3.5.1 Active Power ....................................... 26

3.5.2 Automatic Power Savings (APS) ......... 26

3.5.3 Standby Power .................................... 26

3.5.4 Deep Power-Down Mode..................... 26

3.6 Power-Up/Down Operation......................... 26

3.6.1 RP# Connected to System Reset ........ 26

3.6.2 V

, V

and RP# Transitions ............. 27

3.7 Power Supply Decoupling .......................... 27

3.7.1 V

Trace on Printed Circuit Boards.... 27

4.0 ABSOLUTE MAXIMUM RATINGS................ 28

5.0 COMMERCIAL OPERATING CONDITIONS . 29

5.1 Applying V

Voltages ............................... 29

5.2 DC Characteristics ..................................... 30

5.3 AC Characteristics ..................................... 34

6.0 EXTENDED OPERATING CONDITIONS ...... 44

6.1 Applying V

Voltages ............................... 44

6.2 DC Characteristics ..................................... 45

6.3 AC Characteristics ..................................... 51

APENDIX A: Additional Information ................. 56

APPENDIX B: Additional Information............... 57

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

REVISION HISTORY

Number

Description

-001

Initial release of datasheet.

-002

Status changed from Product Preview to Preliminary

28F400CV/CE/BE references and information added throughout.

2.7V CE/BE specs added throughout.

The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,

3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.

Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.

Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.

Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.

Sections 5.1, 6.1 changed to “Applying V

Voltages.” These sections completely

changed to clarify V

ramp requirements.

PPD

3.3V Commercial spec changed from 10 to 5

Capacitance tables added after commercial and extended DC Characteristics tables.

Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.

Test configuration drawings (Fig. 14, 22) consolidated into one, with component

values in table. (Component values also rounded off).

ELFL

, t

ELFH

, t

AVFL

changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V

TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial.

WHAX

and t

EHAX

changed from 10 to 0 ns.

PHWL

changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial.

PHEL

changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial.

-003

28F400BE row removed from Table 1

Applying V

voltages (Sections 5.1 and 6.1) rewritten for clarity.

Minor cosmetic changes/edits.

-004

Corrections: Spec typographical error “t

QWL

” corrected to read “t

QVVL

.”

Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU

specs require less glue logic.

Spec t

ELFL

and t

ELFH

changed from 5 ns (max) to 0 ns (min).

New specs t

PLPH

and t

PLQX

added from Specification Update document (297595).

Specs t

EHQZ

and t

GHQZ

improved on most voltage/speed combinations.

-005

Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80

to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80.

Updated disclaimer.

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

1.0

PRODUCT FAMILY OVERVIEW

This datasheet contains the specifications for the

two branches of products in the SmartVoltage

4-Mbit boot block flash memory family: the -BE/CE

suffix products feature a low V

operating range

of 2.7V–3.6V; the -BV/CV suffix products offer

3.0V–3.6V operation. Both BE/CE and BV/CV

products also operate at 5V for high-speed access

times. Throughout this datasheet, the 28F400

refers to all x8/x16 4-Mbit products, while

28F004B refers to all x8 4-Mbit boot block

products. Also, the term “2.7V” generally refers to

the full voltage range 2.7V–3.6V. Section 1

provides an overview of the flash memory family

including applications, pinouts and pin

descriptions. Sections 2 and 3 describe the

memory organization and operation for these

products. Finally, Sections 4 and 5 contain the

family’s operating specifications.

1.1

New Features in the

SmartVoltage Products

The SmartVoltage boot block flash memory family

offers identical operation with the BX/BL 12V

program products, except for the differences listed

below. All other functions are equivalent to current

products, including signatures, write commands,

and pinouts.

•

WP# pin has replaced a DU (Don’t Use) pin.

Connect the WP# pin to control signal or to

or GND (in this case, a logic-level signal

can be placed on DU pin). See Tables 2 and

9 to see how the WP# pin works.

•

5V program/erase operation has been added.

If switching V

for write protection, switch to

GND (not 5V) for complete write protection. To

take advantage of 5V write-capability, allow for

connecting 5V to V

and disconnecting 12V

from V

line.

•

Enhanced circuits optimize low V

performance, allowing operation down to

= 2.7V (using the BE product).

If you are using BX/BL 12V V

boot block

products today, you should account for the

differences listed above and also allow for

connecting 5V to V

and disconnecting 12V from

line, if 5V writes are desired.

1.2

Main Features

Intel’s SmartVoltage technology is the most

flexible voltage solution in the flash industry,

providing two discrete voltage supply pins: V

for

read operation, and V

for program and erase

operation. Discrete supply pins allow system

designers to use the optimal voltage levels for

their design. The 28F400BV/CV, 28F004BV,

28F400CE and 28F004BE provide program/erase

capability at 5V or 12V. The 28F400BV/CV and

28F004BV allow reads with V

at 3.3

0.3V or

5V, while the 28F400CE and 28F004BE allow

reads with V

at 2.7V–3.6V or 5V. Since many

designs read from the flash memory a large

percentage of the time, read operation using the

2.7V or 3.3V ranges can provide great power

savings. If read performance is an issue, however,

5V V

provides faster read access times.

Table 1. SmartVoltage Provides Total Voltage Flexibility

Product

Bus

Name

Width

2.7V–3.6V

3.3

0.3V

10%

12V

28F004BV-T/B

√

28F400BV-T/B

x8 or x16

√

28F400CV-T/B

x8 or x16

√

28F004BE-T/B

√

28F400CE-T/B

x8 or x16

√

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

For program and erase operations, 5V V

operation eliminates the need for in system voltage

converters, while 12V V

operation provides faster

program and erase for situations where 12V is

available, such as manufacturing or designs where

12V is in-system. For design simplicity, however,

just hook up V

and V

to the same 5V ± 10%

source.

The 28F400/28F004B boot block flash memory

family is a high-performance, 4-Mbit (4,194,304 bit)

flash memory family organized as either

256 Kwords of 16 bits each (28F400 only) or

512 Kbytes of 8 bits each (28F400 and 28F004B).

Separately erasable blocks, including a hardware-

lockable boot block (16,384 bytes), two parameter

blocks (8,192 bytes each) and main blocks (one

block of 98,304 bytes and three blocks of 131,072

bytes), define the boot block flash family

architecture. See Figures 7 and 8 for memory

maps. Each block can be independently erased and

programmed 100,000 times at commercial

temperature or 10,000 times at extended

temperature.

The boot block is located at either the top (denoted

by -T suffix) or the bottom (-B suffix) of the address

map in order to accommodate different

microprocessor protocols for boot code location.

The hardware-lockable boot block provides

complete code security for the kernel code required

for system initialization. Locking and unlocking of

the boot block is controlled by WP# and/or RP#

(see Section 3.4 for details).

The Command User Interface (CUI) serves as the

interface between the microprocessor or

microcontroller and the internal operation of the

boot block flash memory products. The internal

Write State Machine (WSM) automatically executes

the algorithms and timings necessary for program

and erase operations, including verifications,

thereby unburdening the microprocessor or

microcontroller of these tasks. The Status Register

(SR) indicates the status of the WSM and whether it

successfully completed the desired program or

erase operation.

Program and Erase Automation allows program and

erase operations to be executed using an industry-

standard two-write command sequence to the CUI.

Data writes are performed in word (28F400 family)

or byte (28F400 or 28F004B families) increments.

Each byte or word in the flash memory can be

programmed independently of other memory

locations, unlike erases, which erase all locations

within a block simultaneously.

The 4-Mbit SmartVoltage boot block flash memory

family is also designed with an Automatic Power

Savings (APS) feature which minimizes system

battery current drain, allowing for very low power

designs. To provide even greater power savings,

the boot block family includes a deep power-down

mode which minimizes power consumption by

turning most of the flash memory’s circuitry off.

This mode is controlled by the RP# pin and its

usage is discussed in Section 3.5, along with other

power consumption issues.

Additionally, the RP# pin provides protection

against unwanted command writes due to invalid

system bus conditions that may occur during

system reset and power-up/down sequences. For

example, when the flash memory powers-up, it

automatically defaults to the read array mode, but

during a warm system reset, where power

continues uninterrupted to the system components,

the flash memory could remain in a non-read mode,

such as erase. Consequently, the system Reset

signal should be tied to RP# to reset the memory to

normal read mode upon activation of the Reset

signal. See Section 3.6.

The 28F400 provides both byte-wide or word-wide

input/output, which is controlled by the BYTE# pin.

Please see Table 2 and Figure 16 for a detailed

description of BYTE# operations, especially the

usage of the DQ

–1

pin.

The 28F400 products are available in a

ROM/EPROM-compatible pinout and housed in the

44-lead PSOP (Plastic Small Outline) package, the

48-lead TSOP (Thin Small Outline, 1.2 mm thick)

package and the 56-lead TSOP as shown in

Figures

4, 5 and

6, respectively. The 28F004

products are available in the 40-lead TSOP

package as shown in Figure 3.

Refer to the DC Characteristics Table, Section 5.2

(commercial temperature) and Section 6.2

(extended temperature), for complete current and

voltage specifications. Refer to the AC

Characteristics Table, Section 5.3 (commercial

temperature) and Section 6.3 (extended

temperature), for read, write and erase performance

specifications.

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

1.3

Applications

The 4-Mbit boot block flash memory family

combines high-density, low-power, high-

performance, cost-effective flash memories with

blocking and hardware protection capabilities. Their

flexibility and versatility reduce costs throughout the

product life cycle. Flash memory is ideal for Just-In-

Time production flow, reducing system inventory

and costs, and eliminating component handling

during the production phase.

When your product is in the end-user’s hands, and

updates or feature enhancements become

necessary, flash memory reduces the update costs

by allowing user-performed code changes instead

of costly product returns or technician calls.

The 4-Mbit boot block flash memory family provides

full-function, blocked flash memories suitable for a

wide range of applications. These applications

include extended PC BIOS and ROM-able

applications storage, digital cellular phone program

and data storage, telecommunication boot/firmware,

printer firmware/font storage and various other

embedded applications where program and data

storage are required.

Reprogrammable systems, such as personal

computers, are ideal applications for the 4-Mbit

flash memory products. Increasing software

sophistication greatens the probability that a code

update will be required after the PC is shipped. For

example, the emerging of “plug and play” standard

in desktop and portable PCs enables auto-

configuration of ISA and PCI add-in cards.

However, since the “plug and play” specification

continues to evolve, a flash BIOS provides a cost-

effective capability to update existing PCs. In

addition, the parameter blocks are ideal for storing

the required auto-configuration parameters,

allowing you to integrate the BIOS PROM and

parameter storage EEPROM into a single

component, reducing parts costs while increasing

functionality.

The 4-Mbit flash memory products are also

excellent design solutions for digital cellular phone

and telecommunication switching applications

requiring very low power consumption, high-

performance, high-density storage capability,

modular software designs, and a small form factor

package. The 4-Mbit’s blocking scheme allows for

easy segmentation of the embedded code with

16 Kbytes of hardware-protected boot code, four

main blocks of program code and two parameter

blocks of 8 Kbytes each for frequently updated data

storage and diagnostic messages (e.g., phone

numbers, authorization codes).

Intel’s boot block architecture provides a flexible

voltage solution for the different design needs of

various applications. The asymmetrically-blocked

memory map allows the integration of several

memory components into a single flash device. The

boot block provides a secure boot PROM; the

parameter blocks can emulate EEPROM

functionality for parameter store with proper

software techniques; and the main blocks provide

code and data storage with access times fast

enough to execute code in place, decreasing RAM

requirements.

1.4

Pinouts

Intel’s SmartVoltage Boot Block architecture

provides upgrade paths in every package pinout to

the 8-Mbit density. The 28F004B 40-lead TSOP

pinout for space-constrained designs is shown in

Figure 3. The 28F400 44-lead PSOP pinout follows

the industry-standard ROM/EPROM pinout, as

shown in Figure 4. For designs that require x16

operation but have space concerns, refer to the

48-lead pinout in Figure 5. Furthermore, the 28F400

56-lead TSOP pinout shown in Figure 6 provides

density upgrades to future higher density boot block

memories.

Pinouts for the corresponding 2-Mbit and 8-Mbit

components are also provided for convenient

reference. 4-Mbit pinouts are given on the chip

illustration in the center, with 2-Mbit and 8-Mbit

pinouts going outward from the center.

4-MBIT SmartVoltage BOOT BLOCK FAMILY

PRELIMINARY

28F004B

Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

RP#

WE#

WP#

CE#

OE#

GND

28F002B

28F008B

CE#

OE#

GND

RP#

WE#

WP#

RP#

WE#

WP#

CE#

OE#

GND

0530_03

Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications

PA28F400

Boot Block

44-Lead PSOP

0.525" x 1.110"

TOP VIEW

RP#

WE#

BYTE#

GND

DQ /A

-1

28F800 28F200

WP#